Data transmission / reception circuit and display device including the same

Abstract

The present disclosure relates to a data transmission / reception circuit and a display apparatus including the same. The display apparatus includes a display panel configured to display an image, a timing controller configured to control the display panel, a memory operated in association with the timing controller, and a data transmission / reception circuit configured to write data into or read data from the memory under control of the timing controller, wherein the data transmission / reception circuit includes a transmission direction setting unit configured to set a data transmission / reception path according to a data transmission period or a data reception period to avoid a conflict between input and output during data transmission / reception.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0194567, filed on December 31, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to data transmission / reception circuits and display devices including such data transmission / reception circuits. Background Technology

[0004] With the development of information technology, the market for display devices, which serve as a connection medium between users and information, is growing. Therefore, there is an increasing use of display devices such as light-emitting diode (LED) displays, quantum dot (QOD) displays, and liquid crystal displays (LCDs).

[0005] The aforementioned display device includes a display panel containing sub-pixels, a driver that outputs drive signals for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

[0006] In the above-described display device, when driving signals, such as scan signals and data signals, are supplied to sub-pixels formed in the display panel, the selected sub-pixels emit light or emit light directly, thereby displaying an image. Summary of the Invention

[0007] Therefore, this disclosure provides an apparatus that allows for remote data transmission / reception and stable communication between a timing controller and a memory, thereby increasing flexibility in assembling and modularizing the apparatus and overcoming the inconvenience of having to replace the memory of a neighboring timing controller in the event of a timing controller failure.

[0008] To achieve these and other advantages, and in accordance with this disclosure, as implemented and broadly described herein, the display device includes: a display panel configured to display an image; a timing controller configured to control the display panel; a memory operating in association with the timing controller; and data transmission / reception circuitry configured to write data to or read data from the memory under the control of the timing controller, wherein the data transmission / reception circuitry includes a transmission direction setting unit configured to set a data transmission / reception path according to a data transmission period or a data reception period to avoid conflicts between inputs and outputs during data transmission / reception.

[0009] The transmission direction setting unit may include multiple tri-state buffers, and the transmission / reception path is set according to the logic state of the enable signal applied to the enable terminal of the multiple tri-state buffers.

[0010] Multiple tri-state buffers may include a data transmit tri-state buffer enabled when sending data and a data receive tri-state buffer enabled when receiving data.

[0011] The data transmission / reception circuit may include: a first interface configured to transmit data signals from a timing controller to a memory; and a second interface configured to transmit data signals from the memory to the timing controller, wherein an enable signal may be output from one of the first and second interfaces.

[0012] The data transmission / reception circuit may include: a first data format converter configured to receive a signal sent from a timing controller, convert a serial data signal from the signal sent from the timing controller into a parallel data signal, and output a parallel data signal; and a second data format converter configured to receive a signal sent from a memory, convert a parallel data signal from the signal sent from the memory into a serial data signal, and output a serial data signal.

[0013] The second data format converter can convert parallel data signals into serial data signals based on the clock signal output from the first data format converter.

[0014] When performing irregular operations, including memory read, write, and erase operations, the timing controller and data transmit / receive circuitry can perform clock training.

[0015] The display device may further include a first communication line between the timing controller and the data transmission / reception circuit and a second communication line between the data transmission / reception circuit and the memory, wherein the first communication line may be selected as a differential signal line that allows remote data transmission and reception.

[0016] In another aspect of this disclosure, the data transmission / reception circuit includes: a first data format converter configured to receive a signal transmitted from a first external device, convert a serial data signal in the signal transmitted from the first external device into a parallel data signal, and output a parallel data signal; a second data format converter configured to receive a signal transmitted from a second external device, convert the parallel data signal in the signal transmitted from the second external device into a serial data signal, and output a serial data signal; a first interface configured to operate to transmit a data signal transmitted from the first external device to the second external device; a second interface configured to operate to transmit a data signal transmitted from the second external device to the first external device; and a transmission direction setting unit configured to set a data transmission / reception path according to a data transmission period or a data reception period to avoid input and output conflicts during data transmission / reception between the first external device and the second external device.

[0017] The transmission direction setting unit may include multiple tri-state buffers, and sets the data transmission / reception path according to the logic state of the enable signals applied to the enable terminals of the multiple tri-state buffers.

[0018] Multiple tri-state buffers may include a data transmit tri-state buffer that is enabled when transmitting data and a data receive tri-state buffer that is enabled when receiving data, and the enable signal may be output from one of the first interface and the second interface.

[0019] The second data format converter can convert parallel data signals into serial data signals based on the clock signal output from the first data format converter. Attached Figure Description

[0020] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated into and constitute a part of this disclosure. The drawings illustrate various aspects of this disclosure and, together with the description, serve to illustrate the principles of this disclosure.

[0021] In the attached diagram:

[0022] Figure 1 It is a schematic block diagram showing a light-emitting display device, and Figure 2 It is shown schematically. Figure 1 The diagram shows the configuration of the sub-pixels;

[0023] Figures 3 to 5 This is a diagram used to describe the configuration of the gate-type gate driver within the panel;

[0024] Figure 6 This is a module configuration diagram of a light-emitting display device according to an embodiment of the present disclosure;

[0025] Figure 7 This is a module configuration diagram of a light-emitting display device according to another embodiment of the present disclosure;

[0026] Figure 8 This is a diagram used to briefly describe the process related to data transmission / reception of a light-emitting display device according to one aspect of this disclosure;

[0027] Figure 9 This is a diagram used to describe read and write operations of a memory according to one aspect of this disclosure;

[0028] Figure 10 It is used to briefly describe the process of execution. Figure 9 A diagram illustrating the protocol of the operation shown;

[0029] Figure 11This is a block diagram used to briefly describe a data transmission / reception circuit according to one aspect of this disclosure.

[0030] Figure 12 It is a block diagram used to describe in more detail a data transmission / reception circuit according to one aspect of this disclosure;

[0031] Figure 13 This is a diagram showing the symbols and truth table of the tri-state buffer included in the transmit direction setting unit;

[0032] Figure 14 and Figure 15 This is a diagram illustrating the patterns based on the operating states of a three-state buffer; and

[0033] Figure 16 and Figure 17 This is a diagram illustrating examples of request signals used to perform read and write operations on memory. Detailed Implementation

[0034] The display device according to this disclosure can be implemented as a television, video player, personal computer (PC), home theater, automotive electrical system, smartphone, etc., but this disclosure is not limited thereto. The display device according to this disclosure can be implemented as a light-emitting display (LED) device, a quantum dot display (QOD) device, a liquid crystal display (LCD) device, etc. However, for ease of description, a light-emitting display device based on direct light emission from inorganic or organic light-emitting diodes will be illustrated below.

[0035] Figure 1 It is a schematic block diagram showing a light-emitting display device, and Figure 2 It is shown schematically. Figure 1 The diagram shows the configuration of the sub-pixels.

[0036] like Figure 1 and Figure 2 As shown, the light-emitting display device may include an image provider 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power supply 180, etc.

[0037] Image provider (collection or main system) 110 can output various drive signals along with image data signals supplied from an external source or stored in internal memory. Image provider 110 can supply data signals and various drive signals to timing controller 120.

[0038] The timing controller 120 can output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals.

[0039] The timing controller 120 can supply the data signal DATA supplied from the image provider 110, along with the data timing control signal DDC, to the data driver 140. The timing controller 120 may be in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0040] The gate driver 130 can output a gate signal (or gate voltage) in response to a gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 can supply the gate signal to the sub-pixels included in the display panel 150 through gate lines GL1 to GLm. The gate driver 130 can be in the form of an IC, or it can be directly formed on the display panel 150 as an in-panel gate structure, but is not limited thereto.

[0041] The data driver 140 can sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driver 140 can supply the data voltage to the sub-pixels included in the display panel 150 via data lines DL1 to DLn. The data driver 140 can be in the form of an IC and mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

[0042] Power supply 180 can generate high-level voltages and low-level voltages based on externally supplied power input, and output the high-level voltages and low-level voltages through the first power line EVDD and the second power line EVSS. Power supply 180 can generate and output voltages necessary to drive gate driver 130 (e.g., gate voltages including gate high voltage and gate low voltage) and voltages necessary to drive data driver 140 (drain voltages including drain voltage and half-drain voltage), as well as high-level voltages and low-level voltages.

[0043] The display panel 150 can display images in response to drive signals including gate signals and data voltages, and drive voltages including high-level voltages and low-level voltages. The sub-pixels of the display panel 150 emit light directly. The display panel 150 can be manufactured based on a substrate that is rigid or flexible, such as glass, silicon, or polyimide. Furthermore, the light-emitting sub-pixels can include red, green, and blue pixels, or red, green, blue, and white pixels.

[0044] For example, a sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and can include pixel circuitry comprising a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode (OLED), etc. Since the sub-pixel SP in a light-emitting display device emits light directly, the circuit configuration is complex. Furthermore, various compensation circuits exist to compensate for degradation of the driving transistor and the OLED, the driving transistor being used to supply the drive current necessary to drive the OLED to emit light. Therefore, note that the sub-pixel SP is simply shown in block form.

[0045] Meanwhile, in the above description, the timing controller 120, gate driver 130, data driver 140, etc., are described as single components. However, depending on the implementation method of the light-emitting display device, one or more of the timing controller 120, gate driver 130, and data driver 140 can be integrated into a single IC.

[0046] Figures 3 to 5 This is a diagram used to describe the configuration of the gate-type gate driver within the panel.

[0047] like Figure 3 As shown, the in-panel gate-type gate driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a clock signal Clk and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply 180. The clock signal Clk may be generated in the form of J different phases (J is an integer equal to or greater than 2), such as 2 phases, 4 phases, or 8 phases. The shift register 131 may output gate signals Gout[1] to Gout[m] based on the clock signal Clk and the start signal Vst output from the level shifter 135.

[0048] like Figure 3 and Figure 4 As shown, unlike shift register 131, level shifter 135 can be configured as an independent IC or may be included in power supply 180. However, this is merely an example and the scope of this disclosure is not limited thereto.

[0049] like Figure 5 As shown, the display panel 150 includes a display area AA and a non-display area NA. Shift registers 131a and 131b, which output gate signals in an in-panel gate-type gate driver, can be disposed in the non-display area NA of the display panel 150. Shift registers 131a and 131b can be formed as thin films on the display panel 150 as an in-panel gate structure. Although an example is shown in which shift registers 131a and 131b are disposed in the left and right non-display areas NA, the present disclosure is not limited thereto.

[0050] Figure 6 This is a module configuration diagram of a light-emitting display device according to a first embodiment of the present disclosure, and Figure 7 This is a module configuration diagram of a light-emitting display device according to a second embodiment of the present disclosure.

[0051] like Figure 6 and Figure 7 As shown, the display panel 150 may have multiple sub-pixels SP. Multiple data drivers 140 may be mounted on multiple flexible printed circuit boards 145 respectively. The multiple flexible printed circuit boards 145 may be connected to multiple printed circuit boards 148. The timing controller 120 may be mounted on the main board 125. The main board 125 and the multiple printed circuit boards 148 may be electrically connected via connectors (or cables) 126.

[0052] According to the first embodiment, the memory 160 and the data transmission / reception circuitry 170 may be disposed on one of a plurality of printed circuit boards 148. According to the second embodiment, the memory 160 may be disposed on one of a plurality of printed circuit boards 148, and the data transmission / reception circuitry 170 may be embedded in a data driver 140 adjacent to the memory 160.

[0053] According to the first and second embodiments, the data transmission / reception circuit 170 is configured between the timing controller 120 and the memory 160 to realize a NAND (NSP) structure on the source PCB that allows for remote communication. The NSP structure allows for remote data transmission / reception between the timing controller 120 and the memory 160, increasing flexibility when assembling the device and modularizing it. Furthermore, the NSP structure overcomes the disadvantage that in the event of a failure of the timing controller 120 formed on the motherboard 125, the memory 160, which is located adjacent to the timing controller 120, must be replaced. Additionally, the NSP structure allows for the separate packaging of the motherboard 125 and other components, thereby reducing packaging and logistics costs.

[0054] The memory 160 can be selected as an embedded NAND flash memory (e-MMC), etc. The data transmit / receive circuit 170 can be used as a data relay to allow remote data transmission / reception between the timing controller 120 and the memory 160.

[0055] The data transmit / receive circuit 170 can provide a bidirectional data transmit / receive path, through which data can be transmitted and received via a first communication line DFSL coupled to the timing controller 120 and a second communication line SESL coupled to the memory 160. The data transmit / receive circuit 170 can be implemented based on a differential buffer.

[0056] A first communication line DFSL can be selected as a differential signal line through which remote data transmission / reception can be performed, and a second communication line SESL can be selected as a signal line different from the first communication line DFSL through which short-range data transmission / reception can be performed. The second communication line SESL can be varied depending on the method of sending / receiving data to / from the memory.

[0057] Meanwhile, the memory 160 can store compensation data for compensating for the degradation of components (e.g., driving transistors, organic light-emitting diodes, etc.) included in the display panel 150, and initial compensation data (initial values ​​before degradation) of the components (driving transistors, organic light-emitting diodes, etc.).

[0058] Figure 6 and Figure 7 An example is shown in which the flexible circuit board 145, printed circuit board 148, connector 126, and main board 125 are connected to the display panel 150. However, this is only an example, and more circuit boards or flexible boards can be added between them depending on the size of the light-emitting display device. Furthermore, the first communication line DFSL connecting the timing controller 120 and the data transmission / reception circuit 170 can be configured as a separate cable.

[0059] Figure 8 This is a diagram used to briefly describe the flow related to data transmission / reception of a light-emitting display device according to one aspect of this disclosure. Figure 9 This is a diagram used to describe read and write operations of a memory according to one aspect of this disclosure. Figure 10 It is used to briefly describe the process of execution. Figure 9 The diagram shows the protocol of the operation, and Figure 11 This is a block diagram used to briefly describe a data transmission / reception circuit according to one aspect of this disclosure.

[0060] like Figure 8 As shown, the light-emitting display device according to an aspect of this disclosure can perform the process of reading and writing compensation data stored in NAND flash memory to compensate for elements included in the display panel.

[0061] When the light-emitting display device is powered on (On-RF), clock training and communication with the memory can begin, defining the communication lines used for communication with the memory (S110). Next, a startup mode for memory initialization (NAND initialization) can be executed (S120).

[0062] Next, the communication speed can be changed to a high speed for setting the memory mode (NAND mode) (S130). Then, after reading the compensation data stored in the memory to the timing controller (T-Con), data transfer (data read) can be performed to load the compensation data into the frame memory (DDR) (S140).

[0063] When the above steps are completed, the display panel is driven (RT) or real-time sensing is performed, so that the memory-related device can be switched to sleep mode and enter communication standby state (S150).

[0064] When the light-emitting display device is disconnected (power off (Off-RS)), communication with the memory can begin along with clock training to define the communication lines used for communication with the memory (S160). Next, a memory erase (NAND erase) can be performed to erase unnecessary data stored in the memory (S170).

[0065] Next, data transfer (data writing) can be performed to obtain new compensation data, and the compensation data obtained by the timing controller can be written to the memory (S180).

[0066] like Figure 9 As shown and as described above, the timing controller 120 can perform operations to read data stored in the memory 160 and to write data into the memory 160 associated with the data transmission / reception circuit 170, as described above.

[0067] When performing a read operation to read data stored in memory 160, timing controller 120 may output a request signal for sending command signals and data signals to data transmission / reception circuit 170. Furthermore, when performing a write operation to write data to memory 160, timing controller 120 may output a request signal for performing clock training to data transmission / reception circuit 170.

[0068] like Figure 10 As shown, in order for the timing controller 120 to access the data transmission / reception circuit 170, a first protocol consisting of a request signal REQ, a clock signal CLK, a reset signal RST, a command signal CMD, data signals D0 to D7, and a virtual signal DMY can be used.

[0069] To enable the data transmission / reception circuit 170 to access the timing controller 120, a second protocol consisting of a request signal REQ, a low-level signal L, a command signal CMD, data signals D0 to D7, and a dummy signal DMY can be used.

[0070] The formats of the first and second protocols can be defined in the timing controller 120, and the data transmission / reception circuit 170 can perform corresponding operations to write data to or read data from the memory.

[0071] Although an example where data signals D0 to D7 are 8-bit signals has been described above, this is only an example. Therefore, the number of bits in the data signals is not indicated below.

[0072] like Figure 11 As shown, the data transmission / reception circuit 170 may include a first data format converter (serial-to-parallel) 173, a first interface (I / F1) 177a, a second data format converter (parallel-to-serial) 176, a second interface (I / F2) 177b, a transmission direction setting unit (DIR) 178, and a clock compensator (Comp) 179.

[0073] The first data format converter 173 can receive signals sent from the timing controller (or the first external device) via the first differential signal line RX P / N. The first data format converter 173 can convert the serial data signal sent from the timing controller into a parallel data signal and output the converted signal.

[0074] The first data format converter 173 can generate the interface clock signal ICLK necessary to drive the first interface 177a and the second interface 177b based on the first received clock signal RXCLK extracted from the signal sent from the timing controller. When the interface clock signal ICLK necessary to drive the first interface 177a and the second interface 177b is generated in this way based on the first received clock signal RXCLK extracted from the signal sent from the timing controller, it is not necessary to receive additional clock signals, and therefore additional clock signal lines can be omitted.

[0075] The first interface 177a can be defined as a receiving interface. The first interface 177a can be configured to send a data signal DAT to the memory based on the interface clock signal ICLK and the data signal Dat output from the first data format converter 173. The first interface 177a can output not only the data signal DAT, but also the clock signal CLK, the reset signal RST, and the command signal CMD for sending / receiving data to / from the memory. Here, the command signal CMD can be received from the timing controller, and at least one of the clock signal CLK and the reset signal RST can be received from the timing controller, or at least one of the clock signal CLK and the reset signal RST can be generated by the first interface 177a.

[0076] The second data format converter 176 can send signals to the timing controller via the second differential signal line TX P / N. The second data format converter 176 can convert parallel data signals sent from the memory (or a second external device) into serial data signals.

[0077] The second interface 177b can be defined as a transmit interface. The second interface 177b can be configured with the data signal to be transmitted to the timing controller based on the interface clock signal ICLK output from the first data format converter 173.

[0078] The clock compensator 179 can compensate for the clock signal used for clock training, enabling specific operations to be performed between the data transmission / reception circuit 170 and the timing controller.

[0079] The transmission direction setting unit 178 can set the transmission direction, wherein it outputs a clock signal CLK and a reset signal RST generated from the first interface 177a, and sends or receives a data signal DAT from the memory. The transmission direction setting unit 178 can be used to set the transmission / reception path according to the data transmission period or the data reception period to avoid input and output conflicts during the transmission / reception of the command signal (CMD) and the data signal (DAT).

[0080] The operation of the transmission direction setting unit 178 can be selected in response to the command signal CMD as either a write mode for writing data to memory or a read mode for reading data stored in memory. For example, the transmission direction setting unit 178 can set the transmission / reception path according to the data transmission period or the data reception period in response to a request signal including the command signal (CMD).

[0081] The data transmission / reception circuitry according to one aspect of this disclosure will be described in more detail below, with a focus on more detailed configuration and operation.

[0082] Figure 12 This is a block diagram used to describe in more detail the data transmission / reception circuitry according to aspects of this disclosure. Figure 13 This is a diagram showing the symbols and truth table of the tri-state buffer included in the transmit direction setting unit, and... Figure 14 and Figure 15 This is a diagram illustrating the pattern of operation states based on the three-state buffer.

[0083] like Figure 12As shown, the first data format converter 173 may include: a (1-1) data format converter 171, which includes a data receiver RX, a signal recovery unit CDR, a first signal converter SIPO and a clock distributor CLKDIV; and a (1-2) data format converter 172, which includes a first polarity controller POL1 and a downlink unit DWNSTM.

[0084] The second data format converter 176 may include: a (2-1) data format converter 174, which includes a data transmitter TX and a second signal converter PISO; and a (2-2) data format converter 175, which includes a second polarity controller POL2 and an uplink unit UPSTM.

[0085] The data receiver RX can be used to receive signals transmitted from the timing controller via the first differential signal line RX P / N. The data receiver RX may include an equalizer and be configured to improve consistency and minimize noise during data transmission / reception to / from the timing controller.

[0086] The signal recovery unit (CDR) can be used to extract (separate) and recover the clock signal and serial data signal from the signal transmitted from the data receiver (RX). The serial data signal output from the signal recovery unit (CDR) can be sent to the first signal converter (SIPO), and the first receive clock signal (RXCLK) can be sent to the clock distributor (CLKDIV). Furthermore, the first receive clock signal (RXCLK) output from the signal recovery unit (CDR) can be sent to the uplink unit (UPSTM).

[0087] The first signal converter (SIPO) can be used to convert the serial data signal output from the signal recovery unit (CDR) into a parallel data signal.

[0088] The clock distributor CLKDIV can be used to generate a second receive clock signal RXCLK_OUT, which is used to drive the first signal converter SIPO and the downlink unit DWNSTM based on the first receive clock signal RXCLK output from the signal recovery unit CDR. The clock distributor CLKDIV may include clock distributor circuitry that distributes clock signals based on the first receive clock signal RXCLK to generate the second receive clock signal RXCLK_OUT.

[0089] The first polarity controller POL1 can be used to control the polarity of the parallel data signal output from the first signal converter SIPO. Since the parallel data signal output from the first signal converter SIPO is based on differential signal generation and reception, the first polarity controller POL1 can be used to remove the polarity assigned to the parallel data signal.

[0090] The downlink unit DWNSTM (RX data to downlink PCS block) can perform data decoding to enable the parallel data signal output from the first polarity controller POL1 to be sent downlink in a data format that can be sent to memory. The downlink unit DWNSTM can decode the data signal Dat according to the clock signal CLK. The downlink unit DWNSTM may include an 8-bit or 10-bit decoder for decoding the data signal Dat to be transmitted.

[0091] The data transmitter TX can be used to transmit signals from the memory to the timing controller via the second differential signal line TX P / N. The data transmitter TX can transmit serial data signals output from the second signal converter PISO based on the transmit clock signal TXCLK_OUT output from the uplink unit UPSTM. The data transmitter TX can include and configure pre-emphasis for increasing data transmission capability during data transmission / reception to / from the timing controller. The data transmitter TX can operate based on the clock signal output from the clock distributor CLKDIV, causing data transmission to be performed at a rate matched to the transmission speed of the second differential signal line TX P / N.

[0092] The second signal converter PISO can be used to convert the parallel data signal output from the second polarity controller POL2 into a serial data signal. The second signal converter PISO converts the parallel data signal output from the second polarity controller POL2 into a serial data signal based on the transmit clock signal TXCLK_OUT output from the uplink unit UPSTM.

[0093] The second polarity controller POL2 can be used to control the polarity of the parallel data signal output from the uplink unit UPSTM. Since the parallel data signal output from the uplink unit UPSTM needs to be transmitted based on differential signals, the second polarity controller POL2 can be used to assign polarity to the parallel data signal.

[0094] The uplink unit UPSTM (TX data to the uplink PCS block) can perform data encoding to uplink the parallel data signal output from the second interface 177b to obtain a data format that can be sent to the timing controller. The uplink unit UPSTM can encode the data signal Dat according to the clock signal CLK. The uplink unit UPSTM may include an 8-bit or 10-bit encoder to encode the data signal Dat to be transmitted. The uplink unit UPSTM can generate and output the transmit clock signal TXCLK_OUT based on the first receive clock signal RXCLK sent from the signal recovery unit CDR to drive the data transmitter TX and the second signal converter PISO.

[0095] The first interface 177a can output a clock signal CLK, a reset signal RST, a command signal CMD, and a data signal DAT to / from the memory, based on the data signal Dat and the interface clock signal ICLK output from the downlink unit DWMSTM. The first interface 177a can generate a request signal CT_REQ for performing clock training. The clock training request signal CT_REQ can be generated to perform specific irregular operations, such as read, write, and erase operations, between the data transmit / receive circuitry 170 and the timing controller.

[0096] The clock compensator 179 can compensate the clock signal so that clock training can be performed in response to the clock training request signal CT_REQ output from the first interface 177a.

[0097] The transmit direction setting unit 178 includes a first tri-state buffer TBU1, a second tri-state buffer TBU2, a third tri-state buffer TBU3, a fourth tri-state buffer TBU4, a first inverter INV1, and a second inverter INV2. Although only one second tri-state buffer TBU2 and one fourth tri-state buffer TBU4 are shown for transmitting and receiving the data signal DAT, multiple second tri-state buffers TBU2 and multiple fourth tri-state buffers TBU4 can be configured according to the number of bits in the data signal DAT. For example, when referring to the above... Figure 10 When sending and receiving the 8-bit data signal DAT, eight second-state buffers TBU2 and eight fourth-state buffers TBU4 can be set.

[0098] The first tri-state buffer TBU1 can be enabled or disabled in response to a first enable signal output through the first enable signal line EN1 of the first interface 177a. When the first tri-state buffer TBU1 is enabled, the command signal CMD can be sent to the memory. The second tri-state buffer TBU2 can be enabled or disabled in response to a second enable signal output through the second enable signal line EN2 of the first interface 177a. When the second tri-state buffer TBU2 is enabled, the data signal DAT can be sent to the memory.

[0099] The third tri-state buffer TBU3 can be enabled or disabled in response to the inverted first enable signal output from the first inverter INV1 connected to the first enable signal line EN1. When the third tri-state buffer TBU3 is enabled, the command signal CMD can be received from the memory. The fourth tri-state buffer TBU4 can be enabled or disabled in response to the inverted second enable signal output from the second inverter INV2 connected to the second enable signal line EN2. When the fourth tri-state buffer TBU4 is enabled, the data signal DAT can be received from the memory.

[0100] like Figure 13As shown, the operating state of the tri-state buffer TBU can be determined based on the logic of the enable signal input through the enable terminal En. When the logic of the enable signal input through the enable terminal En is 0, the tri-state buffer TBU is in an operating state in which it cannot output an input signal as an output signal, such as a high-impedance Hi-Z signal. On the other hand, when the logic of the enable signal input through the enable terminal En is 1, the tri-state buffer TBU is in an operating state in which it can output an input signal as an output signal of either 0 or 1.

[0101] like Figure 14 As shown, when the data transmission / reception circuit operates in data transmission mode, the first tri-state buffer TBU1 and the second tri-state buffer TBU2 can be enabled in response to the first enable signal En1[1] and the second enable signal EN2[1] corresponding to logic 1. On the other hand, the third tri-state buffer TBU3 and the fourth tri-state buffer TBU4 can be disabled in response to the first enable signal En1[0] and the second enable signal EN2[0] inverted by the first inverter INV1 and the second inverter INV2 and corresponding to logic 0. Therefore, when the data transmission / reception circuit operates in data transmission mode, only the first tri-state buffer TBU1 and the second tri-state buffer TBU2 can be in an operable state. That is, the first tri-state buffer TBU1 and the second tri-state buffer TBU2 can be defined as tri-state buffers for data transmission.

[0102] like Figure 15 As shown, when the data transmission / reception circuit operates in data reception mode, the first tri-state buffer TBU1 and the second tri-state buffer TBU2 can be disabled in response to the first enable signal En1[0] and the second enable signal EN2[0] corresponding to logic 0. On the other hand, the third tri-state buffer TBU3 and the fourth tri-state buffer TBU4 can be enabled in response to the first enable signal En1[1] and the second enable signal EN2[1] inverted by the first inverter INV1 and the second inverter INV2 and corresponding to logic 1. Therefore, when the data transmission / reception circuit operates in data reception mode, only the third tri-state buffer TBU3 and the fourth tri-state buffer TBU4 can be in an operable state. That is, the third tri-state buffer TBU3 and the fourth tri-state buffer TBU4 can be defined as tri-state buffers for data reception.

[0103] In the following, an example of a request signal for performing read and write operations on a memory using a data transmission circuit unit, according to one aspect of this disclosure, will be described.

[0104] Figure 16 and Figure 17 This is a diagram illustrating examples of request signals used to perform read and write operations on memory.

[0105] like Figure 16 and Figure 17 As shown, the requests to perform a memory read operation (based on the REQ of the memory read operation) and the requests to perform a memory write operation (based on the REQ of the memory write operation) using the data transmission circuit unit can take different forms. The requests to perform memory read and memory write operations can be generated based on the first request signal CMD_REQ, the second request signal DAT_REQ, and the third request signal CT_REQ, as will be described below.

[0106] The first request signal CMD_REQ can be used to distinguish between read and write operations related to the command signal CMD. When the first request signal CMD_REQ is high (CMDREQ = H), the data transmit / receive circuit can send the command signal CMD to the memory. In this case, the data transmit / receive circuit may not receive the command signal from the transmit terminal of the timing controller. When the first request signal CMD_REQ is low (CMD_REQ = L), the data transmit / receive circuit may not send the command signal CMD to the memory. In this case, the data transmit / receive circuit can receive the response command signal CMD (RSP) from the transmit terminal of the timing controller.

[0107] The second request signal DAT_REQ can be used to distinguish between read and write operations related to the data signal DAT. When the second request signal DAT_REQ is high (DAT_REQ = H), the data transmit / receive circuit can send the data signal DAT to the memory. In this case, since the data transmit / receive circuit is in a memory write operation state, it may not receive data from the timer controller's transmit terminal. When the second request signal DATREQ is low (DAT_REQ = L), the data transmit / receive circuit can send the data signal DAT to the memory (memory write operation). In this case, since the data transmit / receive circuit is in a memory read operation state, it can receive data from the timer controller's transmit terminal.

[0108] The third request signal CT_REQ can be used to perform clock training between the timing controller and the data transmit / receive circuitry before performing read, write, or erase operations. The third request signal CT_REQ can be used for stable communication (transmit / receive) of high-rate data. For example, clock training can be performed immediately when the third request signal CT_REQ is high.

[0109] Furthermore, clock training can be performed not only during specific irregular operations such as read, write, and erase operations, but also during the transmission of the data signal DAT to improve data transmission stability. This can be seen from the example shown. Figure 17 It is determined that, in this example, whenever a second request signal DAT_REQ for sending a block of data signal Dat is generated in a high state (DAT_REQ=H), a second request signal DAT_REQ is subsequently generated in a low state (DAT_REQ=L), and a third request signal CT_REQ is generated in a high state (CT_REQ=H).

[0110] As described above, this disclosure provides an apparatus that enables remote data transmission / reception and stable communication between a timing controller and a memory. Furthermore, by enabling remote data transmission / reception between the timing controller and the memory, this disclosure increases the flexibility in assembling and modularizing the apparatus. Additionally, this disclosure overcomes the inconvenience of having to replace the memory of a neighboring timing controller in the event of a timing controller failure.

Claims

1. A display device, comprising: The display panel is configured to display images; A timing controller configured to control the display panel; A memory configured to operate in association with the timing controller; as well as A data transmission / reception circuit configured to write data to or read data from the memory under the control of the timing controller. The data transmission / reception circuit includes a transmission direction setting unit, which is configured to set the data transmission / reception path according to the data transmission period or the data reception period to avoid conflicts between input and output during data transmission / reception. The transmission direction setting unit includes multiple tri-state buffers and is configured to set the data transmission / reception path according to the logic state of the enable signal applied to the enable terminal of the multiple tri-state buffers. The plurality of tri-state buffers include a data transmission tri-state buffer enabled when transmitting data and a data reception tri-state buffer enabled when receiving data; The data transmission / reception circuit further includes: A first interface, configured to operate to transmit data signals from the timing controller to the memory; and The second interface is configured to operate to send data signals from the memory to the timing controller. The enable signal is output from one of the first interface and the second interface; The data transmission / reception circuit further includes: A first data format converter is configured to receive a signal sent from the timing controller, convert a serial data signal in the signal sent from the timing controller into a parallel data signal, and output the parallel data signal; and A second data format converter is configured to receive signals sent from the memory, convert parallel data signals in the signals sent from the memory into serial data signals, and output the serial data signals.

2. The display device according to claim 1, wherein, The second data format converter is configured to convert the parallel data signal into the serial data signal based on a clock signal output from the first data format converter.

3. The display device according to claim 1, wherein, When performing irregular operations including read, write, and erase operations of the memory, the timing controller and the data transmission / reception circuit are configured to perform clock training.

4. The display device according to claim 1, further comprising: A first communication line located between the timing controller and the data transmission / reception circuit; as well as The second communication line is located between the data transmission / reception circuit and the memory. The first communication line is selected as a differential signal line that allows remote data transmission and reception.

5. A data transmission / reception circuit, comprising: A first data format converter is configured to receive a signal transmitted from a first external device, convert a serial data signal in the signal transmitted from the first external device into a parallel data signal, and output the parallel data signal. A second data format converter is configured to receive a signal sent from a second external device, convert a parallel data signal in the signal sent from the second external device into a serial data signal, and output the serial data signal. A first interface is configured to transmit data signals sent from the first external device to the second external device; A second interface is configured to transmit data signals from the second external device to the first external device; as well as The transmission direction setting unit is configured to set the data transmission / reception path according to the data transmission period or the data reception period to avoid input and output conflicts during data transmission / reception between the first external device and the second external device.

6. The data transmission / reception circuit according to claim 5, wherein, The transmission direction setting unit includes multiple tri-state buffers, and sets the data transmission / reception path according to the logic state of the enable signal applied to the enable terminal of the multiple tri-state buffers.

7. The data transmission / reception circuit according to claim 6, wherein, The plurality of tri-state buffers include a data transmission tri-state buffer enabled when transmitting data and a data reception tri-state buffer enabled when receiving data, and the enable signal is output from one of the first interface and the second interface.

8. The data transmission / reception circuit according to claim 5, wherein, The second data format converter is configured to convert the parallel data signal into the serial data signal based on a clock signal output from the first data format converter.

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