Tiled display device

Abstract

A tiled display apparatus includes a plurality of display modules connected to each other by an interface circuit based on a serial communication scheme to divide input image data constituting one screen to display a plurality of module images, and a setting board that checks a module identification number based on a connection order of the plurality of display modules and sets a module image coordinate value corresponding to the module image and image rematching control information for each of the plurality of display modules based on a placement direction of a control printed circuit board (PCB) individually included in each display module.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0194685, filed on December 31, 2021, and Korean Patent Application No. 10-2022-0058046, filed on May 11, 2022, both of which are incorporated herein by reference as fully set forth herein. Technical Field

[0003] This disclosure relates to scalable tiled display devices. Background Technology

[0004] Large-size displays can be used in various fields, such as indoor and outdoor digital advertising. To meet the demand for large-size displays, scalable tiled display devices have been proposed. In tiled display devices, a single screen is configured by connecting multiple display modules, and the desired screen size can be achieved by adjusting the number of display modules connected to each other.

[0005] The input image is displayed on a single screen achieved through the connection of display modules. The resolution of the input image is the sum of the resolutions achievable by the display modules. Each display module divides and displays the input image according to the number of images, with the number of images corresponding to the resolution of the input image. Therefore, module image coordinates and module identification numbers based on the connection location should be pre-set for each display module.

[0006] Several methods have been proposed for setting module image coordinate values ​​and module identifiers for each display module. However, according to these methods, the resources of the display device increase, user convenience decreases, and there is a possibility of connection errors due to staff mistakes. Summary of the Invention

[0007] In order to overcome the above-mentioned problems of related technologies, this disclosure provides a tiled display device that can reduce the resources of display devices associated with setting module image coordinate values ​​and module identification numbers, increase user convenience, and be automatically controlled regardless of the connection scheme.

[0008] To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a tiled display apparatus according to one embodiment of the present disclosure includes a plurality of display modules connected to each other through an interface circuit based on a serial communication scheme to divide input image data constituting one screen to display a plurality of module images, and a setting board checking a module identification number based on a connection order of the plurality of display modules and setting a module image coordinate value and image rematching control information corresponding to the module image for each of the plurality of display modules based on a placement direction of a control printed circuit board (PCB) separately included in each display module.

[0009] A tiled display apparatus according to another embodiment of the present disclosure includes a plurality of display modules connected to each other through an interface circuit based on a serial communication scheme to divide input image data constituting one screen to display a plurality of module images, wherein each of the plurality of display modules includes a control printed circuit board (PCB) and a timing controller dividing the module image into a plurality of sub-images, and a setting board generating a control command signal for causing the timing controller in the plurality of display modules to sequentially generate a module identification number, and setting a module image coordinate value and image rematching control information corresponding to the module image for each display module based on a placement direction of the control printed circuit board (PCB). BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:

[0011] Figure 1 FIG. 1 is a diagram schematically illustrating a tiled display apparatus according to an embodiment of the present disclosure;

[0012] Figure 2 FIG. 2 is a diagram illustrating a connection configuration of a display module included in the tiled display apparatus;

[0013] Figure 3 FIG. 3 is a diagram illustrating a connection configuration of a display module included in the tiled display apparatus; Figure 4

[0014] FIG. 4 is a diagram illustrating a connection configuration of a display module included in the tiled display apparatus; Figure 5

[0015] FIG. 5 is a diagram illustrating an interface connection structure of the tiled display apparatus; Figure 6

[0016] FIG. 6 is a diagram illustrating an interface connection structure of the tiled display apparatus; Figure 7 Figure 8 ​is a diagram illustrating a configuration of an embodiment showing automatic setting of a module identification number for image division in a tiled display device;

[0017] Figure 9 is a diagram illustrating a connection structure between a first option pin and a second option pin of each display module for automatic setting of a module identification number;

[0018] Figures 10A-10D is an exemplary diagram illustrating an informal connection structure between display modules for implementing a tiled display device;

[0019] Figure 11A is a diagram illustrating an example in which an input image and an output image are completely matched with a default allocation order in a default placement structure of a control printed circuit board (PCB);

[0020] Figure 11B is a diagram illustrating an example in which an input image and an output image are not completely matched with a default allocation order in a reverse placement structure of a control printed circuit board (PCB);

[0021] Figures 12A-12B is a diagram illustrating a first embodiment of an overall connection structure of each display module for automatically recognizing a placement direction of a control printed circuit board (PCB);

[0022] Figure 13 and Figure 14 is a diagram illustrating an example in which a control printed circuit board (PCB) is connected to a lower board at each of 0 degrees and 180 degrees of rotation from a specific direction in a display module according to the first embodiment;

[0023] Figure 15 is a diagram illustrating a logic value of a direction recognition pin based on a placement direction of a control printed circuit board (PCB) in a display module according to the first embodiment;

[0024] Figures 16A-16C is a diagram illustrating a second embodiment of an overall connection structure of each display module for automatically recognizing a placement direction of a control printed circuit board (PCB);

[0025] Figures 17-20 is a diagram illustrating an example in which a control printed circuit board (PCB) is connected to a lower board at each of 270 degrees, 90 degrees, 0 degrees, and 180 degrees of rotation from a specific direction in a display module according to the second embodiment;

[0026] Figure 21 is a diagram illustrating a logic value of a first direction recognition pin and a second direction recognition pin based on a placement direction of a control printed circuit board (PCB) in a display module according to the second embodiment;

[0027] Figure 22 and Figure 23FIG. 1 is a diagram illustrating an example of setting module image coordinate values of display modules based on a placement direction of a control PCB in an informal connection structure between the display modules;

[0028] Figure 24 and Figure 25 FIG. 2 is a diagram illustrating a third embodiment of an overall connection structure of each display module for automatically recognizing a placement direction of a control PCB;

[0029] Figure 26 and Figure 27 FIG. 3 is a diagram illustrating a fourth embodiment of an overall connection structure of each display module for automatically recognizing a placement direction of a control PCB;

[0030] Figures 28-31 FIG. 4 is a diagram illustrating an example of input / output image matching based on a placement direction of a control PCB;

[0031] Figure 32 FIG. 5 is a diagram illustrating 4K resolution input image data assigned to display modules having an informal connection structure of Figure 10A FIG. 6 is a diagram illustrating module image data assigned to a first display module and a fifth display module in input image data of

[0032] Figure 33 FIG. 7 is a diagram illustrating a display device according to an embodiment of the present disclosure. Figure 32

[0033] Figure 34 FIG. 8 is a diagram illustrating an automatic control sequence of a tiled display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0035] The advantages and features of the present disclosure and implementations thereof will be clarified through the embodiments described below with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art. In addition, the present disclosure is defined only by the scope of the claims.

[0036] ​The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing various embodiments of the disclosure are merely illustrative and the disclosure is not limited thereto. Throughout the entire description, like reference numerals indicate like elements. Throughout the specification, like elements are denoted by like reference numerals. As used herein, the terms "comprise", "have", "include" and the like are meant to be interpreted inclusively rather than exclusively. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well.

[0037] Even if not explicitly stated, elements in various embodiments of the disclosure should be construed to include an error margin.

[0038] In describing positional relationships, for example, when the positional relationship between two parts is described as "on", "above", "below", and "close to", one or more other parts can be disposed between the two parts, unless "just" or "directly" is used.

[0039] It should be understood that although the terms "first", "second", and the like can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the disclosure.

[0040] In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the gist of the disclosure, the detailed description will be omitted. Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 FIG. 1 is a diagram schematically illustrating a tiled display apparatus 100 according to an embodiment of the disclosure. Figure 2 FIG. 2 is a diagram illustrating a connection configuration of display modules included in the tiled display apparatus 100.

[0042] Referring to Figure 1 and Figure 2 The tiled display apparatus 100 according to an embodiment of the disclosure can include a set plate SET and a plurality of display modules CB. Each of the display modules CB can be referred to as a cabinet.

[0043] The display modules CB can be connected to each other through the serial interface circuit to constitute a large screen. The total resolution of the large screen can be determined as the sum of the unit resolution of each display module CB. For example, in the case where the screen is constituted by eight display modules CB having a unit resolution of 960*1080, the total resolution of the screen can be 3840*2160. In this case, 3840*2160 can be the resolution of the input image data, and 960*1080 can be the resolution of the module image data implemented in one display module CB.

[0044] Each display module CB can be implemented as an electroluminescent display type or a liquid crystal display type, and in the following embodiments, the display module CB is implemented as an embodiment of an electroluminescent display type based on a micro light emitting diode (LED). However, the inventive concept is not limited to the implementation type of the display module CB.

[0045] The display modules CB can perform a target operation (for example, generation of a module identification number, sub-image re-matching, etc.) corresponding to a control command signal input from the setting plate SET, and in order to feedback the execution result to the setting plate SET, the display modules CB can be connected to each other through a first interface circuit based on a bidirectional serial communication scheme. The first interface circuit can be implemented as a bidirectional multi-link interface of a feedback loop type between adjacent display modules CB.

[0046] In addition, the setting plate SET can transmit image data for implementing an input image to the display modules CB through a second interface circuit. The second interface circuit can be an interface circuit based on a serial communication scheme, and can be implemented based on a V-by-One (Vx1) scheme capable of high-speed and large-capacity interface connection.

[0047] The setting plate SET can check the module identification number based on the connection order of the display modules CB, and can set a module image coordinate value and image re-matching control information corresponding to the module image based on the placement direction of the control PCB CPCB individually included in each display module CB and the input / output direction of the module image corresponding to the control PCB CPCB. Accordingly, each display module CB can separate the module image data from the input image data, divide the module image data into sub-image data, and re-match the data based on the image re-matching control information and the module image coordinate value.

[0048] Each display module CB can include a plurality of display panels PNL-A, PNL-B, PNL-C, and PNL-D that divide a module image into sub-images to display the sub-images, a plurality of panel driving circuits to drive the display panels PNL-A, PNL-B, PNL-C, and PNL-D, a timing controller TCON to control the panel driving circuits, and a control PCB CPCB to mount the timing controller TCON. The control PCB CPCB can include a plurality of image output ports TA, TB, TC, and TD to electrically connect the timing controller TCON to the display panels PNL-A, PNL-B, PNL-C, and PNL-D. The image output ports TA, TB, TC, and TD can be connected in parallel to the panel driving circuits of the corresponding display module CB through branch cables CAL.

[0049] The timing controller TCON can be connected to an adjacent display module CB or a setting plate SET through the first interface circuit and the second interface circuit. The timing controller TCON can re-match image data of the sub-images with the image output ports TA, TB, TC, and TD based on image re-matching control information and module image coordinate values set in the setting plate SET. Accordingly, image distortion phenomena, such as image mixing and image inversion that occur when a placement direction of the control PCB CPCB is different from a predetermined default direction, can be prevented. The default direction can be the same as or different from a specific direction (e.g., a forward direction). However, the default direction and the specific direction can be determined based on design specifications.

[0050] The panel driving circuits can each be connected to the plurality of display panels PNL-A, PNL-B, PNL-C, and PNL-D. The panel driving circuits can include a source PCB SPCB connected to the timing controller TCON through the branch cable CAL, a memory circuit MEM mounted on the source PCB SPCB, a conductive film COF electrically connecting the source PCB SPCB to the display panels PNL, a data driver SIC bonded on the conductive film COF, and a gate driver and a power circuit electrically connected to the source PCB SPCB.

[0051] The memory circuit MEM can be a non-volatile memory that stores panel characteristics, and can include a correction value of a gamma setting, a first compensation value to compensate for a driving characteristic / color deviation between pixels, a second compensation value to compensate for a boundary deviation between adjacent display panels PNL-A, PNL-B, PNL-C, and PNL-D, various image quality and driving control data. The memory circuit MEM can be a flash memory and / or an electrically erasable programmable read-only memory (EEPROM). A large amount of data can be stored in the flash memory, and a small amount of data can be stored in the EEPROM.

[0052] Reference Figure 3and Figure 4 A pixel array for reproducing an input image can be provided in each of the display panels PNL. A plurality of pixels can be arranged in the pixel array, and signal lines for driving the pixels can be arranged in the pixel array. The signal lines can include a plurality of data lines DL for supplying a data voltage Vdata to the pixels, a plurality of gate lines GL for supplying a gate signal GSIG to the pixels, and a plurality of power lines for supplying a source voltage to the pixels.

[0053] Each of the pixels can include a micro LED chip (μLED chip) as a light emitting device EL. The plurality of micro LED chips (μLED chips) can include a red chip (μLED chip_R), a green chip (μLED chip_G), and a blue chip (μLED chip_B) provided on a thin film transistor (TFT) backplane. A red (R) pixel can include the red chip (μLED chip_R) as the light emitting device EL, a green (G) pixel can include the green chip (μLED chip_G) as the light emitting device EL, and a blue (B) pixel can include the blue chip (μLED chip_B) as the light emitting device EL.

[0054] The micro LED chips (μLED chips) can be transferred from R donors / G donors / B donors, and thus can be mounted on the TFT backplane. The red chip (μLED chip_R) can be transferred from the R donor, the green chip (μLED chip_G) can be transferred from the G donor, and the blue chip (μLED chip_B) can be transferred from the B donor. The transfer technique can use an electrostatic force, a laser, a speed-dependent viscous force, and a load-dependent viscous force. The transfer technique is not limited thereto, and a self-assembly based on an electrostatic force can be used.

[0055] The TFT backplane can be implemented in an active matrix structure to enable effective driving. In the TFT backplane, the pixels can be defined by the data lines DL, the gate lines GL, and the power lines.

[0056] The plurality of pixels can constitute one unit pixel. For example, the R pixel, the G pixel, and the B pixel arranged adjacent to each other can constitute one unit pixel in an extension direction of the gate lines GL or an extension direction of the data lines DL.

[0057] As shown in FIG. 1A, the pixel PXL can include a light emitting device EL, a driving TFT DT, and a node circuit NCON. Figure 5

[0058] ​The node circuit NCON can be connected to the gate line GL and the data line DL. The node circuit NCON can be supplied with the data voltage Vdata through the data line DL, and can be supplied with the gate signal GSIG through the gate line GL. The node circuit NCON can apply the data voltage Vdata to the gate of the drive TFT DT in synchronization with the gate signal GSIG, and thus, can set the gate-source voltage of the drive TFT DT based on a condition for generating a drive current. The node circuit NCON can include an internal compensation circuit that senses and compensates for a threshold voltage and / or electron mobility of the drive TFT DT.

[0059] The drive TFT DT can be a drive element that generates a drive current based on its gate-source voltage. The gate electrode of the drive TFT DT can be connected to the node circuit NCON, the first electrode (drain electrode) of the drive TFT DT can be connected to the high-level pixel power VDD, and the second electrode (source electrode) of the drive TFT DT can be connected to the light emitting device EL.

[0060] The light emitting device EL can be a light emitting device that emits light having an intensity corresponding to the drive current input to the drive TFT DT. The light emitting device EL can be implemented using a micro-LED including an inorganic light emitting layer. The first electrode of the light emitting device EL can be connected to the drive TFT DT, and the second electrode of the light emitting device EL can be connected to the low-level pixel power VSS.

[0061] The connection configuration and operation of one pixel PXL are merely embodiments, and the concept of the disclosure is not limited thereto. For example, each of the drive TFT DT and the node circuit NCON can be implemented based on a PMOS transistor, or can be implemented based on an NMOS transistor. Furthermore, a plurality of gate lines GL connected to the node circuit NCON can be provided.

[0062] Figure 6 FIG. 1 is a diagram illustrating an interface connection structure of a tiled display apparatus.

[0063] Referring to Figure 6 The first interface circuit of the setting plate SET connected to the first to nth timing controllers TCON#1 to TCON#n of the display module can be implemented as a bidirectional dual serial peripheral interface (SPI). Separate bidirectional serial communication between the display modules CB can be performed through the first interface circuit, and thus, a short communication line can be secured, and the speed and reliability of high-capacity data communication based on the short communication line can be enhanced.

[0064] In order to implement the bidirectional dual SPI, each of the first to nth timing controllers TCON#1 to TCON#n can include a first master port, a first slave port, a second master port, and a second slave port.

[0065] The first master port and the first slave port can be used to transmit a control command signal (e.g., CMD) to an adjacent timing controller through a forward SPI (F-SPI). The second master port and the second slave port can be used to transmit a control response signal (e.g., ACK) to the adjacent timing controller through a reverse SPI (R-SPI). Figure 7 Figure 7

[0066] Referring to Figure 6 , the second interface circuit of the first to nth timing controllers TCON#1 to TCON#n connected to the setting board SET can be implemented based on a unidirectional V-by-One (Vx1) scheme capable of high-speed and large-capacity data interface connection.

[0067] Figure 7 and Figure 8 are diagrams illustrating a configuration of an embodiment of automatically setting a module identification number for image division in a tiled display apparatus.

[0068] Referring to Figure 7 , the first to nth timing controllers TCON#1 to TCON#n can sequentially generate a module identification number in response to a control command signal CMD through the first interface circuit, and can feed back a control response signal ACK including a result thereof to the setting board SET through the first interface circuit. Such an "automatic nID setting process" can be performed in a power-on sequence period. The power-on sequence period can be a time from when power-on operation power is applied until a display screen is displayed in the tiled display apparatus.

[0069] The "automatic nID setting process" will be described below with reference to Figure 8

[0070] The control command signal CMD generated by the setting board SET can be sequentially updated and transmitted to the first to eighth timing controllers TCON#1 to TCON#8 through the forward SPI. The 1 data transmission packet can be divided into a header region H, a data region D, and an information region I, and the control command signal CMD for generating a module identification number can be located in the header region H. Each of the first to eighth timing controllers TCON#1 to TCON#8 can check the automatic nID generation command signal and the nID setting value in the header region H to generate its module identification number. In addition, each of the first to seventh timing controllers TCON#1 to TCON#7 can add 1 to its nID value to update the nID setting value of the header region H, and then, can transmit the new nID setting value to a subsequent timing controller.

[0071] ​​​The control response signal ACK generated by each of the first to eighth timing controllers TCON#1 to TCON#8 can be transmitted to the setting board SET through a reverse SPI. The control response signal ACK can be located in a header region H of a 1 data transmission packet. Each of the first to eighth timing controllers TCON#1 to TCON#8 can check an ACK command signal in the header region H to generate its control response signal ACK, update the control response signal ACK to the header region H, and transmit the control response signal ACK to a subsequent timing controller.

[0072] The setting board SET can check the control response signal ACK, and when the control response signal ACK is normal, the setting board SET can end the "automatic nID setting process".

[0073] The setting board SET can perform an "automatic image coordinate recognition process" after the "automatic nID setting process" ends. The "automatic image coordinate recognition process" can be a process of setting a module image coordinate value corresponding to a module image and image rematching control information for each display panel based on a placement direction of a control PCB separately included in each display module. The "automatic image coordinate recognition process" can be performed in a power-on sequence period.

[0074] Figure 9 FIG. 1 is a diagram illustrating a connection structure between a first option pin and a second option pin of each display module for automatically setting a module identification number.

[0075] Referring to Figure 9 The first to nth timing controllers TCON#1 to TCON#n can be mounted on the first to nth control PCBs CPCB1 to CPCBn, respectively. Among the first to nth timing controllers TCON#1 to TCON#n, the first timing controller TCON#1 can be a first timing controller connected to the setting board SET, and the nth timing controller TCON#n can be a last timing controller. For the "automatic nID setting process", the setting board SET can automatically recognize at least a connection position between the first timing controller TCON#1 and the nth timing controller TCON#n.

[0076] To this end, the first timing controller TCON#1 can include a first option pin S-Pin1 connected to a high logic power supply (3.3V) and a second option pin S-Pin2 connected to the high logic power supply (3.3V). The setting board SET can recognize that the first timing controller TCON#1 is the first timing controller directly connected to the setting board SET based on a logic combination "11" of the first option pin S-Pin1 and the second option pin S-Pin2 of the first timing controller TCON#1.

[0077] Further, the nth timing controller TCON#n can include a first option pin S-Pin1 connected to a low logic power (GND) and a second option pin S-Pin2 which is floating. The nth timing controller TCON#n can recognize a floating voltage of the second option pin S-Pin2 as a low logic voltage. The setting board SET can recognize that the nth timing controller TCON#n is the last timing controller based on a logic combination "00" of the first option pin S-Pin1 and the second option pin S-Pin2 of the nth timing controller TCON#n.

[0078] Further, the second to (n-1)th timing controllers TCON#2 to TCON#n-1 other than the first timing controller TCON#1 and the nth timing controller TCON#n can include a first option pin S-Pin1 connected to a low logic power (GND) and a second option pin S-Pin2 connected to a high logic power (3.3V). The nth timing controller TCON#n can recognize a floating voltage of the second option pin S-Pin2 as a low logic voltage. The setting board SET can recognize that the second to (n-1)th timing controllers TCON#2 to TCON#n-1 are timing controllers disposed between the first timing controller and the last timing controller based on a logic combination "01" of the first option pin S-Pin1 and the second option pin S-Pin2 of each of the second to (n-1)th timing controllers TCON#2 to TCON#n-1.

[0079] Figures 10A-10D is a schematic diagram for implementing an informal connection structure between display modules of a tiled display device.

[0080] Referring to Figures 10A-10D , based on a connection position of the setting board SET and a method of a manufacturing system, a connection structure between display modules can be informal.

[0081] The display module can display a module image divided according to an input image. Control PCBs included in the display module can be electrically connected to each other through interface cables CBL. Timing controllers TCON#1 to TCON#8 mounted on the control PCBs can be connected to panel driving circuits through internal interface lines. An input / output direction of image data can be designed to be fixed in the control PCBs so that the internal interface lines are not twisted in a connected state in which the display modules are connected to each other. That is, with respect to the control PCBs arranged in a forward direction, the control PCBs can be designed so that image data is input from a left side direction of the control PCB to the timing controllers and is output from the timing controllers in a right side direction of the control PCB. Based on the input / output direction of the image data corresponding to the control PCBs and a length of the interface cable CBL between adjacent timing controllers, the control PCBs arranged in odd-numbered rows can be arranged in a first direction, and the control PCBs arranged in even-numbered rows can be arranged in a second direction opposite to the first direction.

[0082] For example, as shown in FIG. 1, Figure 10A The control PCBs arranged in the first row (corresponding to TCON#1 to TCON#4) can be arranged in a forward direction, and the control PCBs arranged in the second row (corresponding to TCON#5 to TCON#8) can be arranged in a reverse direction. The setting plate SET can determine a placement direction of the control PCBs based on logic value information of direction identification pins provided in the timing controllers of the control PCBs. The setting plate SET can set module image coordinate values (1, 1) to (2, 4) and image rematching control information corresponding to the module images based on module identification numbers nID 1 to nID 8 assigned to the timing controllers TCON#1 to TCON#8 and the placement direction in which the control PCBs are arranged. When the module image coordinate value is “(a, b)”, “a” can represent a row coordinate in which the module image is located in the input image, and “b” can represent a column coordinate in which the module image is located in the input image. In this case, the module image coordinate value (1, 1) can be set in the first display module including the first timing controller TCON#1, and the module image coordinate value (2, 4) can be set in the fifth display module including the fifth timing controller TCON#5. When the total resolution of the input image is 3840*2160, the module image coordinate value (1, 1) can represent a module image having unit horizontal resolution X “1 to 960” and unit vertical resolution Y “1 to 1080”, and the module image coordinate value (2, 4) can represent a module image having unit horizontal resolution X “2881 to 3840” and unit vertical resolution Y “1081 to 2160”.

[0083] In addition, as shown in FIG. 2, Figure 10BAs shown, the control PCBs arranged in the first row (corresponding to TCON#5 to TCON#8) can be arranged in a forward direction, and the control PCBs arranged in the second row (corresponding to TCON#1 to TCON#4) can be arranged in a reverse direction. The setting plate SET can determine the placement direction of the control PCBs based on the logic value information of the direction recognition pin set in the timing controller of the control PCB. In this case, the module image coordinate value (2, 4) can be set in the first display module including the first timing controller TCON#1, and the module image coordinate value (1, 1) can be set in the fifth display module including the fifth timing controller TCON#5. When the total resolution of the input image is 3840*2160, the module image coordinate value (1, 1) can represent a module image having a unit horizontal resolution X "1 to 960" and a unit vertical resolution Y "1 to 1080", and the module image coordinate value (2, 4) can represent a module image having a unit horizontal resolution X "2881 to 3840" and a unit vertical resolution Y "1081 to 2160".

[0084] In addition, as Figure 10C shown, the control PCBs arranged in the odd-numbered rows (corresponding to TCON#3, TCON#4, TCON#7, and TCON#8) can be arranged in a forward direction, and the control PCBs arranged in the even-numbered rows (corresponding to TCON#1, TCON#2, TCON#5, and TCON#6) can be arranged in a reverse direction. The setting plate SET can determine the placement direction of the control PCBs based on the logic value information of the direction recognition pin set in the timing controller of the control PCB. In this case, the module image coordinate value (4, 2) can be set in the first display module including the first timing controller TCON#1, and the module image coordinate value (2, 2) can be set in the fifth display module including the fifth timing controller TCON#5.

[0085] Based on the same method, as Figure 10D shown, the module image coordinate value (2, 2) can be set in the first timing controller TCON#1, the module image coordinate value (2, 1) can be set in the second timing controller TCON#2, the module image coordinate value (1, 1) can be set in the third timing controller TCON#3, and the module image coordinate value (1, 2) can be set in the fourth timing controller TCON#4.

[0086] In Figures 10A-10DIn the middle, the module image can be reassigned to four image output ports installed in the control PCB, and thus, can be divided and displayed in four display panels. The operation of dividing one module image into four sub-images can be performed in all timing controllers. The sub-image rematching operation can be performed only by a specific timing controller to prevent an image inversion / mixing phenomenon from occurring when a module image is divided into sub-images. That is, the sub-image rematching operation can be performed based on image rematching control information input from the setting board SET, and can be related to a control PCB arranged in only a direction different from a predetermined default direction. Each of the timing controllers installed on the control PCB arranged in a direction different from the default direction can be reassigned to the four image output ports differently from a predetermined default assignment order, thereby preventing image distortion.

[0087] Figure 11A is a diagram illustrating an example in which an input image and an output image are completely matched with a default assignment order in a default placement structure of a control PCB. Figure 11B is a diagram illustrating an example in which an input image and an output image are not completely matched with a default assignment order in a reverse placement structure of a control PCB.

[0088] In Figure 11A and Figure 11B , the default direction can be a forward direction. In Figure 11A and Figure 11B , "EPI-1, EPI-2, and EPI-3" can each be an internal interface line for data communication between a timing controller TCON and a panel driving circuit.

[0089] Referring to Figure 11A , when a module image MI is input to a display module in which a control PCB CPCB is arranged in a default direction, a timing controller TCON can divide the module image MI into four sub-images A, B, C, and D, and can assign the sub-images A, B, C, and D to four output ports based on a default assignment order.

[0090] Referring to Figure 11B , when a module image MI is input to a display module in which a control PCB CPCB is arranged in a direction rotated 180 degrees from a default direction, a timing controller TCON can divide the module image MI into four sub-images A, B, C, and D, and can assign the sub-images A, B, C, and D to four output ports differently from a default assignment order.

[0091] According to the default assignment order TA[A], TB[B], TC[C], TD[D], the timing controller TCON can output the sub-image A to the first display panel PNL-A through the first output port TA, output the sub-image B to the second display panel PNL-B through the second output port TB, output the sub-image C to the third display panel PNL-C through the third output port TC, and output the sub-image D to the fourth display panel PNL-D through the fourth output port TD.

[0092] Referring to Figure 11A , the output image realized in the display panel can be completely matched with the input module image MI. That is, the module image MI can be completely displayed by the four display panels without image inversion or image mixing. Therefore, as shown in Figure 11A , in the display module in which the control PCB CPCB is arranged in the default direction, the sub-image re-matching operation can not be performed. In this case, the image data of the sub-images can be assigned to the first to fourth output ports TA, TB, TC, and TD in the same default assignment order.

[0093] On the other hand, according to Figure 11B , the output image realized in the display panel can not be matched with the input module image MI. That is, the input module image MI can be displayed by the four display panels with inversion. Therefore, as shown in Figure 11B , in the display module in which the control PCB CPCB is arranged in a direction rotated by 180 degrees from the default direction, the sub-image re-matching operation can be required to eliminate the image inversion, and the image data of the sub-images can be assigned to the first to fourth output ports TA, TB, TC, and TD differently from the default assignment order. In other words, the sub-image A can be re-matched to the fourth output port TD, the sub-image B can be re-matched to the third output port TC, the sub-image C can be re-matched to the second output port TB, and the sub-image D can be re-matched to the first output port TA.

[0094] Figures 12A-12B is a diagram illustrating a first embodiment of an overall connection structure of each display module for automatically recognizing a placement direction of a control PCB. Figure 13 and Figure 14 are diagrams illustrating examples in which the control PCB is connected to a lower plate at each of 0 degrees and 180 degrees of rotation from a specific direction in the display module according to the first embodiment. Figure 15 is a diagram illustrating a logic value of a direction recognition pin based on a placement direction of a control PCB in a display module according to the first embodiment.

[0095] Referring to Figures 12A-12B , each display module can further include a lower plate Lplate coupled to a rear surface of the control PCB CPCB.

[0096] The timing controller TCON can be mounted on the control PCB CPCB. The timing controller TCON can be fixed to the control PCB CPCB, and thus, a placement direction of the timing controller TCON can be changed based on a placement direction of the control PCB CPCB. To represent two placement directions of the control PCB CPCB, a first direction identification pin D-Pin can be included in the timing controller TCON. The first direction identification pin D-Pin can represent two pieces of direction information (e.g., forward placement direction information and reverse placement direction information) having different logic values based on the placement direction of the control PCB CPCB.

[0097] A plurality of sub-holes FH for coupling to the lower plate Lplate and a first power connection hole DH for connection to a high logic power source can be formed in the control PCB CPCB. The first power connection hole DH can be formed at a first upper position close to a region in which the timing controller TCON is mounted. The first power connection hole DH can be connected to the first direction identification pin D-Pin of the timing controller TCON through a first power line PL1 and can be connected to the high logic power source (3.3 V) through a second power line PL2.

[0098] Regardless of a change in the placement direction of the control PCB CPCB, the lower plate Lplate can be coupled to the control PCB CPCB with being fixed to a specific direction (e.g., a forward direction). A first coupling socket DSK can be disposed at a first lower position of the lower plate Lplate. A plurality of sub-sockets FSK corresponding to the sub-holes FH of the control PCB CPCB can be disposed in the lower plate Lplate. The sub-holes FH can be coupled to the sub-sockets FSK by using a conductive coupler SRW, but the disclosure is not limited thereto. An element for coupling the sub-holes FH to the sub-sockets FSK can not necessarily be a conductor.

[0099] Based on the placement direction of the control PCB CPCB, the first upper position of the control PCB CPCB can overlap the first lower position of the lower plate Lplate or can not overlap the first lower position of the lower plate Lplate. When the first upper position overlaps the first lower position, the first power connection hole DH can be coupled to the first coupling socket DSK through the first conductive coupler SRW. On the other hand, when the first upper position does not overlap the first lower position, the first power connection hole DH can not be coupled to the first coupling socket DSK through the first conductive coupler SRW.

[0100] For example, as Figure 13As shown, when the placement direction of the control PCB is a forward direction (0 degree) identical to the specific direction, the first upper position can overlap the first lower position, and the first power connection hole DH can be coupled to the first coupling socket DSK through the first conductive coupler SRW, and thus, the high logic power (3.3V) can be connected to the first direction recognition pin D-Pin of the timing controller TCON through the first and second power lines PL1 and PL2 and the first conductive coupler SRW. Accordingly, as shown, Figure 15 As shown, the timing controller TCON can transmit forward placement direction information having a logic value of "1" to the setting board.

[0101] On the other hand, as shown, Figure 14 As shown, when the placement direction of the control PCB is a reverse direction (180 degrees) opposite to the specific direction, the first upper position can not overlap the first lower position, and the first power connection hole DH can not be coupled to the first coupling socket DSK, and thus, the high logic power (3.3V) can not be connected to the first direction recognition pin D-Pin of the timing controller TCON. The first direction recognition pin D-Pin of the timing controller TCON can not be connected to the high logic power (3.3V) and can be floated. Accordingly, as shown, Figure 15 As shown, the timing controller TCON can transmit reverse placement direction information having a logic value of "0" to the setting board.

[0102] Figures 16A-16C FIG. 2 is a diagram showing a first embodiment of an overall connection structure of each display module for automatically recognizing a placement direction of a control PCB. Figures 17-20 is a diagram showing an example in which the control PCB is connected to a lower plate at each of 270 degrees, 90 degrees, 0 degrees, and 180 degrees rotated from a specific direction in the display module according to the first embodiment. Figure 21 is a diagram showing logic values of a first direction recognition pin and a second direction recognition pin based on a placement direction of a control PCB in a display module according to the first embodiment.

[0103] Referring to Figures 16A-16C Each display module can further include a lower plate Lplate coupled to a rear surface of the control PCB CPCB.

[0104] The timing controller TCON can be mounted on the control PCB CPCB. The timing controller TCON can be fixed to the control PCB CPCB, and thus, the placement direction of the timing controller TCON can be changed based on the placement direction of the control PCB CPCB. To represent four placement directions of the control PCB CPCB, a first direction identification pin D-Pin1 and a second direction identification pin D-Pin2 can be included in the timing controller TCON. The first direction identification pin D-Pin1 and the second direction identification pin D-Pin2 can represent four pieces of direction information (e.g., 0-degree, 90-degree, 180-degree, and 270-degree placement direction information) having different logic values based on the placement direction of the control PCB CPCB.

[0105] A plurality of sub-holes FH for coupling to the lower plate Lplate and first and second power connection holes DH1 and DH2 for connection to a high logic power source can be formed in the control PCB CPCB. The first power connection hole DH1 can be formed at a first upper position close to a region in which the timing controller TCON is mounted, and the second power connection hole DH2 can be formed at a second upper position close to the region in which the timing controller TCON is mounted. The first power connection hole DH1 can be connected to the first direction identification pin D-Pin1 of the timing controller TCON through a first power line PL1 and can be connected to the high logic power source (3.3 V) through a second power line PL2. The second power connection hole DH2 can be connected to the second direction identification pin D-Pin2 of the timing controller TCON through a third power line PL3 and can be connected to the high logic power source (3.3 V) through a fourth power line PL4.

[0106] Regardless of the change in the placement direction of the control PCB CPCB, the lower plate Lplate can be coupled to the control PCB CPCB in a state of being fixed to a specific direction (e.g., 0-degree and positive direction). A first coupling socket DSK1 can be disposed at a first lower position of the lower plate Lplate, and a second coupling socket DSK2 can be disposed at a second lower position of the lower plate Lplate. A plurality of sub-sockets FSK corresponding to the sub-holes FH of the control PCB CPCB can be disposed in the lower plate Lplate. The sub-holes FH can be coupled to the sub-sockets FSK by using a conductive coupler SRW, but the disclosure is not limited thereto.

[0107] The number of sub-holes FH and the number of sub-sockets FSK can be implemented to be equal, so that mechanical coupling between the control PCB CPCB and the lower plate Lplate is feasible regardless of the placement direction of the control PCB CPCB. In particular, the interval between adjacent sub-holes FH can be designed to be equal to the interval between adjacent sub-sockets FSK.

[0108] Based on the placement orientation of the control PCB CPCB, at least one of the first upper position and the second upper position of the control PCB CPCB can overlap with at least one of the first lower position and the second lower position of the lower plate Lplate, or they can not overlap. When at least one of the first upper position and the second upper position overlaps with at least one of the first lower position and the second lower position, the first power connection hole DH1 and the second power connection hole DH2 can be coupled to at least one of the first coupling socket DSK1 and the second coupling socket DSK2 through at least one of the first conductive coupler and the second conductive coupler SRW. On the other hand, when at least one of the first upper position and the second upper position does not overlap with at least one of the first lower position and the second lower position, the first power connection hole DH1 and the second power connection hole DH2 can be coupled to the first coupling socket DSK1 and the second coupling socket DSK2 without the first conductive coupler and the second conductive coupler SRW.

[0109] For example, such as Figure 17 As shown, when the control PCB is placed in the same positive direction (0 degrees) as the specific direction, the first upper position can overlap with the first lower position, and the first power connection hole DH1 can be coupled to the first coupling socket DSK1 through the first conductive coupler SRW. Therefore, the high logic power supply (3.3V) can be connected to the first direction identification pin D-Pin1 of the timing controller TCON through the first power line PL1, the second power line PL2, and the first conductive coupler SRW. Furthermore, when the control PCB is placed in the same positive direction (0 degrees) as the specific direction, the second upper position can overlap with the second lower position, and the second power connection hole DH2 can be coupled to the second coupling socket DSK2 through the second conductive coupler SRW. Therefore, the high logic power supply (3.3V) can be connected to the second direction identification pin D-Pin2 of the timing controller TCON through the third power line PL3, the fourth power line PL4, and the second conductive coupler SRW. Thus, as... Figure 21 As shown, the timing controller TCON can transmit 0-degree placement orientation information with a logic value of "11" to the setting board.

[0110] like Figure 18As shown, when the placement direction of the control PCB is rotated 90 degrees from the specific direction, the first upper position can overlap with the second lower position, and the first power connection hole DH1 can be coupled to the second coupling socket DSK2 through the first conductive coupler SRW, and thus the high logic power (3.3V) can be connected to the first direction recognition pin D-Pin1 of the timing controller TCON through the first and second power lines PL1 and PL2 and the first conductive coupler SRW. In addition, when the placement direction of the control PCB is rotated 90 degrees from the specific direction, the second upper position can not overlap with the first lower position and the second lower position, and the second power connection hole DH2 can not be coupled to the first coupling socket DSK1 and the second coupling socket DSK2, and thus the high logic power (3.3V) can not be connected to the second direction recognition pin D-Pin2 of the timing controller TCON. Accordingly, as shown, Figure 21 the timing controller TCON can transmit 90-degree placement direction information having a logic value of "10" to the setting board.

[0111] As shown, Figure 19 when the placement direction of the control PCB is rotated 180 degrees from the specific direction, the first upper position can not overlap with the first lower position and the second lower position, and the first power connection hole DH1 can not be coupled to the first coupling socket DSK1 and the second coupling socket DSK2, and thus the high logic power (3.3V) can not be connected to the first direction recognition pin D-Pin1 of the timing controller TCON. In addition, when the placement direction of the control PCB is rotated 180 degrees from the specific direction, the second upper position can not overlap with the first lower position and the second lower position, and the second power connection hole DH2 can not be coupled to the first coupling socket DSK1 and the second coupling socket DSK2, and thus the high logic power (3.3V) can not be connected to the second direction recognition pin D-Pin2 of the timing controller TCON. Accordingly, as shown, Figure 21 the timing controller TCON can transmit 180-degree placement direction information having a logic value of "00" to the setting board.

[0112] As shown, Figure 20As shown, when the placement direction of the control PCB is rotated 270 degrees from the specific direction, the first upper position can not overlap with the first lower position and the second lower position, and the first power connection hole DH1 can not be coupled to the first coupling socket DSK1 and the second coupling socket DSK2, and thus the high logic power supply (3.3V) can not be connected to the first direction identification pin D-Pin1 of the timing controller TCON. In addition, when the placement direction of the control PCB is rotated 270 degrees from the specific direction, the second upper position can overlap with the first lower position, and the second power connection hole DH2 can be coupled to the first coupling socket DSK1 through the second conductive coupler SRW, and thus the high logic power supply (3.3V) can be connected to the second direction identification pin D-Pin2 of the timing controller TCON through the third power line PL3 and the fourth power line PL4 and the second conductive coupler SRW. Therefore, as shown, the timing controller TCON can transmit 270-degree placement direction information having a logic value "01" to the setting plate. Figure 21

[0113] Figure 22 Figure 23 are diagrams illustrating an example of setting module image coordinate values of display modules based on a placement direction of a control PCB in an informal connection structure between the display modules.

[0114] Referring to Figure 22 Figure 23 In order to correspond to various informal connection structures, the case 1 to the case 4 can correspond to a placement direction of the control PCB CPCB being rotated 90 degrees, 270 degrees, 0 degrees, and 180 degrees from a specific direction, respectively. The case 1 to the case 4 can be combined such that a length of the interface cable CBL is optimal.

[0115] In the informal connection structure, an input / output direction of image data based on the control PCB CPCB can be based on a placement direction of the control PCB CPCB. For example, in the case 1, the input / output direction of the image data can be a direction from an upper side of the control PCB CPCB to a lower side of the control PCB CPCB, and in the case 2, the input / output direction of the image data can be a direction from the lower side of the control PCB CPCB to the upper side of the control PCB CPCB. In addition, in the case 3, the input / output direction of the image data can be a direction from a left side of the control PCB CPCB to a right side of the control PCB CPCB, and in the case 4, the input / output direction of the image data can be a direction from the right side of the control PCB CPCB to the left side of the control PCB CPCB.

[0116] The setting plate SET can determine module image coordinate values of each display module based on a plurality of pieces of placement direction information about the control PCB CPCB received from the display modules.​​​

[0117] The setting plate SET can combine the plurality of placement direction information about the previous and current control PCBs CPCBs with the module image coordinate values of the previous control PCB CPCB to calculate the module image coordinate values of the current control PCB CPCB.

[0118] For example, in the case of calculating the module image coordinate values of the second display module CB on which the TCON#2 is mounted, the setting plate SET can apply “column coordinate + 1” to the module image coordinate values (1, 1) of the first display module CB to calculate the module image coordinate values (1, 2). This can correspond to the case where the case 3 becomes the case 1.

[0119] In the case of calculating the module image coordinate values of the third display module CB on which the TCON#3 is mounted, the setting plate SET can apply “row coordinate + 1” to the module image coordinate values (1, 2) of the second display module CB to calculate the module image coordinate values (2, 2). This can correspond to the case where the case 1 becomes the case 1.

[0120] In the case of calculating the module image coordinate values of the fourth display module CB on which the TCON#4 is mounted, the setting plate SET can apply “column coordinate - 1” to the module image coordinate values (2, 2) of the third display module CB to calculate the module image coordinate values (2, 1). This can correspond to the case where the case 1 becomes the case 4.

[0121] Figure 24 And Figure 25 are diagrams illustrating a third embodiment of the overall connection structure of each display module for automatically recognizing a placement direction of a control PCB.

[0122] Referring to Figure 24 And Figure 25 Each display module can further include a lower plate Lplate coupled to a rear surface of the control PCB CPCB.

[0123] A timing controller TCON can be mounted on the control PCB CPCB. The timing controller TCON can be fixed to the control PCB CPCB, and thus, a placement direction of the timing controller TCON can be changed based on a placement direction of the control PCB CPCB. In order to represent two or more placement directions of the control PCB CPCB, one or more direction identification pins D-Pin can be included in the timing controller TCON. The direction identification pins D-Pin can represent two or more pieces of direction information (for example, 0-degree and 180-degree placement direction information or 0-degree, 90-degree, 180-degree, and 270-degree placement direction information) having different logic values based on the placement direction of the control PCB CPCB.

[0124] The pair of conductive patterns CP1 and CP2 for coupling to the plurality of sub-holes of the lower plate Lplate and for connection to the high logic power supply can be formed in the control PCB CPCB. The pair of conductive patterns CP1 and CP2 can be formed at a first upper position close to a region where the timing controller TCON is mounted. The pair of conductive patterns CP1 and CP2 can also be formed at another first upper position close to a region where the timing controller TCON is mounted.

[0125] The pair of conductive patterns CP1 and CP2 can include a first conductive pattern CP1 and a second conductive pattern CP2 that are electrically disconnected from each other. The first conductive pattern CP1 can be connected to a direction recognition pin D-Pin of the timing controller TCON through a first power line PL1, and the second conductive pattern CP2 can be connected to a high logic power supply (3.3V) through a second power line PL2.

[0126] Regardless of the change in the placement direction of the control PCB CPCB, the lower plate Lplate can be coupled to the control PCB CPCB in a fixed direction (for example, 0 degrees). A first conductive gasket GSK can be disposed at a first lower position of the lower plate Lplate. The first conductive gasket GSK can also be disposed at another first lower position of the lower plate Lplate. A plurality of sub-jacks corresponding to the sub-holes of the control PCB CPCB can be disposed in the lower plate Lplate. The sub-holes can be coupled to the sub-jacks by using a conductive coupler, but the present disclosure is not limited thereto.

[0127] The number of sub-holes and the number of sub-jacks can be implemented to be equal, so that mechanical coupling between the control PCB CPCB and the lower plate Lplate is possible regardless of the placement direction of the control PCB CPCB. In particular, the interval between adjacent sub-holes can be designed to be equal to the interval between adjacent sub-jacks.

[0128] Based on the placement direction of the control PCB CPCB, at least one of the first upper positions of the control PCB CPCB can overlap at least one of the first lower positions of the lower plate Lplate, or can not overlap at least one of the first lower positions of the lower plate Lplate.

[0129] When at least one of the first upper positions overlaps at least one of the first lower positions (for example, as in FIG. 6A), the conductive gasket GSK can be disposed at the first lower position of the lower plate Lplate. The conductive gasket GSK can be disposed at another first lower position of the lower plate Lplate. Figure 25When the first upper position and the first lower position overlap (for example, as shown in the left part of FIG. 10) (for example, when the placement direction of the control PCB CPCB is the same as the specific direction), the first conductive pattern CP1 and the second conductive pattern CP2 can be electrically connected to each other at the corresponding overlapping positions through the first conductive gasket GSK, and thus, the high logic power (3.3V) can be connected to the direction recognition pin D-Pin of the timing controller TCON through the first power line PL1 and the second power line PL2 and the first conductive pattern CP1 and the second conductive pattern CP2.

[0130] On the other hand, when the first upper position and the first lower position do not overlap (for example, as shown in the right part of FIG. 10) (for example, when the placement direction of the control PCB CPCB is opposite to the specific direction), the first conductive pattern CP1 and the second conductive pattern CP2 can remain disconnected from each other, and thus, the high logic power (3.3V) can not be connected to the direction recognition pin D-Pin of the timing controller TCON. Figure 25

[0131] In Figure 24 and Figure 25 , in the case where each control PCB CPCB is connected to the lower plate Lplate rotated by 0 degrees and 180 degrees from the specific direction, the operation of generating the placement direction information in the timing controller TCON can be similar to the details described above with reference to Figure 13 and Figure 14 .

[0132] In Figure 24 and Figure 25 , in the case where each control PCB CPCB is connected to the lower plate Lplate rotated by 0 degrees, 90 degrees, 180 degrees, and 270 degrees from the specific direction, the operation of generating the placement direction information in the timing controller TCON can be similar to the details described above with reference to Figures 17-20 .

[0133] Figure 26 and Figure 27 are diagrams showing the overall connection structure of each display module for automatically recognizing the placement direction of the control PCB.

[0134] Referring to Figure 26 and Figure 27 , each display module can further include a lower plate Lplate coupled to the rear surface of the control PCB CPCB.

[0135] ​The timing controller TCON can be mounted on the control PCB CPCB. The timing controller TCON can be fixed to the control PCB CPCB, and thus, the placement direction of the timing controller TCON can be changed based on the placement direction of the control PCB CPCB. To represent two or more placement directions of the control PCB CPCB, one or more direction identification pins D-Pin can be included in the timing controller TCON. The direction identification pins D-Pin can represent two or more pieces of direction information (e.g., 0-degree and 180-degree placement direction information or 0-degree, 90-degree, 180-degree, and 270-degree placement direction information) having different logic values based on the placement direction of the control PCB CPCB.

[0136] A plurality of sub-holes for coupling to the lower plate Lplate and a press switch SW for connection to a high logic power source can be formed in the control PCB CPCB. The press switch SW can be formed at a first upper position close to an area in which the timing controller TCON is mounted. The press switch SW can also be formed at another first upper position close to the area in which the timing controller TCON is mounted.

[0137] The press switch SW can be connected to the direction identification pins D-Pin of the timing controller TCON through a first power line PL1 and to a high logic power source (3.3 V) through a second power line PL2.

[0138] Regardless of the change in the placement direction of the control PCB CPCB, the lower plate Lplate can be coupled to the control PCB CPCB with being fixed to a specific direction (e.g., 0 degrees). A first protruding portion PP can be disposed at a first lower position of the lower plate Lplate. The first protruding portion PP can also be disposed at another first lower position of the lower plate Lplate. A plurality of sub-jacks corresponding to the sub-holes of the control PCB CPCB can be disposed in the lower plate Lplate. The sub-holes can be coupled to the sub-jacks by using a conductive coupler SRW, but the disclosure is not limited thereto.

[0139] The number of sub-holes and the number of sub-jacks can be implemented to be equal, so that mechanical coupling between the control PCB CPCB and the lower plate Lplate is possible regardless of the placement direction of the control PCB CPCB. In particular, the interval between adjacent sub-holes can be designed to be equal to the interval between adjacent sub-jacks.

[0140] Based on the placement direction of the control PCB CPCB, at least one of the first upper positions of the control PCB CPCB can overlap at least one of the first lower positions of the lower plate Lplate, or can not overlap at least one of the first lower positions of the lower plate Lplate.

[0141] When at least one of the first upper positions overlaps with at least one of the first lower positions (for example, as shown in the right part of Figure 27 , the press switch SW can be turned on based on contacting the first protrusion part PP at the corresponding overlapping position, and thus, the high logic power (3.3V) can be connected to the direction recognition pin D-Pin of the timing controller TCON through the first and second power lines PL1 and PL2 and the press switch SW.

[0142] On the other hand, when the first upper positions do not overlap with the first lower positions (for example, as shown in the left part of Figure 27 , the press switch SW can remain off, and thus, the high logic power (3.3V) can not be connected to the direction recognition pin D-Pin of the timing controller TCON.

[0143] In Figure 26 and Figure 27 , in the case where each control PCB CPCB is connected to the lower plate Lplate rotated by 0 and 180 degrees from the specific direction, the operation of generating the placement direction information in the timing controller TCON can be similar to the details described above with reference to Figure 13 and Figure 14 .

[0144] In Figure 26 and Figure 27 , in the case where each control PCB CPCB is connected to the lower plate Lplate rotated by 0, 90, 180, and 270 degrees from the specific direction, the operation of generating the placement direction information in the timing controller TCON can be similar to the details described above with reference to Figures 17-20 .

[0145] Figures 28-31 is a diagram showing an example of input / output image matching based on the placement direction of the control PCB. In Figures 28-31 , “EPI-1, EPI-2, and EPI-3” can each be an internal interface line for data communication between the timing controller TCON and the panel driving circuit.

[0146] With reference to Figures 28-31 , the timing controller TCON can perform a sub-image rematching operation based on image rematching control information from the setting plate to make the module image assignment order the same as or different from the default assignment order.

[0147] According to the default assignment order TA[1], TB[2], TC[3], TD[4], sub- image 1 can be output to the first display panel PNL-A through the first output port TA, sub- image 2 can be output to the second display panel PNL-B through the second output port TB, sub- image 3 can be output to the third display panel PNL-C through the third output port TC, and sub- image 4 can be output to the fourth display panel PNL-D through the fourth output port TD.

[0148] As shown in case 1 in which the placement direction of the control PCB CPCB is the same as the default direction (e.g., a direction rotated 90 degrees from the forward direction), the panel output images based on the default assignment order can be completely matched with the input module images MI. That is, the module images MI can be displayed completely by the four display panels without image inversion or image mixing, and thus, the sub- image rematching operation can not be performed. The timing controller TCON can assign the image data of the sub- images to the first to fourth output ports TA, TB, TC, and TD based on the default assignment order. Figure 28 As shown in case 2, case 3, and case 4 in which the placement direction of the control PCB CPCB is different from the default direction, the panel output images based on the default assignment order can not be matched with the input module images MI. To eliminate the image mismatch, the sub- image rematching operation can be performed in case 2, case 3, and case 4.

[0149] Figures 29-31 In detail, as in case 2, in which the control PCB CPCB is arranged in a direction rotated 270 degrees from the forward direction, the image data of the sub- images can be assigned to the first to fourth output ports TA, TB, TC, and TD differently from the default assignment order. In other words, sub- image 1 can be reassigned to the fourth output port TD, sub- image 2 can be reassigned to the third output port TC, sub- image 3 can be reassigned to the second output port TB, and sub- image 4 can be reassigned to the first output port TA (i.e., the assignment order is TD[1], TC[2], TB[3], TA[4]).

[0150] In detail, as in case 2, in which the control PCB CPCB is arranged in a direction rotated 270 degrees from the forward direction, the image data of the sub- images can be assigned to the first to fourth output ports TA, TB, TC, and TD differently from the default assignment order. In other words, sub- image 1 can be reassigned to the fourth output port TD, sub- image 2 can be reassigned to the third output port TC, sub- image 3 can be reassigned to the second output port TB, and sub- image 4 can be reassigned to the first output port TA (i.e., the assignment order is TD[1], TC[2], TB[3], TA[4]). Figure 29 In addition, as in case 3, in which the control PCB CPCB is arranged in a direction rotated 180 degrees from the forward direction, the image data of the sub- images can be assigned to the first to fourth output ports TA, TB, TC, and TD differently from the default assignment order. In other words, sub- image 1 can be reassigned to the fourth output port TD, sub- image 2 can be reassigned to the third output port TC, sub- image 3 can be reassigned to the second output port TB, and sub- image 4 can be reassigned to the first output port TA (i.e., the assignment order is TD[1], TC[2], TB[3], TA[4]).

[0151] Figure 30 ​​In case 3, in a display module in which the control PCB CPCB is arranged in a forward direction, the image data of the sub-images can be allocated to the first to fourth output ports TA, TB, TC, and TD differently from the default allocation order. In other words, the sub-image 1 can be reallocated to the second output port TB, the sub-image 2 can be reallocated to the fourth output port TD, the sub-image 3 can be reallocated to the first output port TA, and the sub-image 4 can be reallocated to the third output port TC (i.e., the allocation order is TB[1], TD[2], TA[3], TC[4]).

[0152] In addition, as in Figure 31 case 4, in a display module in which the control PCB CPCB is arranged in a direction rotated 180 degrees from the forward direction, the image data of the sub-images can be allocated to the first to fourth output ports TA, TB, TC, and TD differently from the default allocation order. In other words, the sub-image 1 can be reallocated to the fourth output port TD, the sub-image 2 can be reallocated to the first output port TA, and the sub-image 4 can be reallocated to the second output port TB. However, the sub-image 3 can be reallocated to the third output port TC (i.e., the allocation order is TD[1], TA[2], TC[3], TB[4]).

[0153] Figure 32 is a diagram showing 4K resolution input image data allocated to a display module having an informal connection structure of Figure 10A . Figure 33 is a diagram showing module image data allocated to the first display module and the fifth display module in the input image data of Figure 32 .

[0154] Referring to Figure 10A , Figure 32 and Figure 33 , the setting board SET can set module image coordinate values (1, 1) to (2, 4) and image rematching control information corresponding to the module images based on the module identification numbers nID 1 to nID 8 allocated to the timing controllers TCON#1 to TCON#8 and the direction in which the control PCB is arranged.

[0155] The 4K resolution can be 3840*2160. The timing controllers TCON#1 to TCON#8 can separately process eight module images A1 to A8 constituting the 4K resolution. For example, the first timing controller TCON#1 can process the first module image A1 corresponding to the module image coordinate value (1, 1), and the fifth timing controller TCON#5 can process the fifth module image A5 corresponding to the module image coordinate value (2, 4).

[0156] The first module image A1 can have a unit horizontal resolution X "1 to 960" and a unit vertical resolution Y "1 to 1080". The fifth module image A5 can have a unit horizontal resolution X "2881 to 3840" and a unit vertical resolution Y "1081 to 2160".

[0157] Figure 34 is a diagram illustrating an automatic control sequence of a tiled display apparatus according to an embodiment of the present disclosure.

[0158] Referring to Figure 34 , the automatic control sequence of the tiled display apparatus according to the embodiment of the present disclosure can include an automatic nID setting process S2 and S3 and an automatic image coordinate recognition process S4, S5, and S6, the automatic nID setting process S2 and S3 and the automatic image coordinate recognition process S4, S5, and S6 being performed within a power-up sequence period.

[0159] In S1, power-up is performed.

[0160] In S2, a first TCON, a last TCON are recognized. In S3, an automatic nID setting is performed.

[0161] A detailed explanation of the automatic nID setting process S2 and S3 can be as described above with reference to Figures 7-9 .

[0162] In S4, an automatic recognition of a placement direction of a PCB is performed. In S5, an automatic recognition of a placement position of the PCB is performed. In S6, input image data and a data output port are re-matched.

[0163] A detailed explanation of the automatic image coordinate recognition process S4, S5, and S6 can be as described above with reference to Figures 12A-31 .

[0164] In S7, display on is performed.

[0165] The present embodiment can achieve the following effects.

[0166] According to the present embodiment, when the control PCB is joined to the lower plate, the placement direction and position of the control PCB can be automatically checked in the setting plate. Therefore, whenever the display module is installed or replaced, the user does not need to input information associated with the placement direction and position of the control PCB to the memory.

[0167] Therefore, in the present embodiment, resources of the display apparatus associated with the setting of the module image coordinate values and the module identification numbers can be reduced, the convenience of the user can be increased, and errors caused by the user's negligence can be prevented.

[0168] Effects according to the present disclosure are not limited to the examples described above, and other various effects can be included in the specification.

[0169] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A tiled display device, comprising: Multiple display modules are interconnected through an interface circuit based on a serial communication scheme to divide the input image data that constitutes a screen, thereby displaying multiple module images; as well as The setting board checks the module identification number based on the connection order of the plurality of display modules, and sets the module image coordinate value and image rematching control information corresponding to the module image in the plurality of module images for each of the plurality of display modules based on the placement direction of the control printed circuit board (PCB) individually included in each of the plurality of display modules.

2. The tiled display device according to claim 1, wherein, Each of the plurality of display modules includes: A timing controller that divides the module image into multiple sub-images; and Multiple display panels displaying the multiple sub-images, and The control PCB includes multiple image output ports that electrically connect the timing controller to the plurality of display panels, and the timing controller is mounted on the control PCB. The timing controller re-matches the image data of the plurality of sub-images with the plurality of image output ports based on the module image coordinate values ​​transmitted from the setting board and the image rematch control information.

3. The tiled display device according to claim 2, wherein, In response to the control PCB being placed in the same orientation as the default orientation, the timing controller allocates the image data of the plurality of sub-images to the plurality of image output ports based on the default allocation order, and In response to the fact that the placement orientation of the control PCB is different from the default orientation, the timing controller allocates the image data of the plurality of sub-images to the plurality of image output ports in a different order than the default allocation order.

4. The tiled display device according to claim 2, wherein, Each of the plurality of display modules further includes: Regardless of the placement orientation of the control PCB, the lower plate is always coupled to the rear surface of the control PCB in a fixed specific orientation; The first coupling socket at the first lower position of the lower plate; The first power connection hole is located at a first upper position in the area of ​​the control PCB where the timing controller is mounted; A first power line is connected between a first direction identification pin of the timing controller and a first power connection hole; and A second power line is connected between the high logic power supply and the first power connection hole.

5. The tiled display device according to claim 4, wherein, In response to the placement orientation of the control PCB being the same as the specific orientation, the first upper position overlaps with the first lower position, and the first power connection hole is coupled to the first coupling socket through the first conductive coupler, thereby the high logic power supply is connected to the first direction identification pin of the timing controller through the first power line, the second power line and the first conductive coupler.

6. The tiled display device according to claim 4, wherein, In response to the placement orientation of the control PCB being opposite to the specific orientation, the first upper position does not overlap with the first lower position, and the first power connection hole is not coupled to the first coupling socket, so that the high logic power supply is not connected to the first direction identification pin of the timing controller.

7. The tiled display device according to claim 2, wherein, Each of the plurality of display modules further includes: Regardless of the placement orientation of the control PCB, the lower plate is always coupled to the rear surface of the control PCB in a fixed specific orientation; The first coupling socket and the second coupling socket are respectively located at the first lower position and the second lower position of the lower plate; The first power connection hole and the second power connection hole are respectively located at a first upper position and a second upper position in the area where the timing controller is installed in the control PCB; A first power line is connected between the first direction identification pin of the timing controller and the first power connection hole; A second power line is connected between a high logic power supply and the first power connection hole; A third power line, wherein the third power line is connected between the second direction identification pin of the timing controller and the second power connection hole; and A fourth power line is connected between the high logic power supply and the second power connection hole.

8. The tiled display device according to claim 7, wherein, In response to the control PCB being placed in the same orientation as the specific orientation, The first upper position overlaps with the first lower position, and the first power connection hole is coupled to the first coupling socket through a first conductive coupler, so that the high logic power supply is connected to the first direction identification pin of the timing controller through the first power line, the second power line, and the first conductive coupler. The second upper position overlaps with the second lower position, and the second power connection hole is coupled to the second coupling socket through the second conductive coupler, so that the high logic power supply is connected to the second direction identification pin of the timing controller through the third power line, the fourth power line and the second conductive coupler.

9. The tiled display device according to claim 7, wherein, When the placement orientation of the control PCB is rotated 90 degrees from the specific orientation, The first upper position overlaps with the second lower position, and the first power connection hole is coupled to the second coupling socket through a first conductive coupler, so that the high logic power supply is connected to the first direction identification pin of the timing controller through the first power line, the second power line, and the first conductive coupler. The second upper position does not overlap with the first lower position and the second lower position, and the second power connection hole is not coupled to the first coupling socket and the second coupling socket, so that the high logic power supply is not connected to the second direction identification pin of the timing controller.

10. The tiled display device according to claim 7, wherein, In response to the placement orientation of the control PCB being rotated 180 degrees from the specific orientation, The first upper position does not overlap with the first lower position and the second lower position, and the first power connection hole is not coupled to the first coupling socket and the second coupling socket, so that the high logic power supply is not connected to the first direction identification pin of the timing controller, and The second upper position does not overlap with the first lower position and the second lower position, and the second power connection hole is not coupled to the first coupling socket and the second coupling socket, so that the high logic power supply is not connected to the second direction identification pin of the timing controller.

11. The tiled display device according to claim 7, wherein, In response to the placement orientation of the control PCB rotating 270 degrees from the specific orientation, The first upper position does not overlap with the first lower position and the second lower position, and the first power connection hole is not coupled to the first coupling socket and the second coupling socket, so that the high logic power supply is not connected to the first direction identification pin of the timing controller, and The second upper position overlaps with the first lower position, and the second power connection hole is coupled to the first coupling socket through the second conductive coupler, so that the high logic power supply is connected to the second direction identification pin of the timing controller through the third power line, the fourth power line and the second conductive coupler.

12. The tiled display device according to claim 2, wherein, Each of the plurality of display modules further includes: Regardless of the placement orientation of the control PCB, the lower plate is always coupled to the rear surface of the control PCB in a fixed specific orientation; A first conductive pad is disposed at the first lower position of the lower plate; A first conductive pattern and a second conductive pattern are spaced apart from each other at a first upper position in the area of ​​the control PCB where the timing controller is mounted. A first power line is connected between the first direction identification pin of the timing controller and the first conductive pattern; and The second power line is connected between the high logic power supply and the second conductive pattern.

13. The tiled display device according to claim 12, wherein, In response to the control PCB being placed in the same orientation as the specific orientation, The first upper position overlaps with the first lower position, and the first conductive pattern is electrically connected to the second conductive pattern through the first conductive pad, so that the high logic power supply is connected to the direction recognition pin of the timing controller through the first power line, the second power line, the first conductive pattern and the second conductive pattern.

14. The tiled display device according to claim 12, wherein, In response to the placement orientation of the control PCB being opposite to the specific orientation, The first upper position does not overlap with the first lower position, and the first conductive pattern and the second conductive pattern are separated from each other, so that the high logic power supply is not connected to the direction recognition pin of the timing controller.

15. The tiled display device according to claim 2, wherein, Each of the plurality of display modules further includes: Regardless of the placement orientation of the control PCB, the lower plate is always coupled to the rear surface of the control PCB in a fixed specific orientation; A first protrusion is provided at the first lower position of the lower plate; A push switch is disposed at a first upper position in the area of ​​the control PCB in which the timing controller is mounted; A first power line is connected between the direction recognition pin of the timing controller and the push switch; and A second power line is connected between the high logic power supply and the push-button switch.

16. The tiled display device according to claim 15, wherein, In response to the control PCB being placed in the same orientation as the specific orientation, The first upper position overlaps with the first lower position, and the push switch is turned on based on contact with the first protrusion, such that the high logic power supply is connected to the direction recognition pin of the timing controller through the first power line, the second power line, and the push switch.

17. The tiled display device according to claim 15, wherein, In response to the placement orientation of the control PCB being opposite to the specific orientation, The first upper position does not overlap with the first lower position, and the push switch remains in the off state, so that the high logic power supply is not connected to the direction recognition pin of the timing controller.

18. The tiled display device according to claim 1, wherein, Each of the plurality of display modules includes a timing controller. The first timing controller, based on the connection order of the plurality of display modules, includes a first option pin connected to a high logic power supply and a second option pin connected to the high logic power supply. The final timing controller based on the connection order of the multiple display modules includes a first option pin connected to a low logic power supply and a floating second option pin, and Each of the other timing controllers besides the first and the last timing controllers includes a first option pin connected to the low logic power supply and a second option pin connected to the high logic power supply.

19. A tiled display device, comprising: Multiple display modules are interconnected via an interface circuit based on a serial communication scheme to divide input image data constituting a screen, thereby displaying multiple module images. Each display module includes a control printed circuit board (PCB) and a timing controller for dividing the module image into multiple sub-images. The setting board generates control command signals to cause the timing controllers in the plurality of display modules to sequentially generate module identifiers, and for each display module, sets module image coordinate values ​​and image rematching control information corresponding to the module image based on the placement orientation of the control printed circuit board (PCB).

Images