Gate driving circuit and display device including the same

Abstract

Disclosed is a gate driving circuit that minimizes output characteristic deviation among a plurality of scan output buffer units and a display device including the same, wherein an Nth stage of the gate driving circuit, N being a natural number, includes a node controller configured to control voltages of a first node and a second node according to a set signal and a reset signal, a carry pulse output unit configured to receive a carry clock and output the carry clock as a carry pulse according to the voltages of the first node and the second node, and a plurality of scan pulse output units configured to receive a plurality of scan clocks and output each of the scan clocks as a scan pulse according to the voltages of the first node and the second node, wherein the carry clock is provided before a scan clock provided to a first scan pulse output unit and after a scan clock provided to a last scan pulse output unit among the plurality of scan pulse output units.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0192811, filed on December 30, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a gate driving circuit that uses a shift register to shift scan pulses and a display device including the gate driving circuit. Background Technology

[0004] In the information society, numerous technologies have been developed in the field of display devices for displaying visual information as images or videos. The driving circuitry of a display device includes data driving circuitry for providing data signals to data lines, gate driving circuitry for sequentially providing gate signals (or scan signals) to gate lines (or scan lines), and so on. The gate driving circuitry can be directly formed on the display area of ​​the same substrate along with the circuit elements of the pixel array included in the screen.

[0005] The circuitry of the pixel array is comprised in pixel circuitry formed in each pixel by a matrix defined by the data lines and gate lines of the pixel array. Each circuitry element of the pixel array and gate drive circuitry comprises multiple transistors. Hereinafter, the gate drive circuitry formed directly on the display area of ​​the display panel, together with the circuitry of the pixel array, will be referred to as "GIP circuitry".

[0006] Most display devices use a progressive scan method to write data to pixels. In this method, pixel data of the input image is sequentially written to all rows of the pixel array during the vertical active period of a frame cycle. For example, pixel data is written to the pixels of the first row simultaneously, then to the pixels of the second row simultaneously, and so on, until the pixels of the third row are written to the pixels of the third row simultaneously. In this way, pixel data is sequentially written to the pixels of all rows of the display panel. To implement this progressive scan method, the GIP circuitry uses a shift register to shift the output signal and sequentially provides the gate signal to the gate lines. Here, the output signal can be interpreted as either a gate signal or a scan signal.

[0007] The shift register includes multiple slave-connected stages, and each stage has an output buffer that generates a gate signal and provides the generated gate signal to a gate line.

[0008] In recent years, since the gate drive circuit (GIP circuit) is formed directly in the display area of ​​the display panel along with the circuit elements of the pixel array, there is a requirement to minimize the configuration of the GIP circuit.

[0009] Therefore, a shift register for outputting multiple gate signals in a single stage has been developed. That is, the single stage has a carry output buffer for outputting carry pulses and multiple scan output buffers for outputting scan pulses of different phases, called "NSDC". Summary of the Invention

[0010] Therefore, the present invention aims to provide a gate driving circuit and a display device including the gate driving circuit, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0011] The purpose of this invention is to provide a gate driving circuit that minimizes the output characteristic deviation between multiple scan output buffer units, and a display device including the gate driving circuit.

[0012] Other advantages, objects, and features of the invention will be set forth in part in the description which follows, and will also be apparent in part to those skilled in the art upon examination of the following, or may be learned from practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and claims, and in the accompanying drawings.

[0013] To achieve these and other advantages and according to the purposes of the invention, as specifically implemented and broadly described herein, the Nth (N is a natural number) stage of the gate drive circuit includes: a node controller configured to control the voltages of a first node and a second node according to a set signal and a reset signal; a carry pulse output unit configured to receive a carry clock and output a carry clock as a carry pulse according to the voltages of the first node and the second node; and a plurality of scan pulse output units configured to receive a plurality of scan clocks and output each scan clock as a scan pulse according to the voltages of the first node and the second node, wherein, among the plurality of scan pulse output units, a carry clock is provided before the scan clock provided to the first scan pulse output unit and after the scan clock provided to the last scan pulse output unit.

[0014] Multiple scan pulse output units may include a first scan pulse output unit to a fourth scan pulse output unit, configured to receive a first scan clock to a fourth scan clock and output scan pulses sequentially; and before the first scan clock provided to the first scan pulse output unit is converted to a high level, the carry clock may be converted to a high level and remain at a high level for a specific period of time, and after the fourth scan clock provided to the fourth scan pulse output unit is converted to a high level, the carry clock may be converted to a high level and remain at a high level for a specific period of time.

[0015] The first to fourth scan clocks can remain high for two horizontal cycles and be shifted so that the high levels of adjacent scan clocks overlap within one horizontal cycle; and the carry clock can be converted to a high level one horizontal cycle (1H) earlier than the first scan clock and remain high for two horizontal cycles, and the carry clock can be converted to a high level one horizontal cycle (1H) later than the fourth scan clock and remain high for two horizontal cycles.

[0016] In another aspect of the invention, a display device includes: a display panel including data lines, gate lines, and sub-pixels; a data driving circuit configured to provide data signals of an input image to the data lines; and a gate driving circuit configured to provide gate signals to the gate lines. The Nth-level gate driving circuit includes: a node controller configured to control the voltages of a first node and a second node according to a set signal and a reset signal; a carry pulse output unit configured to receive a carry clock and output a carry clock as a carry pulse according to the voltages of the first node and the second node; and a plurality of scan pulse output units configured to receive a plurality of scan clocks and output each scan clock as a scan pulse according to the voltages of the first node and the second node, wherein the carry clock is provided before the scan clock provided to the first scan pulse output unit and after the scan clock provided to the last scan pulse output unit among the plurality of scan pulse output units.

[0017] It should be understood that the foregoing general description and the following detailed description of the invention are exemplary and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0018] The accompanying drawings are included in and constitute a part of this application to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0019] Figure 1 This is a structural diagram of a display device according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the shift register of the gate drive circuit 120;

[0021] Figure 3 This is a detailed circuit diagram of the Nth stage according to the present invention;

[0022] Figure 4 This is a schematic input / output waveform diagram of a gate drive circuit according to a comparative example of the present invention;

[0023] Figure 5The diagram illustrates, more specifically, the input / output waveforms of the gate drive circuit according to a comparative example of the present invention;

[0024] Figure 6 This is a schematic input / output waveform diagram of the gate drive circuit according to an embodiment of the present invention;

[0025] Figure 7 More specifically, the input / output waveform diagrams of the gate drive circuit according to an embodiment of the present invention are illustrated; and

[0026] Figure 8 This is a graph comparing the output of the scanning pulses according to the comparative example and embodiment of the present invention.

[0027] Figure 9 This is a table comparing the maximum voltage, rise time, and fall time of each scan pulse according to the comparative examples and embodiments of the present invention. Detailed Implementation

[0028] The advantages and features of the present invention, as well as the methods for achieving these advantages and features, will become clear from the following detailed description of the embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in various different forms, and these embodiments are intended to make the disclosure of the invention complete and are provided only to those skilled in the art to whom the invention pertains. Furthermore, the invention is defined only by the scope of the claims.

[0029] The shapes, dimensions, proportions, angles, quantities, etc., disclosed in the accompanying drawings for describing embodiments of the present invention are exemplary, and therefore the present invention is not limited to the elements shown. The same reference numerals refer to the same elements throughout the specification. Furthermore, in describing the present invention, detailed descriptions of related known technologies will be omitted when it is determined that such detailed descriptions may unnecessarily obscure the subject matter of the present invention.

[0030] When terms such as “equipped with,” “including,” “having,” or “comprising” are used in this specification, other parts may also be present, unless “only” is used. When an element is expressed in the singular, it may be interpreted as plural unless otherwise expressly stated.

[0031] When interpreting components, even if there is no separate explicit description, it will be interpreted as including the error range.

[0032] When describing positional relationships, such as when using terms like "above," "over," "below," or "adjacent" to describe the positional relationship between two parts, one or more other parts may be located between the two parts, unless "immediately" or "directly" is used.

[0033] Although terms such as "first" and "second" can be used to distinguish elements, the function or structure of these elements is not limited by the serial number or name preceding the element. Since the claims are described based on basic elements, the serial numbers preceding the element names in the claims may not match the serial numbers preceding the element names in the embodiments.

[0034] The following implementation methods can be combined or integrated in whole or in part, and various types of interlocks and drives are technically possible. The various implementation methods can be implemented independently or together in a related manner.

[0035] In this invention, each of the gate-in-the-loop (GIP) circuit and the pixel circuit includes multiple transistors. The transistors can be implemented as thin-film transistors (TFTs) with a metal-oxide-semiconductor (MOSFET) FET structure, and can be oxide TFTs comprising oxide semiconductors or LTPS TFTs comprising low-temperature polycrystalline silicon (LTPS). The oxide TFT can be implemented as an n-type TFT (NMOS), and the LTPS TFT can be implemented as a p-type TFT (PMOS). Both an n-type TFT (NMOS) and a p-type TFT (PMOS) can be formed in each of the GIP circuit and the pixel circuit.

[0036] A MOSFET is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a MOSFET, charge carriers begin to flow out of the source. The drain is the electrode through which charge carriers leave the MOSFET. In a MOSFET, charge carriers flow from the source to the drain. In the case of an n-type TFT (NMOS), since the charge carriers are electrons and the source voltage is lower than the drain voltage, electrons can flow from the source to the drain. In an n-type TFT (NMOS), current flows from the drain to the source. In the case of a p-type TFT (PMOS), since the charge carriers are holes and the source voltage is higher than the drain voltage, holes can flow from the source to the drain. In a p-type TFT (PMOS), current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a TFT are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the present invention is not limited to the source and drain of the TFT. In the following description, the source and drain of the TFT will be referred to as the first electrode and the second electrode, respectively.

[0037] The scan pulse (gate signal) output from the GIP circuit of the gate drive circuit oscillates between the gate on-state voltage and the gate off-state voltage. The gate on-state voltage is set to a voltage higher than the threshold voltage of the TFT, and the gate off-state voltage is set to a voltage lower than the threshold voltage of the TFT. The TFT turns on in response to the gate on-state voltage and turns off in response to the gate off-state voltage.

[0038] Hereinafter, various embodiments of this specification will be described in detail with reference to the accompanying drawings. In the following embodiments, electroluminescent displays will be described primarily with respect to organic light-emitting diode (OLED) displays that include organic light-emitting materials. It should be noted that the technical concepts in this specification are not limited to OLED displays. For example, without significant changes, the present invention is applicable to the gate drive circuits of digital flat panel displays that require gate drive circuits, such as liquid crystal displays (LCDs) or quantum dot displays (QDs).

[0039] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0040] The display device according to the embodiments of this specification includes a display panel 100 and a display panel driving circuit.

[0041] The display panel 100 includes an active area AA for displaying data of an input image. The active area AA is a screen for displaying video data of the input image. The pixel array of the active area AA includes multiple data lines DL, multiple gate lines GL intersecting the multiple data lines DL, and pixels arranged in a matrix. In addition to a matrix, the pixels can be arranged in various forms, such as a shared form of pixels emitting the same color, a striped form, and a diamond form.

[0042] Each pixel can be divided into red, green, and blue sub-pixels to achieve color. Each pixel may also include a white sub-pixel. Each sub-pixel 101 includes pixel circuitry. In the case of an electroluminescent display, the pixel circuitry includes a light-emitting element, multiple TFTs, and a capacitor. The pixel circuitry is connected to a data line DL and a gate line GL. Figure 1 In the diagram, "D1 to D3" in the circle are data lines, and "Gn-2 to Gn" in the circle are gate lines.

[0043] A touch sensor can be mounted on the display panel 100. Touch input can be sensed using a separate touch sensor, or it can be sensed via pixels. The touch sensor can be mounted on the screen of the display panel as an on-chip or external touch sensor, or it can be implemented as an in-chip touch sensor embedded in a pixel array.

[0044] The display panel driving circuit for driving the display panel 100 includes a data driving circuit 110 and a gate driving circuit 120. Under the control of the timing controller (TCON) 130, the display panel driving circuit writes the data of the input image into the pixels of the display panel 100.

[0045] The data driver circuit 110 converts the digital data V-DATA, which is the pixel data of the input image received from the timing controller 130 in each frame, into a gamma-compensated voltage and outputs a data signal. The data driver circuit 110 provides the voltage of the data signal (hereinafter referred to as the "data voltage") to the data line DL. The data driver circuit 110 uses a digital-to-analog converter (hereinafter referred to as the "DAC") that converts the digital data VDATA into a gamma-compensated voltage to output the data voltage.

[0046] The gate driving circuit 120 can be formed in the border area BZ on the display panel 100 where no image is displayed. Alternatively, the gate driving circuit 120 can be distributed in the active area AA on the display panel 100 where an image is displayed.

[0047] Under the control of timing controller 130, gate drive circuit 120 outputs a gate signal (scan pulse) through gate line GL to select pixels charged with data voltage. Gate drive circuit 120 uses one or more shift registers to output the gate signal (scan pulse) and shift the gate signal. During the vertical activation period, gate drive circuit 120 shifts the gate signal provided to the gate line to a predetermined specific gate line in a specific shift sequence, and then temporarily holds the voltage of the specific gate line in response to a line control signal. Subsequently, gate drive circuit 120 provides the gate signal to the specific gate line, and then shifts the gate pulses provided to the remaining gate lines in a specific shift sequence. Therefore, during the vertical activation period, the first gate signal and the second gate signal are applied only to the specific gate line, with a predetermined hold time interspersed, and one gate signal is applied to each of the other gate lines.

[0048] The timing controller 130 receives pixel data of the input image and timing signals synchronized with the pixel data from the host system. The pixel data of the input image received by the timing controller 130 is digital data. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0049] The host system can be a television (TV), set-top box, navigation system, personal computer (PC), home theater, mobile device, and wearable device. In mobile devices and wearable devices, data drive circuit 110, timing controller 130, level shifter 140, etc., can be integrated into a single driver IC.

[0050] The timing controller 130 can control the operating timing of the data drive circuit 110 and the gate drive circuit 120 by multiplying the input frame frequency by i to obtain a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the Phase Alternating Line (PAL) scheme.

[0051] The timing controller 130 can reduce the driving frequency of the data driving circuit 110 and the gate driving circuit 120 in low-speed drive mode. For example, the timing controller 130 can reduce the driving frequency of the display panel driving circuit to 1 Hz, thereby writing data to the pixel once per second. The frequency of the low-speed drive mode is not limited to 1 Hz. Therefore, the pixels of the display panel 100 can maintain the data voltage previously charged to the pixel for most of the time in low-speed drive mode, without charging a new data voltage.

[0052] The timing controller 130 generates a data timing control signal DDC for controlling the operation timing of the data drive circuit 110 and a gate timing control signal GDC for controlling the operation timing of the gate drive circuit 120 based on the timing signals received from the host system.

[0053] Level shifter 140 converts the high-level voltage of the gate timing control signal GDC output from timing controller 130 to a gate on-state voltage, and converts the low-level voltage of the gate timing control signal GDC to a gate off-state voltage, providing the voltage to gate drive circuit 120. In the case of n-channel TFT (NMOS), the gate on-state voltage can be the gate high voltage VGH, and the gate off-state voltage can be the gate low voltage VGL. In the case of p-channel TFT (PMOS), the gate on-state voltage can be the gate low voltage VGL, and the gate off-state voltage can be the gate high voltage VGH. Hereinafter, the high-potential power voltage Vdd can be interpreted as the gate on-state voltage. The low-potential power voltage Vss can be set to a voltage lower than the high-potential power voltage Vdd. The low-potential power voltage Vss can be interpreted as the gate off-state voltage.

[0054] The gate timing control signal GDC includes the gate start pulse VST, line select pulse LSP, carry clock signal CRCLK, scan clock signal SCCLK, etc. In each frame period, the start pulse VST is generated once at the beginning of the frame period and is input to the gate drive circuit 120.

[0055] The start pulse VST controls the start timing of the gate drive circuit 120 in each frame period. The carry clock signal CRCLK and the scan clock signal SCCLK control the shift timing of the carry pulse and scan pulse output from the gate drive circuit 120.

[0056] Figure 2 This is a schematic diagram illustrating the shift register of the gate drive circuit 120.

[0057] First, the gate drive circuit 120 can be driven by three carry clocks and twelve scan clocks. That is, different carry clocks and scan clocks are provided to the three stages in such a way that one carry clock and four scan clocks are provided to the first stage.

[0058] Each carry clock and each scan clock is held high for two horizontal cycles (2H), and the 12 scan clocks are shifted so that the high levels of adjacent scan clocks overlap during one horizontal cycle (1H).

[0059] like Figure 2 As shown, the shift register of the gate drive circuit 120 includes stages SR(N-2) to SR(N+2) connected by wires. The shift register receives a start pulse VST, or a carry pulse CP from the previous stage and a carry pulse CP from the next stage, and outputs a carry pulse CP and i scan pulses SP according to the input clock timing CLK. Here, N and i are natural numbers, preferably natural numbers greater than or equal to 2.

[0060] The carry pulse CP output from the previous stage can be a set signal, and the carry pulse CP output from the next stage can be a reset signal.

[0061] Figure 2 The example illustrates that the Nth stage SR(N) is set by the carry pulse CP output from the (N-2)th stage SR(N-2) and reset by the carry pulse CP output from the (N+2)th stage SR(N+2). However, the invention is not limited to this and can be modified in various ways depending on the number of clock pulses and the phase between the clocks.

[0062] Figure 3 This is a specific circuit diagram of the Nth level SR(N) according to an embodiment of the present invention.

[0063] exist Figure 3 In this circuit, the set signal Set can be the start pulse VST, the carry pulse CP output from the previous stage, or the set signal Set input from an external source, and the reset signal Reset can be the carry pulse CP output from the next stage or the reset signal Reset input from an external source.

[0064] In addition, the Set and Reset signals can use either the carry clock signal CRCLK or the scan clock signal SCCLK.

[0065] The Nth level configuration according to the implementation method will be described below.

[0066] like Figure 3As shown, the Nth stage includes: a node controller 11, which controls the voltage of the first node Q-node and the second node QB-node according to the set signal Set and the reset signal Reset; a carry pulse output unit 12, which outputs a first carry clock CRCLK1 as a carry pulse CP according to the voltage of the first node Q-node and the second node QB-node; a first scan pulse output unit 13, which outputs a first scan clock SCCLK1 as a first scan pulse SP (1) according to the voltage of the first node Q-node and the second node QB-node; a second scan pulse output unit 14, which outputs a second scan clock SCCLK2 as a second scan pulse SP (2) according to the voltage of the first node Q-node and the second node QB-node; a third scan pulse output unit 15, which outputs a third scan clock SCCLK3 as a third scan pulse SP (3) according to the voltage of the first node Q-node and the second node QB-node; and a fourth scan pulse output unit 16, which outputs a fourth scan clock SCCLK4 as a fourth scan pulse SP (4) according to the voltage of the first node Q-node and the second node QB-node.

[0067] The node controller 11 performs a control operation that makes the voltage phase of the first node Q-node and the voltage phase of the second node QB-node opposite to each other, and performs a control operation that makes the high-level portion of the voltage of the first node Q-node shorter than the high-level portion of the voltage of the second node QB-node.

[0068] Each of the carry pulse output unit 12 and the first scan pulse output units 13 to the fourth scan pulse output units 16 has the same configuration.

[0069] That is, each of the carry pulse output unit 12 and the first scan pulse output units 13 to the fourth scan pulse output units 16 includes: a pull-up transistor T6cr, T6-1, T6-2, T6-3 or T6-4 that is turned on or off according to the voltage of the first node Q-node to output the carry clock or the corresponding scan clock to the output terminal; a pull-down transistor T7cr, T7-1, T7-2, T7-3 or T7-4 that is turned on or off according to the voltage of the second node QB-node to output the low-voltage power GVSS to the output terminal; and a capacitor Cq0, Cq1, Cq2, Cq3 or Cq4 connected between the first node Q-node and the output terminal to bootstrap the gate voltage of each pull-up transistor.

[0070] Figure 3The example illustrates an Nth stage comprising one carry pulse output unit and four scan pulse output units. However, the invention is not limited thereto. In the gate drive circuit of the present invention, the Nth stage may include one carry pulse output unit and at least two scan pulse output units.

[0071] The operation of the gate drive circuit according to a comparative example of the present invention, configured as described above, will now be described.

[0072] First, the operation of the gate drive circuit according to the comparative example will be described below.

[0073] Figure 4 This is a schematic input / output waveform diagram of a gate drive circuit according to a comparative example of the present invention; and Figure 5 The diagram illustrates, more specifically, the input / output waveforms of the gate drive circuit according to a comparative example of the present invention.

[0074] like Figure 4 As shown, when the start signal VST or carry pulse CP output from the first two stages (stage (N-2)) is input at a high level, the node controller 11 applies a high voltage GVDD to the first node Q-node and a low voltage GVSS2 to the second node QB-node.

[0075] In this state, when the first scan clock SCCLK1 is input at a high level, the first scan pulse output unit 13 bootstraps the first node Q-node through the first capacitor Cq1. The pull-up transistor T6-1 of the first scan pulse output unit 13 is turned on, and the pull-down transistor T7-1 is turned off. Therefore, the first scan clock SCCLK1 is output as the first scan pulse SP(1).

[0076] When the second scan clock SCCLK2 is input at a high level, the second scan pulse output unit 14 bootstraps the first node Q-node through the second capacitor Cq2, the pull-up transistor T6-2 of the second scan pulse output unit 14 is turned on, and the pull-down transistor T7-2 is turned off. Therefore, the second scan clock SCCLK2 is output as the second scan pulse SP(2).

[0077] When the third scan clock SCCLK3 is input at a high level, the third scan pulse output unit 15 bootstraps the first node Q-node through the third capacitor Cq3, the pull-up transistor T6-3 of the third scan pulse output unit 15 is turned on, and the pull-down transistor T7-3 is turned off. Therefore, the third scan clock SCCLK3 is output as the third scan pulse SP(3).

[0078] When the fourth scan clock SCCLK4 is input at a high level, the fourth scan pulse output unit 16 bootstraps its first node Q-node through the fourth capacitor Cq4. The pull-up transistor T6-4 of the fourth scan pulse output unit 16 is turned on, and the pull-down transistor T7-4 is turned off. Therefore, the fourth scan clock SCCLK4 is output as the fourth scan pulse SP(4).

[0079] The carry pulse output unit 12 bootstraps the first node Q-node through capacitor Cq0. The pull-up transistor T6cr of the carry pulse output unit 12 is turned on, and the pull-down transistor T7cr is turned off, thereby outputting the first carry clock CRCLK1 as the carry pulse CP.

[0080] In the comparative examples, such as Figure 4 As shown, the execution driver makes the phase of the first carry clock CRCLK1 and the phase of the fourth scan clock SCCLK4 the same.

[0081] For this reason, such as Figure 4 and Figure 5 As shown, a voltage difference appears at the first node Q-node. Furthermore, due to the voltage difference at the first node Q-node, the rise time of the first scan pulse SP(1) output from the first scan pulse output unit 13 and the maximum voltage characteristics of the third scan pulse SP(3) output from the third scan pulse output unit 15 are different from other scan pulses, and a 4-line blur phenomenon appears on the screen.

[0082] Therefore, it is necessary to improve the output characteristics of each scan pulse output unit.

[0083] Figure 6 This is a schematic illustration of the input / output waveforms of a gate drive circuit according to an embodiment of the present invention, and Figure 7 The diagram illustrates, more specifically, the input / output waveforms of the gate drive circuit according to an embodiment of the present invention, and illustrates the case where the first carry clock CRCLK1 goes high before the first scan clock SCCLK1 goes high.

[0084] like Figure 6 As shown, when the start signal VST or carry pulse CP output from the first two stages (the (N+2)th stage) is input at a high level, the node controller 11 applies a high-level voltage GVDD to the first node Q-node and applies a low-level voltage GVSS2 to the second node QB-node.

[0085] In this state, when the first carry clock CRCLK1 is input at a high level, the carry pulse output unit 12 bootstraps its first node Q-node through capacitor Cq0. The pull-up transistor T6cr of the carry pulse output unit 12 is turned on, and the pull-down transistor T7cr is turned off. Therefore, the first carry clock CRCLK1 is output as the carry pulse CP.

[0086] As described above, the carry pulse CP output from the carry pulse output unit 12 of the Nth stage SR(N) resets the node controller of the previous stage (e.g., the (N-2)th stage) and sets the node controller of the subsequent stage (e.g., the (N+2)th stage).

[0087] When the first scan clock SCCLK1 is input at a high level, the first scan pulse output unit 13 bootstraps the first node Q-node through the first capacitor Cql. The pull-up transistor T6-1 of the first scan pulse output unit 13 is turned on, and the pull-down transistor T7-1 is turned off. Therefore, the first scan clock SCCLK1 is output as the first scan pulse SP(1).

[0088] When the second scan clock SCCLK2 is input at a high level, the second scan pulse output unit 14 bootstraps the first node Q-node through the second capacitor Cq2. The pull-up transistor T6-2 of the second scan pulse output unit 14 is turned on, and the pull-down transistor T7-2 is turned off. Therefore, the second scan clock SCCLK2 is output as the second scan pulse SP(2).

[0089] When the third scan clock SCCLK3 is input at a high level, the third scan pulse output unit 15 bootstraps the first node Q-node through the third capacitor Cq3. The pull-up transistor T6-3 of the third scan pulse output unit 15 is turned on, and the pull-down transistor T7-3 is turned off. Therefore, the third scan clock SCCLK3 is output as the third scan pulse SP(3).

[0090] When the fourth scan clock SCCLK4 is input at a high level, the fourth scan pulse output unit 16 bootstraps its first node Q-node through the fourth capacitor Cq4. The pull-up transistor T6-4 of the fourth scan pulse output unit 16 is turned on, and the pull-down transistor T7-4 is turned off. Therefore, the fourth scan clock SCCLK4 is output as the fourth scan pulse SP(4).

[0091] In embodiments of the present invention, such as Figure 6 As shown, before the first scan clock SCCLK1 goes high, the first carry clock CRCLK1 goes high and remains high for two horizontal cycles (2H). Figure 6This example illustrates that the first carry clock CRCLK1 goes high one horizontal cycle (1H) earlier than the first scan clock SCCLK1.

[0092] In addition, after the fourth scan clock SCCLK4 goes high, the first carry clock CRCLK1 goes high and remains high for two horizontal cycles (2H). Figure 6 It is shown that the first carry clock CRCLK1 goes high one horizontal cycle (1H) later than the fourth scan clock SCCLK4.

[0093] Thus, before the first scan clock SCCLK1 goes high, the first carry clock CRCLK1 goes high and remains high for two horizontal cycles (2H). After the fourth scan clock SCCLK4 goes high, the first carry clock CRCLK1 goes high and remains high for two horizontal cycles (2H).

[0094] Therefore, as Figure 6 and Figure 7 As shown, when the first scan pulse output unit 13 to the fourth scan pulse output unit 16 output scan pulses SP(1) to SP(4), the voltage level of the first node Q-node is maintained at a level higher than that of the reference node. Figure 4 and Figure 5 The comparative example described is more constant. In addition, the deviation in the output characteristics of the scan pulses SP(1) to SP(4) output from the first scan pulse output unit 13 to the fourth scan pulse output unit 16 can be resolved.

[0095] In this invention, when the Nth stage includes one carry pulse output unit and at least two scan pulse output units, the first carry clock CRCLK1 goes high before the scan clock supplied to the first scan pulse output unit goes high, and the first carry clock CRCLK1 remains high for two horizontal cycles (2H). Furthermore, after the scan clock supplied to the last scan pulse output unit goes high, the first carry clock CRCLK1 goes high, and the first carry clock CRCLK1 remains high for two horizontal cycles (2H). Therefore, the deviation in the output characteristics of the scan pulse can be resolved as described above.

[0096] Figure 8 This is a graph comparing the output of the scan pulses according to the comparative example and embodiment of the present invention, and Figure 9 This is a table comparing the maximum voltage, rise time, and fall time of each scan pulse according to the comparative examples and embodiments of the present invention. Figure 8 and Figure 9The illustration shows the case where the first carry clock CRCLK1 goes high before the first scan clock SCCLK1 goes high, according to an embodiment of the present invention.

[0097] like Figure 8 and Figure 9 As shown, according to an embodiment of the present invention, the rise time of the first scan pulse SP(1) and the maximum voltage characteristics of the third scan pulse SP(3) can be improved, and the variation of the maximum voltage and rise time of each scan pulse can be significantly reduced.

[0098] The gate driving circuit according to the present invention having the above-described features and the display device using the gate driving circuit have the following effects.

[0099] In this invention, the level of the first node (Q-node) remains unchanged because a carry clock is provided before the scan clock provided to the first scan pulse output unit and after the scan clock provided to the last scan pulse output unit among the plurality of scan pulse output units.

[0100] Therefore, the deviation in the output characteristics of the scan pulses output from each scan pulse output unit is eliminated.

[0101] In particular, when the first stage includes the first to fourth scan pulse output units, the rise time of the scan pulse output from the first scan pulse output unit and the maximum voltage characteristics of the scan pulse output from the third scan pulse output unit can be improved.

[0102] In addition, the deviations in the maximum voltage and rise time of each scan pulse were significantly reduced.

[0103] Therefore, the gate drive circuit can be driven stably and the display quality can be improved.

[0104] It is evident that those skilled in the art can make various modifications and variations to this invention without departing from its spirit or scope. Therefore, this invention is intended to cover any modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A gate drive circuit comprising a plurality of slave-connected stages, wherein: Level N, where N is a natural number, includes: The node controller is configured to control the voltage of the first node and the second node based on set and reset signals; A carry pulse output unit is configured to receive a carry clock and output the carry clock as a carry pulse based on the voltages of the first node and the second node; and Multiple scan pulse output units are configured to receive multiple scan clocks and output each scan clock as a scan pulse based on the voltages of the first node and the second node. Among the plurality of scan pulse output units, the carry clock is provided before the scan clock provided to the first scan pulse output unit and after the scan clock provided to the last scan pulse output unit. Each of the carry pulse output unit and the plurality of scan pulse output units includes a pull-up transistor that is turned on or off according to the voltage of the first node to output the carry clock or the corresponding scan clock to the output terminal; a pull-down transistor that is turned on or off according to the voltage of the second node to output low-voltage power to the output terminal; and a capacitor connected between the first node and the output terminal to bootstrap the gate voltage of each pull-up transistor.

2. The gate driving circuit according to claim 1, wherein, The plurality of scan pulse output units, including a first scan pulse output unit to a fourth scan pulse output unit, are configured to receive a first scan clock to a fourth scan clock respectively and sequentially output scan pulses; and Before the first scan clock supplied to the first scan pulse output unit is converted to a high level, the carry clock is converted to a high level and maintained at a high level for a specific period of time, and After the fourth scan clock provided to the fourth scan pulse output unit is converted to a high level, the carry clock is converted to a high level and maintains a high level state for a specific period of time.

3. The gate driving circuit according to claim 2, wherein: The first to fourth scan clocks are maintained at a high level for two horizontal cycles and are shifted so that the high levels of adjacent scan clocks overlap during one horizontal cycle; and The carry clock goes high one horizontal cycle earlier than the first scan clock and remains high for two horizontal cycles.

4. The gate driving circuit according to claim 2, wherein: The first to fourth scan clocks are maintained at a high level for two horizontal cycles and are shifted so that the high levels of adjacent scan clocks overlap during one horizontal cycle; and The carry clock switches to high level one horizontal cycle later than the fourth scan clock, and remains high for two horizontal cycles.

5. A display device, comprising: The display panel includes data lines, gate lines, and sub-pixels; The data driving circuit is configured to provide the data line with a data signal of the input image; as well as A gate drive circuit is configured to provide a gate signal to the gate line, wherein: The gate drive circuit includes multiple slave-connected stages. Level N, where N is a natural number, includes: The node controller is configured to control the voltage of the first node and the second node based on set and reset signals; A carry pulse output unit is configured to receive a carry clock and output the carry clock as a carry pulse based on the voltages of the first node and the second node; and Multiple scan pulse output units are configured to receive multiple scan clocks and output each scan clock as a scan pulse based on the voltages of the first node and the second node. Among the plurality of scan pulse output units, the carry clock is provided before the scan clock provided to the first scan pulse output unit and after the scan clock provided to the last scan pulse output unit. Each of the carry pulse output unit and the plurality of scan pulse output units includes a pull-up transistor that is turned on or off according to the voltage of the first node to output the carry clock or the corresponding scan clock to the output terminal; a pull-down transistor that is turned on or off according to the voltage of the second node to output low-voltage power to the output terminal; and a capacitor connected between the first node and the output terminal to bootstrap the gate voltage of each pull-up transistor.

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