Mram chip and method for testing short circuit location of mram chip array

Abstract

The present application provides a MRAM chip, including one or more arrays, each array including row-column distributed memory cells and a plurality of word lines, a plurality of bit lines and a plurality of source lines connected with the memory cells, and each array further including a defect detection circuit for controlling the connection mode of the tested bit lines, comparing the leakage current between the tested bit lines with a reference current, or comparing the leakage voltage between the tested bit lines with a reference voltage, so as to detect whether there is a short circuit fault between each bit line in the array.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a method for testing the short-circuit location of an MRAM chip and an MRAM chip array. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a promising new type of memory with advantages such as simple circuit design, fast read and write speed, unlimited erase and write cycles, and no data loss when power is off.

[0003] The core memory cell of MRAM consists of one magnetic tunnel junction (MTJ) and one field-effect transistor (CMOS). During the manufacturing process of the MTJs, a contact short circuit may occur between some adjacent locations, known as a bottom short. In this case, all MTJs on the black border (BL) containing the two shorted MTJs (excluding the two shorted MTJs themselves) will experience misreading. Simultaneously, the shorted MTJs will also be prone to write errors, leading to inaccurate test results and affecting yield assessment. For example, Figure 1 The diagram illustrates the MRAM array structure, where read and write operations on the MTJs are controlled by disabling SL, BL, and WL. In the diagram, ①, ②, ③, and ④ represent four MTJs. A bottom short occurs between MTJs ① and ②, which leads to the following problem:

[0004] When 0 is written to MTJ (number ③), BL <1> Write voltage VW, SL <1> Following GND, WL <2> If the unselected SL and BL are grounded, then MTJs ① and ② may be written incorrectly.

[0005] When writing 1 to MTJ ①, BL <1> Following GND, SL <1> Write voltage VW, WL <1> If the unselected SL and BL are grounded, then MTJ ② may be written incorrectly.

[0006] When performing a read operation on MTJ number ③, BL <1> Connect to read voltage VR, SL <1> Following GND, WL <2> If the selected pins SL and BL are grounded, the resistance read is ③ / / ①+②. The states of ① and ② affect the reading result of ③, and there is a possibility of reading incorrectly.

[0007] For ease of understanding, Figure 2a The equivalent circuit diagram is shown when 0 is written to MTJ ③. Figure 2b The equivalent circuit diagram is shown when 1 is written to MTJ ①. Figure 2c The equivalent circuit diagram is shown when MTJ ③ is read as 0 or 1, resulting in a misread. Branch A is the normal writing path to MTJ, and branch B is the rewriting path caused by the extra path due to the Bottom Short.

[0008] This demonstrates that a bottom short circuit between two MTJs will directly affect the normal operation of the chip. Therefore, in practical testing, quickly locating the short-circuited MTJ in an MRAM chip array is a problem that must be solved. Summary of the Invention

[0009] To address the aforementioned issues, this invention provides an MRAM chip capable of quickly locating the short-circuited MTJ in an MRAM chip array, promptly repairing it using redundant circuitry, and improving the stability of the MRAM chip.

[0010] On one hand, the present invention provides an MRAM chip comprising one or more arrays, each array further comprising:

[0011] The memory cells are arranged in rows and columns, and each memory cell includes a magnetic tunnel junction and a MOS transistor connected in series;

[0012] Multiple letter lines;

[0013] Pairs of multiple bit lines and multiple source lines; and,

[0014] The defect detection circuit is used to control the connection mode of the bit line under test, compare the leakage current between the bit lines under test with the reference current, or compare the leakage voltage between the bit lines under test with the reference voltage, so as to detect whether there is a short circuit fault between the bit lines inside the array.

[0015] Optionally, the defect detection circuit includes:

[0016] A current-type comparator whose first input terminal receives a reference current;

[0017] Multiple pull-up control transistors connected between each bit line and the second input terminal of the current-type comparator are used to control whether to supply power to the bit line under test so as to generate leakage current at the second input terminal.

[0018] Multiple source line control transistors connected between each source line and the ground line are used to control whether the source line is grounded;

[0019] Multiple bit line control transistors connected between each bit line and the ground line are used to control whether the bit line is grounded;

[0020] The current comparator determines whether there is a short circuit fault between the bit lines being tested by comparing the reference current and the leakage current.

[0021] Optionally, the pull-up control transistor is an NMOS transistor, with its drain connected to the corresponding bit line, its source connected to the second input terminal of the current comparator, and its gate inputting a gating control signal.

[0022] The source line control transistor is an NMOS transistor, with its drain connected to ground, its source connected to the corresponding source line, and its gate input a gating control signal.

[0023] The bit line control transistor is an NMOS transistor, with its drain connected to ground, its source connected to the corresponding bit line, and its gate inputting a gating control signal.

[0024] Optionally, the expression for the reference current is:

[0025] Where Iref represents the reference current, VDD is the internal power supply voltage of the current comparator, Rap represents the resistance value of the magnetic tunnel junction of the memory cell when it is in an antiparallel state, and n≥2.

[0026] Optionally, the defect detection circuit includes:

[0027] A voltage comparator has a reference voltage input at its first input terminal and a power supply connected to its second input terminal via a pull-up resistor.

[0028] Multiple pull-up control transistors connected between each bit line and the second input terminal of the voltage comparator are used to control whether to supply power to the bit line under test so as to generate leakage voltage at the second input terminal.

[0029] Multiple source line control transistors connected between each source line and the ground line are used to control whether the source line is grounded;

[0030] Multiple bit line control transistors connected between each bit line and the ground line are used to control whether the bit line is grounded;

[0031] The voltage comparator determines whether there is a short circuit fault between the bit lines being tested by comparing the reference voltage and the leakage voltage.

[0032] Optionally, the pull-up control transistor is an NMOS transistor, with its drain connected to the corresponding bit line, its source connected to the second input terminal of the voltage comparator, and its gate inputting a gating control signal.

[0033] The source line control transistor is an NMOS transistor, with its drain connected to ground, its source connected to the corresponding source line, and its gate input a gating control signal.

[0034] The bit line control transistor is an NMOS transistor, with its drain connected to ground, its source connected to the corresponding bit line, and its gate inputting a gating control signal.

[0035] Optionally, the expression for the reference voltage is:

[0036] Where Vref represents the reference voltage, VDD is the power supply voltage, and n>1.

[0037] Optionally, the MRAM chip further includes a column address selector and a column address decoder for selecting the bit line to be tested based on the column address.

[0038] Optionally, the MRAM chip further includes: a redundant circuit for repairing the memory cell connected to a bit line that is short-circuited.

[0039] On the other hand, the present invention provides a method for testing the short-circuit location of an MRAM chip array, comprising:

[0040] Select two adjacent bit lines in the array in sequence, control one bit line to be connected to the second input terminal of the current comparator, and the other bit line to be connected to the ground line, and connect all source lines to the ground line;

[0041] The current comparator compares the leakage current between the two bit lines with the reference current input at the first input terminal. If the output is 0, it means that there is no short circuit between the two bit lines, and the test continues; if the output is 1, it means that there is a short circuit between the two bit lines, the address of the failed bit line is recorded, and the test continues.

[0042] After all bitline tests are completed, redundant circuitry is used for repairs.

[0043] On the other hand, the present invention provides a method for testing the short-circuit location of an MRAM chip array, comprising:

[0044] All even-numbered bit lines in the control array are connected to the second input of the current comparator, all odd-numbered bit lines are connected to the ground line, and all source lines are connected to the ground line. The current comparator compares the leakage current input at the second input with the reference current input at the first input. If the output is 0, it means that there is no short circuit in the bit line and the test ends; if the output is 1, it means that there is a short circuit in the bit line and the test continues.

[0045] If a bit line is short-circuited, all bit lines are split into two groups for testing. The even-numbered bit lines in each group are connected to the second input of the current comparator, and the odd-numbered bit lines are connected to the ground. The current comparator compares the leakage current between the even-numbered and odd-numbered bit lines in each group with the reference current to locate the bit line combination with a short circuit.

[0046] The bit line combination with short circuits will be further split into two groups for testing;

[0047] Repeat this process until a faulty bit line is detected, record its address, and repair it using redundant circuitry.

[0048] The present invention provides an MRAM chip in which a defect detection circuit is added to the array structure, which can quickly test short-circuit failures between BLs and improve testing efficiency; and can not only screen out bridging short circuits between BLs, but also screen out bottom short failures between MTJs. Attached Figure Description

[0049] Figure 1 This refers to the array structure of MRAM chips in the prior art;

[0050] Figure 2a for Figure 1 The equivalent circuit diagram for writing 0 to MTJ ③ after short-circuiting MTJ ① and ② in the array structure;

[0051] Figure 2b for Figure 1 After short-circuiting MTJs ① and ② in the array structure, write the equivalent circuit diagram for MTJ ①.

[0052] Figure 2c for Figure 1 The equivalent circuit diagram for reading MTJ ③ after short-circuiting MTJ ① and ② in the array structure;

[0053] Figure 3 This is a basic schematic diagram of the present invention;

[0054] Figure 4 This is an embodiment of the MRAM chip array structure of the present invention;

[0055] Figure 5 This is an array structure of an MRAM chip according to another embodiment of the present invention. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0058] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0059] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0060] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0061] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0062] For well-made array structures, any two adjacent bit lines (BLs) are open circuits, with a theoretical current of 0uA. If a short circuit occurs, a certain leakage current will be generated. The BLs with short circuit failure can be screened by directly comparing the leakage current with a reference current. Figure 3 A basic schematic diagram of the present invention is shown.

[0063] Based on the above principles, one embodiment of the present invention provides an MRAM chip, which includes one or more arrays, such as... Figure 4 As shown, each array further includes:

[0064] The memory cells are arranged in rows and columns, each memory cell including a magnetic tunnel junction and a MOS transistor connected in series, with one end of the magnetic tunnel junction connected to the drain of the MOS transistor;

[0065] Multiple word lines WL <0> ~WL <n>Each word line is connected to the gate of the MOS transistor contained in one of the multiple memory cells in a row;

[0066] Paired multi-bit lines BL <0> ~BL <n>and multiple source lines SL <0> ~SL <n>Each bit line is connected to the other end of a magnetic tunnel junction contained in one of the columns of memory cells, and each source line is connected to the source of a MOS transistor contained in one of the columns of memory cells; and,

[0067] The defect detection circuit controls the connection method of the bit line under test, compares the leakage current between the bit lines under test with the reference current, or compares the leakage voltage between the bit lines under test with the reference voltage, so as to detect whether there is a short circuit fault between the bit lines inside the array.

[0068] Alternatively, as one implementation method, Figure 4 The array structure illustrates a feasible circuit structure for a defect detection circuit. This defect detection circuit includes:

[0069] The current-type comparator SA has an internal power supply VDD, and the first input terminal is a reference current.

[0070] Connected to each bit line BL <0> ~BL <n-1>Multiple pull-up control transistors M between the second input terminal of the current comparator 03 ~M (n-1)3 This is used to control whether to supply power to the bit line under test so as to generate leakage current at the second input terminal. The leakage current is the current caused by a short circuit between the bit lines under test.

[0071] Connected to each source line SL <0> ~SL <n>Multiple source line control transistors M between ground GND 01 ~M n1 This is used to control whether the source line is grounded;

[0072] Connected to each bit line BL <0> ~BL <n>Multiple bit line control transistors M between ground GND 02 ~M n2 This is used to control whether the bit line is grounded;

[0073] The current-type comparator determines whether there is a short circuit fault between the bit lines being tested by comparing the reference current at the first input terminal and the leakage current at the second input terminal.

[0074] This also shows that the bit line BL <n>No pull-up control transistor is required between the current comparator and the second input terminal.

[0075] Furthermore, for ease of circuit implementation, all transistors used in this embodiment are NMOS transistors, and their connection relationships are as follows:

[0076] Source control transistor M connected between each source line and ground line 01 ~M n1 The drain is connected to ground, the source is connected to the corresponding source line, and the gate input is the gating control signal.

[0077] Bit line control transistor M connected between each bit line and ground line 02 ~M n2 The drain is connected to ground, the source is connected to the corresponding bit line, and the gate input is the gating control signal.

[0078] Pull-up control transistor M connected between each bit line and the second input of the current comparator 03 ~M (n-1)3 The drain is connected to the corresponding bit line, the source is connected to the second input terminal of the current comparator, and the gate input is the gating control signal.

[0079] Optionally, when comparing the reference current and the leakage current in a current-type comparator, the setting of the reference current is also crucial. In this embodiment, the expression for the reference current is:

[0080] Where Iref represents the reference current, VDD is the internal power supply voltage of the current comparator, Rap represents the resistance value of the magnetic tunnel junction of the memory cell when it is in an antiparallel state, and n≥2.

[0081] Alternatively, as another implementation method, Figure 5 The array structure illustrates another feasible circuit structure for a defect detection circuit. This defect detection circuit includes:

[0082] The voltage comparator SA has a reference voltage input at its first input terminal and its second input terminal connected to the power supply VDD via a pull-up resistor.

[0083] Connected to each bit line BL <0> ~BL <n-1>Multiple pull-up control transistors M between the second input terminal of the voltage comparator 03 ~M (n-1)3 This is used to control whether to supply power to the bit line under test so as to generate a leakage voltage at the second input terminal, which is the voltage caused by a short circuit between the bit lines under test.

[0084] Connected to each source line SL <0> ~SL <n>Multiple source line control transistors M between ground GND 01 ~M n1 This is used to control whether the source line is grounded;

[0085] Connected to each bit line BL <0> ~BL <n>Multiple bit line control transistors M between ground GND 02 ~M n2 This is used to control whether the bit line is grounded;

[0086] The voltage comparator determines whether there is a short circuit fault between the bit lines under test by comparing the reference voltage at the first input terminal and the leakage voltage at the second input terminal.

[0087] For ease of circuit implementation, all transistors used in this embodiment are NMOS transistors, and their connection relationships are as follows:

[0088] Pull-up control transistor M 03 ~M (n-1)3 The drain is connected to the corresponding bit line, the source is connected to the second input terminal of the voltage comparator, and the gate input is the gating control signal.

[0089] Source line control transistor M 01 ~M n1 The drain is connected to ground, the source is connected to the corresponding source line, and the gate input is the gating control signal.

[0090] Bit line control transistor M 02 ~M n2 The drain is connected to ground, the source is connected to the corresponding bit line, and the gate input is the gating control signal.

[0091] Optionally, the expression for the reference voltage used in this embodiment is:

[0092] Where Vref represents the reference voltage, VDD is the power supply voltage, and n>1.

[0093] Additionally, the MRAM chip may include a column address selector and a column address decoder to select the bit line to be tested based on the column address, as well as redundant circuitry to repair memory cells connected to bit lines that are short-circuited.

[0094] The MRAM chip provided in this embodiment of the invention can quickly test short-circuit failures between BLs by adding a defect detection circuit in the array, thereby improving testing efficiency; and it can not only screen out bridging short circuits between BLs, but also screen out bottom short failures between MTJs.

[0095] On the other hand, using the aforementioned MRAM chip, this embodiment of the invention provides a method for testing the short-circuit location of an MRAM chip array, including:

[0096] Select two adjacent bit lines in the array in sequence, control one bit line to be connected to the second input terminal of the current comparator, and the other bit line to be connected to the ground line, and connect all source lines to the ground line;

[0097] The current comparator compares the leakage current between the two bit lines with the reference current input at the first input terminal. If the output is 0, it means that there is no short circuit between the two bit lines, and the test continues; if the output is 1, it means that there is a short circuit between the two bit lines, the address of the failed bit line is recorded, and the test continues.

[0098] After all bitline tests are completed, redundant circuitry is used for repairs.

[0099] Specifically, the test sequence can be from low to high or from high to low address, and the address of the failed bit line can be recorded. For example, from BL... <0> To BL <n>Test in sequence, first select BL <0> and BL <1> BL <0> Connected to the second input terminal of the current comparator, BL <1> Connect all elements to GND, leave the remaining elements (BL) floating, connect all elements (SL) to GND, and connect all elements (WL) to GND to put the array in a shutdown state. Figure 4 This shows the state of each transistor under the current test conditions; the current-mode comparator will display the BL... <0> and BL <1> The leakage current between the two input terminals is compared with the reference current at the first input terminal. The expression for the reference current is:

[0100] Where Iref represents the reference current, VDD is the internal power supply voltage of the current comparator, Rap represents the resistance value of the magnetic tunnel junction of the memory cell when it is in an antiparallel state, and n≥2.

[0101] If the leakage current between the two BLs is less than the reference current, the current comparator output is 0, indicating that there is no short circuit between the two BLs. If the leakage current between the two BLs is greater than the reference current, the current comparator output is 1, indicating that there is a short circuit between the two BLs, and the address of the failed BL is recorded.

[0102] Continue testing, select BL <1> and BL <2> BL <1> Connected to the second input terminal of the current comparator, BL <2> Connect to GND, and the current-mode comparator compares BL. <1> and BL <2> If the leakage current between the two BLs is less than the reference current, the current comparator outputs 0, indicating that there is no short circuit between the two BLs. If the leakage current between the two BLs is greater than the reference current, the current comparator outputs 1, indicating that there is a short circuit between the two BLs, and the address of the failed BL is recorded.

[0103] Subsequent bit lines were tested sequentially using the method described above. Once the BL test was completed... <n-1>and BL <n>After that, the testing process ends. Therefore, the bit line BL... <n>No gating transistor is required between the second input of the current comparator and the current-type comparator.

[0104] Once all faulty black bars (BLs) are located, they can be screened out through testing or their addresses can be marked and repaired using redundant circuitry.

[0105] This test method involves applying a constant voltage to one of two adjacent bottom loops (BLs) and grounding the other. A current-type comparator is used to compare the leakage current between the two BLs with a reference current to determine whether there is a short circuit between the two adjacent BLs. If there is a short circuit between the two BLs, the MTJ that caused the bottom short can be located.

[0106] On the other hand, another embodiment of the present invention provides a method for testing the short-circuit location of an MRAM chip array, comprising:

[0107] Connect all even-numbered bit lines in the array to the second input of the current comparator, connect all odd-numbered bit lines to ground, and connect all source lines to ground. The current comparator compares the leakage current input at the second input with the reference current input at the first input. If the output is 0, it means that there is no short circuit in the bit lines, and the test ends; if the output is 1, it means that there is a short circuit in the bit lines, and the test continues.

[0108] If a bit line is short-circuited, all bit lines are split into two groups for testing. The even-numbered bit lines in each group are connected to the second input of the current comparator, and the odd-numbered bit lines are connected to the ground. The current comparator compares the leakage current between the even-numbered and odd-numbered bit lines in each group with the reference current to locate the bit line combination with a short circuit.

[0109] The bit line combination with short circuits will be further split into two groups for testing;

[0110] Repeat this process until a faulty bit line is detected, record its address, and repair it using redundant circuitry.

[0111] For example, if a short circuit exists on a bit line, and there are n bit lines in total, where n is an even number, in the first n / 2 bit lines, the even-numbered BLs are connected to the second input terminal of the current-mode comparator, and the odd-numbered BLs are connected to GND. The current-mode comparator compares the leakage current input to the second input terminal with the reference current input to the first input terminal to determine if a short circuit failure exists. Then, in the next n / 2 bit lines, the even-numbered BLs are connected to the second input terminal of the current-mode comparator, and the odd-numbered BLs are connected to GND. The current-mode comparator compares the leakage current input to the second input terminal with the reference current input to the first input terminal to determine if a short circuit failure exists. If a short circuit is located in either the first n / 2 bit lines or the next n / 2 bit lines, the line is further split into two groups for testing. This continues until the failed bit line is detected. Of course, it is possible that both groups of BLs may have short circuit failures; in this case, the line must be split into two groups for testing separately.

[0112] The testing method in this embodiment of the invention is based on the binary search method, which can improve testing efficiency compared to the cyclic testing of two adjacent bit lines.

[0113] Of course, it should be noted that the implementation steps are the same when using a voltage comparator to perform the above tests, and can be referred to for implementation, without further elaboration.

[0114] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. An MRAM chip, characterized in that, Includes one or more arrays, each array further including: The memory cells are arranged in rows and columns, and each memory cell includes a magnetic tunnel junction and a MOS transistor connected in series; Multiple letter lines; Pairs of multiple bit lines and multiple source lines; and, A defect detection circuit is used to control the connection mode of the bit line under test and compare the leakage current between the bit lines under test with the reference current in order to detect whether there is a short circuit fault between the bit lines inside the array. The defect detection circuit includes: A current-type comparator has a reference current input at its first input terminal, and the expression for the reference current is: Where Iref represents the reference current, VDD is the internal power supply voltage of the current comparator, Rap represents the resistance value of the magnetic tunnel junction of the memory cell when it is in antiparallel state, n≥2, and n represents the total number of bit lines minus 1; Multiple pull-up control transistors connected between each bit line and the second input terminal of the current-type comparator are used to control whether to supply power to the bit line under test so as to generate leakage current at the second input terminal. Multiple source line control transistors connected between each source line and the ground line are used to control whether the source line is grounded; Multiple bit line control transistors connected between each bit line and the ground line are used to control whether the bit line is grounded; The current comparator determines whether there is a short circuit fault between the bit lines being tested by comparing the reference current and the leakage current.

2. The MRAM chip according to claim 1, characterized in that, The pull-up control transistor is an NMOS transistor, with its drain connected to the corresponding bit line, its source connected to the second input terminal of the current comparator, and its gate inputting a gating control signal. The source line control transistor is an NMOS transistor, with its drain connected to ground, its source connected to the corresponding source line, and its gate input a gating control signal. The bit line control transistor is an NMOS transistor, with its drain connected to ground, its source connected to the corresponding bit line, and its gate inputting a gating control signal.

3. An MRAM chip, characterized in that, Includes one or more arrays, each array further including: The memory cells are arranged in rows and columns, and each memory cell includes a magnetic tunnel junction and a MOS transistor connected in series; Multiple letter lines; Pairs of multiple bit lines and multiple source lines; and, A defect detection circuit is used to control the connection mode of the bit line under test and compare the leakage voltage between the bit lines under test with the reference voltage in order to detect whether there is a short circuit fault between the bit lines inside the array. The defect detection circuit includes: A voltage comparator has a reference voltage input at its first input terminal and its second input terminal connected to a power supply via a pull-up resistor. The expression for the reference voltage is: , where Vref represents the reference voltage, VDD is the power supply voltage, n>1, and n represents the total number of bit lines minus 1; Multiple pull-up control transistors connected between each bit line and the second input terminal of the voltage comparator are used to control whether to supply power to the bit line under test so as to generate leakage voltage at the second input terminal. Multiple source line control transistors connected between each source line and the ground line are used to control whether the source line is grounded; Multiple bit line control transistors connected between each bit line and the ground line are used to control whether the bit line is grounded; The voltage comparator determines whether there is a short circuit fault between the bit lines being tested by comparing the reference voltage and the leakage voltage.

4. The MRAM chip according to claim 3, characterized in that, The pull-up control transistor is an NMOS transistor, with its drain connected to the corresponding bit line, its source connected to the second input terminal of the voltage comparator, and its gate inputting a gating control signal. The source line control transistor is an NMOS transistor, with its drain connected to ground, its source connected to the corresponding source line, and its gate input a gating control signal. The bit line control transistor is an NMOS transistor, with its drain connected to ground, its source connected to the corresponding bit line, and its gate inputting a gating control signal.

5. The MRAM chip according to claim 1 or 3, characterized in that, The MRAM chip also includes a column address selector and a column address decoder, used to select the bit line to be tested based on the column address.

6. The MRAM chip according to claim 1 or 3, characterized in that, The MRAM chip also includes a redundant circuit for repairing memory cells connected to bit lines that are short-circuited.

7. A method for testing the short-circuit location of an MRAM chip array, characterized in that, Based on the MRAM chip as described in claim 1, the testing method includes: Select two adjacent bit lines in the array in sequence, control one bit line to be connected to the second input terminal of the current comparator, and the other bit line to be connected to the ground line, and connect all source lines to the ground line; The current comparator compares the leakage current between the two bit lines with the reference current input at the first input terminal. If the output is 0, it means that there is no short circuit between the two bit lines, and the test continues; if the output is 1, it means that there is a short circuit between the two bit lines, the address of the failed bit line is recorded, and the test continues. After all bitline tests are completed, redundant circuitry is used for repairs.

8. A method for testing the short-circuit location of an MRAM chip array, characterized in that, Based on the MRAM chip as described in claim 1, the testing method includes: All even-numbered bit lines in the control array are connected to the second input of the current comparator, all odd-numbered bit lines are connected to the ground line, and all source lines are connected to the ground line. The current comparator compares the leakage current input at the second input with the reference current input at the first input. If the output is 0, it means that there is no short circuit in the bit line and the test ends; if the output is 1, it means that there is a short circuit in the bit line and the test continues. If a bit line is short-circuited, all bit lines are split into two groups for testing. The even-numbered bit lines in each group are connected to the second input of the current comparator, and the odd-numbered bit lines are connected to the ground. The current comparator compares the leakage current between the even-numbered and odd-numbered bit lines in each group with the reference current to locate the bit line combination with a short circuit. The bit line combination with short circuits will be further split into two groups for testing; Repeat this process until a faulty bit line is detected, record its address, and repair it using redundant circuitry.

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