Semiconductor Structure and Testing Methods

Abstract

A semiconductor structure and testing method are disclosed. The structure includes: a testing body comprising a first substrate, a second substrate, and a deep trench isolation structure. The first substrate includes adjacent first and second device regions and has a first doped ion concentration of a first concentration. The second substrate is located on the first substrate of the first and second device regions and has a second doped ion concentration of a second concentration, wherein the first and second doped ions have the same conductivity type, and the second concentration is less than the first concentration. The deep trench isolation structure penetrates both sides of the second substrate of the first and second device regions. A signal loading section includes a first interconnect structure and a second interconnect structure. The first interconnect structure is located on top of the second substrate of the first device region and serves as a first test signal loading terminal. The second interconnect structure is located on top of the second substrate of the second device region and serves as a second test signal loading terminal. This invention improves the testing accuracy of semiconductor structures.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and testing method. Background Technology

[0002] In the semiconductor field, adjacent device regions are typically isolated using deep trench isolation (DTI) structures. DTI structures are filled with materials for isolation. However, the contact surface between the DTI structure and the film layers in adjacent device regions is prone to defects. This is particularly prominent in the structure of photoelectric sensors.

[0003] A photoelectric sensor is a device that converts optical signals into electrical signals. Its working principle is based on the photoelectric effect, which refers to the effect where, when light shines on certain materials, electrons in the material absorb the energy of photons, generating free charge carrier pairs. Under the influence of an electric field, this produces a current, thus converting the optical signal into an electrical signal. Photoelectric sensors all have a pixel area of ​​a certain size, used to receive optical signals and complete the photoelectric conversion.

[0004] In a single-photon avalanche diode (SPAD) sensor, the pixel area is typically composed of multiple pixel units arranged in an array. Each pixel unit contains a SPAD device, and adjacent SPAD devices are isolated by a DTI structure. The DTI structure is filled with material for optical and electrical isolation. However, the contact surface between the DTI structure and the pixel unit is prone to some defects, which affect the optical and electrical performance of the SPAD. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and testing method to improve the testing accuracy of semiconductor structures.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a test body portion, the test body portion including a first substrate, a second substrate, and a deep trench isolation structure, wherein the first substrate includes adjacent first device regions and second device regions, and the first substrate has first doped ions; the second substrate is located on the first substrate of the first device regions and the second device regions, and the second substrate has second doped ions, wherein the first doped ions and the second doped ions have the same conductivity type, and the concentration of the second doped ions is less than the concentration of the first doped ions; the deep trench isolation structure passes through the second substrates on both sides of the first device regions and the second device regions respectively, and extends into the first substrate, the first device regions and the second device regions sharing the same deep trench isolation structure at the junction; and a signal loading portion, including a first interconnect structure and a second interconnect structure, the first interconnect structure being located on top of the second substrate of the first device region and electrically connected to the second substrate, the first interconnect structure serving as a first test signal loading terminal; the second interconnect structure being located on top of the second substrate of the second device region and electrically connected to the second substrate, the second interconnect structure serving as a second test signal loading terminal.

[0007] Accordingly, this embodiment of the invention also provides a testing method, comprising: providing the semiconductor structure described in this embodiment of the invention; loading a test signal onto the first test signal loading terminal and the second test signal loading terminal, for making the first substrate, the second substrate of the first device region, the second substrate of the second device region, the first interconnect structure and the second interconnect structure constitute a test path; obtaining the resistance of the test path; and obtaining the inversion layer thickness of the corresponding second substrate sidewall based on the resistance.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure provided by this invention, test signals are applied to the second substrates of the first and second device regions, respectively, through a first interconnect structure and a second interconnect structure. This forms a test path comprised of the first interconnect structure, the second substrate of the first device region, the first substrate, the second substrate of the second device region, and the second interconnect structure. The test path is then tested to obtain its electrical signal, characterizing the distribution of doped ions in the second substrate. Compared to semiconductor structures tested by placing probes on the cross-section of the semiconductor structure, this invention avoids the need to expose the cross-section of the semiconductor structure, thus preventing damage. It also avoids sample preparation errors caused by cutting the semiconductor structure to obtain the cross-section, and avoids cost waste due to damage to the semiconductor structure. Furthermore, compared to the method of testing semiconductor structures by placing probes, which has higher requirements for probe placement, a greater impact of probe signals on test results, and larger human error, this invention effectively avoids large test errors caused by repeated use of probes, thereby improving the testing accuracy of semiconductor structures.

[0010] In the testing method provided by this invention, test signals are applied to the second substrates of the first and second device regions, respectively, through a first interconnect structure and a second interconnect structure. This forms a test path comprised of the first interconnect structure, the second substrate of the first device region, the first substrate, the second substrate of the second device region, and the second interconnect structure. The test path is then tested to obtain its electrical signal, characterizing the distribution of doped ions in the second substrate. Compared to testing semiconductor structures by setting probes on the cross-section of the semiconductor structure, this invention avoids the need to expose the cross-section of the semiconductor structure, thus preventing damage. It also avoids sample preparation errors caused by cutting the semiconductor structure to obtain the cross-section, and avoids cost waste due to damage to the semiconductor structure. Furthermore, compared to the method of testing semiconductor structures by setting probes, which has higher requirements for probe setup, a greater impact of probe signals on test results, and larger human error, this invention effectively avoids large test errors caused by repeated use of probes, thereby improving the testing accuracy of semiconductor structures. Attached Figure Description

[0011] Figures 1 to 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figure 4 This is a flowchart of the steps of an embodiment of the testing method of the present invention. Detailed Implementation

[0013] As known from the background technology, a pixel region with a certain area in a photoelectric sensor is used to receive optical signals. The pixel region usually includes multiple sub-pixel regions arranged in an array. In order to obtain a device with better quality, the sub-pixel regions are usually fabricated in a substrate with a low doping concentration. A DTI structure is formed between adjacent sub-pixel regions. Under the current process conditions, due to factors such as plasma charging required by the process and atomic-level defects at the heterojunction during material deposition, the interface of the fabricated DTI structure near the substrate is prone to carrying stable positive or negative charges. Generally, when the filling material of the DTI structure is silicon oxide, the DTI sidewalls are positively charged, and when the filling material of the DTI structure is a high-k material, the DTI sidewalls are negatively charged. Here, the high-k material is a material with a K value greater than or equal to 7, such as hafnium oxide or aluminum oxide. When the majority carriers of doped ions in the substrate have the same charge as the sidewalls of the DTI structure, the majority carriers on the sidewalls are repelled due to the principle of like charges repelling each other. Consequently, minority carriers with opposite charges are drawn out to the sidewalls of the substrate. As a result, concentrated inversion charges tend to accumulate at the location where the substrate contacts the sidewalls of the DTI structure. The inversion layer formed by the concentrated inversion charges will affect the working performance of the photoelectric sensor. Therefore, it is necessary to obtain the distribution of inversion doped ions in the substrate through testing to provide a reference for subsequent device design rules and manufacturing process adjustments.

[0014] In order to detect the distribution of inversion charge in the substrate of a photoelectric sensor, a semiconductor structure with the same DTI structure and substrate as that in the photoelectric sensor is formed. The distribution of inversion charge in the substrate of the photoelectric sensor is characterized by testing the semiconductor structure.

[0015] In existing technologies, scanning capacitance microscopy (SCM) or scanning spreading resistance microscopy (SSRM) are commonly used to detect the morphology, size, and characteristics of the ion implantation distribution region in the cross-section of a structure. However, both SCM and SSRM require testing on the cross-section of the device, which necessitates cutting the semiconductor structure to expose the cross-section. This can easily lead to sample preparation errors and wastes process resources by damaging the semiconductor structure. Furthermore, the placement of probes on the cross-section requires high precision in terms of probe quality and positioning, which can also lead to human error. After repeated use, probes are prone to wear or contamination, causing testing errors and affecting the accuracy of the test.

[0016] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure, comprising: a test body portion, the test body portion including a first substrate, a second substrate, and a deep trench isolation structure, wherein the first substrate includes adjacent first device regions and second device regions, and the first substrate has first doped ions; the second substrate is located on the first substrate of the first device regions and the second device regions, and the second substrate has second doped ions, wherein the first doped ions and the second doped ions have the same conductivity type, and the concentration of the second doped ions is less than the concentration of the first doped ions; the deep trench isolation structure passes through the second substrates on both sides of the first device regions and the second device regions respectively, and extends into the first substrate, the first device regions and the second device regions sharing the same deep trench isolation structure at their junction; and a signal loading portion, including a first interconnect structure and a second interconnect structure, the first interconnect structure being located on top of the second substrate of the first device region and electrically connected to the second substrate, the first interconnect structure serving as a first test signal loading terminal; the second interconnect structure being located on top of the second substrate of the second device region and electrically connected to the second substrate, the second interconnect structure serving as a second test signal loading terminal.

[0017] In the semiconductor structure provided by this invention, test signals are applied to the second substrates of the first and second device regions, respectively, through a first interconnect structure and a second interconnect structure. This forms a test path comprised of the first interconnect structure, the second substrate of the first device region, the first substrate, the second substrate of the second device region, and the second interconnect structure. The test path is then tested to obtain its electrical signal, characterizing the distribution of doped ions in the second substrate. Compared to semiconductor structures tested by placing probes on the cross-section of the semiconductor structure, this invention avoids the need to expose the cross-section of the semiconductor structure, thus preventing damage. It also avoids sample preparation errors caused by cutting the semiconductor structure to obtain the cross-section, and avoids cost waste due to damage to the semiconductor structure. Furthermore, compared to the method of testing semiconductor structures by placing probes, which has higher requirements for probe placement, a greater impact of probe signals on test results, and larger human error, this invention effectively avoids large test errors caused by repeated use of probes, thereby improving the testing accuracy of semiconductor structures.

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Figures 1 to 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 1 and Figure 2 These are two top views of the semiconductor structure included in this invention. Figure 3 yes Figure 1 and Figure 2 Sectional view based on the AA direction.

[0020] The semiconductor structure includes a test body 10, which includes a first substrate 100, a second substrate 110, and a deep trench isolation structure 200. The first substrate 100 includes adjacent first device regions 100a and 100b, and has a first doped ion concentration of a first concentration. The second substrate 110 is located on the first substrate 100 of the first device regions 100a and 100b, and has a second doped ion concentration of a second concentration. The first and second doped ions have the same conductivity type, and the second concentration is less than the first concentration. The deep trench isolation structure 200 penetrates both the first and second device regions 100a and 100b. The second substrates 110 on both sides of 00b extend into the first substrate 100. The first device region 100a and the second device region 100b share the same deep trench isolation structure 200 at their junction. The signal loading section 20 includes a first interconnect structure 301 and a second interconnect structure 300. The first interconnect structure 301 is located on top of the second substrate 110 of the first device region 100a and is electrically connected to the second substrate 110. The first interconnect structure 301 is used as a first test signal loading terminal. The second interconnect structure 300 is located on top of the second substrate 110 of the second device region 100b and is electrically connected to the second substrate 110. The second interconnect structure 300 is used as a second test signal loading terminal.

[0021] In this embodiment, the semiconductor structure is the semiconductor structure of the optical device. The optical device has the same structure as the second substrate 110 and the deep trench isolation structure 200 in the test body 10. Thus, the performance of the optical device can be characterized by testing the semiconductor structure, and the design and process of the optical device can be adjusted accordingly based on the test results of the semiconductor structure.

[0022] As one embodiment, the optical device includes a single SPAD sensor. In other embodiments, the optical device may also be a charge-coupled device (CCD) image sensor, a CMOS image sensor, a direct time-of-flight (DTOF) sensor, or an indirect time-of-flight (iTOF) sensor, etc.

[0023] The first substrate 100 provides the basis for the process operation of forming the semiconductor structure. Specifically, the first substrate 100 is a silicon first substrate. In other embodiments, the material of the first substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the first substrate may also be other types of first substrates such as silicon on insulator or germanium on insulator.

[0024] According to the actual layout design, such as Figure 1 As shown, the first device region 100a and the second device region 100b are along the first direction (e.g., Figure 1 Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 2 (As shown in the Y direction) adjacent to each other, with the first direction and the second direction perpendicular to each other; or, as... Figure 2 As shown, the first device region 100a surrounds the second device region 100b.

[0025] In this embodiment, the first substrate 100 has a first doped ion, wherein the doped ion includes N-type ions or P-type ions. The N-type ion includes P ions, As ions, or Sb ions; the P-type ion includes B ions, Ga ions, or In ions. As an example, the first doped ion is a P-type ion.

[0026] It should be noted that the resistivity of the first substrate 100 should not be too high. If the resistivity of the first substrate 100 is too high, its conductivity will be poor and its resistance will be high. In the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the high resistance of the first substrate 100 will easily affect the test results of the semiconductor structure, causing a large test error. Therefore, in this embodiment, the resistivity of the first substrate 100 is less than or equal to 20 Ω*cm. A resistivity of less than or equal to 20 Ω*cm indicates that the resistivity of the first substrate 100 is small. Therefore, in the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the resistance of the first substrate 100 is small and has almost no effect on the resistance of the test path. Thus, the resistance of the test path can be considered to be the resistance of the second substrate 110.

[0027] The second substrate 110 provides the basis for the process operation of forming the semiconductor structure. As an example, the material of the second substrate 110 is silicon.

[0028] In optical devices, a photoelectric element is formed in the second substrate 110. Therefore, the second substrate 110 has a second doped ion. The first substrate serves as a film layer suitable for forming the photoelectric element, which is beneficial for the formation of the photoelectric element.

[0029] In this embodiment, the first doped ion and the second doped ion have the same conductivity type to achieve normal function in the optical device, and to avoid the formation of a PN junction between the second substrate 110 and the first substrate 100 due to the different conductivity types of the doped ions, which would affect the normal function in the optical device and the test results in the semiconductor structure.

[0030] Correspondingly, the second doped ion is a p-type ion.

[0031] In this embodiment, the concentration of the second doped ion is less than the concentration of the first doped ion. As a result, in the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the resistance of the second substrate 110 is greater than the resistance of the first substrate 100. Therefore, the resistance of the test path obtained is closer to the resistance of the second substrate 110, which is beneficial to obtaining more accurate test results.

[0032] It should be noted that the resistivity of the second substrate 110 should not be too low. If the resistivity of the second substrate 110 is too low, it indicates that the concentration of the second doped ions in the second substrate 110 is too high, the breakdown effect caused by thermal motion in the second substrate 110 is enhanced, resulting in an increase in dark count, which affects the performance of the optoelectronic element in the optical device. Therefore, in this embodiment, the resistivity of the second substrate 110 is greater than or equal to 100 Ω*cm. The resistivity of the second substrate 110 is greater than or equal to 100 Ω*cm, indicating that the resistivity of the second substrate 110 is relatively large. Therefore, in the test path formed by the second substrate 110 in the first device region 100a, the first substrate 100, and the second substrate 110 in the second device region 100b, the resistance of the second substrate 110 is relatively large. Thus, the other structures have almost no effect on the resistance of the test path compared to the second substrate 110. It can be considered that the resistance of the test path is the resistance of the second substrate 110.

[0033] In this embodiment, the first substrate 100 and the second substrate 110 constitute a frontside illumination (BSI) pixel wafer. In the optical device, the exposed surface of the second substrate 110 is the light-receiving surface of the optical device. The second substrate 110 also contains device structures such as optoelectronic elements (e.g., photodiodes).

[0034] The deep trench isolation structure 200 penetrates the second substrates 110 on both sides of the first device region 100a and the second device region 100b respectively, and is used to isolate adjacent second substrates 110. In optical devices, it is also used to isolate optoelectronic components in adjacent second substrates 110. The deep trench isolation structure 200 also extends into the first substrate 100, which is beneficial to achieve complete isolation of the second substrates of the first device region 100a and the second device region 100b, so that the second substrate 110 of the first device region 100a and the second substrate 110 of the first device region 100b form a series circuit.

[0035] The first device region 100a and the second device region 100b share the same deep trench isolation structure 200 at their junction, which helps to save wafer area and reduce structural costs.

[0036] In this embodiment, the material of the deep trench isolation structure 200 includes silicon oxide.

[0037] Silicon oxide is an insulating material that can achieve good insulation.

[0038] In other embodiments, the material of the deep trench isolation structure may also be a high-K material, wherein the high-K material is a material with a K value greater than or equal to 7, such as hafnium oxide or aluminum oxide.

[0039] In the semiconductor field, an optical device has a pixel area of ​​a certain size for receiving optical signals. The pixel area typically includes multiple sub-pixel areas arranged in an array. Device structures such as optoelectronic elements are formed within these sub-pixel areas, and an isolation structure is formed between adjacent sub-pixel areas for electrical and optical isolation. As described above, in this embodiment, the first device area 100a and the second device area 100b are both equivalent to sub-pixel areas in the optical device. The deep trench isolation structure 200 is used to achieve electrical and optical isolation between adjacent first device areas 100a and second device areas 100b, thereby giving the optical device the same structure as the test body 10.

[0040] It should be noted that during the fabrication of optical devices, due to factors such as plasma charging required by the process and atomic-level defects at the heterogeneous interface during material deposition, the interface of the deep trench isolation structure 200 near the second substrate 110 will carry stable positive or negative charges. Typically, when the filling material of the deep trench isolation structure 200 is silicon oxide, the sidewalls of the deep trench isolation structure 200 carry positive charges, and when the filling material of the deep trench isolation structure 200 is a high-k material, the sidewalls of the deep trench isolation structure 200 carry negative charges. When the majority carriers of doped ions in the second substrate 110 have the same charge as the sidewall of the deep trench isolation structure 200, the majority carriers on the sidewall 100a of the second substrate 110 are repelled due to the principle of like charges repelling each other. Consequently, the minority carriers with opposite charges are drawn out to the sidewall 100a of the second substrate 110. As a result, concentrated inversion charges are easily generated at the position where the second substrate 110 contacts the deep trench isolation structure 200. The inversion layer formed by the concentrated inversion charges will affect the electrical properties of the optical device. Therefore, it is necessary to obtain the distribution of inversion charges in the second substrate 110 through testing to provide a reference for subsequent formulation of device design rules and adjustment of manufacturing process.

[0041] In this embodiment, the second doped ion in the second substrate 110 is a P-type doped ion, whose majority carrier is a hole, correspondingly a positive charge. The filling material of the deep trench isolation structure 200 is silicon oxide, and the sidewalls of the deep trench isolation structure 200 are positively charged. Therefore, the majority carriers on the sidewall 100a of the second substrate 110 are repelled, resulting in the opposite charge minority carriers being drawn out to the sidewall 100a of the second substrate 110. That is, N-type ions are distributed at the sidewall 100a of the second substrate 110, forming an inversion layer (e.g., ...). Figure 3 (As shown by the dashed line).

[0042] It should be noted that the second concentration of the second doped ions in the second substrate 110 is relatively small. Therefore, the influence of the inversion ions adsorbed at the sidewall 100a of the second substrate 110 is more significant. The inversion layer at the sidewall 100a of the second substrate 110 has a significant impact on the resistance of the second substrate 110. The inversion layer will compress the cross-sectional area of ​​the vertical electrical path of the second substrate 110 in the semiconductor structure, thereby increasing the resistance of the second substrate 110. This can even occur when the thickness of the inversion layer is too large compared to the width of the second substrate 110 along the second direction. This will cause a pinch-off phenomenon in the test path. However, the concentration of the first doped ions in the first substrate 100 is relatively large. The inversion layer will hardly be generated at the contact surface between the first substrate 100 and the deep trench isolation structure 200. The resistance of the first substrate 100 is still relatively small. Therefore, in the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the resistance of the first substrate 100 can be ignored. The resistance obtained by testing the semiconductor structure is similar to that of the second substrate 110.

[0043] In this embodiment, in the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the actual resistance of the second substrate 110 is obtained by testing the semiconductor structure, thereby obtaining the thickness and ion concentration of the inversion layer at the sidewall 100a position of the second substrate 110, which serves as a reference for subsequent formulation of device design rules and adjustment of manufacturing process.

[0044] In this embodiment, the distance between adjacent deep trench isolation structures 200 in the first device area 100a is the first spacing d1, and the distance between adjacent deep trench isolation structures 200 in the second device area 100b is the second spacing d2. Both the first spacing d1 and the second spacing d2 are less than or equal to a preset spacing, and the first spacing d1 and the second spacing d2 are equal.

[0045] If the distance between adjacent deep trench isolation structures 200 is too large, the corresponding dimension of the second substrate 110 located between the adjacent deep trench isolation structures 200 along the second direction will be large. Therefore, at the sidewall 100a position of the second substrate 110, the thickness of the inversion layer is smaller than the width dimension of the second substrate 110 along the second direction. Consequently, the inversion layer has a small, or even negligible, effect on the resistance of the second substrate 110. Thus, in the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the test results obtained are insufficient to characterize the effect of the inversion layer on the resistance of the second substrate 110, making it difficult to obtain the thickness and ion concentration of the inversion layer at the sidewall 100a position of the second substrate 110. Therefore, in this embodiment, both the first spacing d1 and the second spacing d2 are less than or equal to a preset spacing.

[0046] It should be noted that the preset spacing should not be too large or too small. If the preset spacing is too large, even if the first spacing d1 and the second spacing d2 are both less than or equal to the preset spacing, it is still easy for the first spacing d1 and the second spacing d2 to be too large. This makes it difficult to characterize the effect of the inversion layer on the resistance of the second substrate 110 in the test results, and thus difficult to obtain the thickness and ion concentration of the inversion layer at the sidewall 100a position of the second substrate 110, thereby affecting the test effect of the semiconductor structure. If the preset spacing is too small, the requirements for the first spacing d1 and the second spacing d2 are too stringent, and the process requirements for forming the semiconductor structure are too high. This can easily lead to unnecessary process problems. For example, if the first spacing d1 and the second spacing d2 are too small during the formation of the semiconductor structure, the width of the photoresist used to pattern the second substrate 110 to form the deep trench isolation structure 200 along the second direction will be too small, which can easily lead to the problem of photoresist tipping over and affect the formation of the semiconductor structure. Therefore, in this embodiment, the spacing is set to be 10μm to 30μm.

[0047] In this embodiment, both the first spacing d1 and the second spacing d2 are less than or equal to a preset spacing. The test results of the semiconductor structure characterize the influence of the inversion layer on the electrical properties of the second substrate 110 of the first device region 100a and the second device region 100b. That is, in the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the resistance obtained by the test is the sum of the resistances of the second substrate 110 of the first device region 100a and the second substrate 110 of the second device region 100b. If the first spacing d1 and the second spacing d2 are not equal, it is difficult to accurately obtain the resistances of the second substrate 110 of the first device region 100a and the second substrate 110 of the second device region 100b respectively. Therefore, in this embodiment, the first spacing d1 and the second spacing d2 are equal, so that the resistance of the second substrate 110 in the first device region 100a and the resistance of the second substrate 110 in the second device region 100b are both half of the resistance obtained by the test. This is beneficial to obtain the thickness of the inversion layer and the ion concentration at the sidewall 100a position of the second substrate 110 more accurately based on the test results.

[0048] In other embodiments, either the first spacing or the second spacing may be less than or equal to a preset spacing, and the other may be greater than the preset spacing. Correspondingly, the resistance of the second substrate less than or equal to the preset spacing is larger, and the resistance of the second substrate greater than the preset spacing is smaller. Thus, in the test path formed by the second substrate of the first device region and the second substrate of the first and second device regions, the resistance of the second substrate greater than the preset spacing has almost no effect on the electrical properties of the test path. The resistance obtained by the test can be considered to characterize the resistance of the second substrate less than or equal to the preset spacing, and the thickness and ion concentration of the inversion layer at the sidewall position of the second substrate less than or equal to the preset spacing can be obtained more accurately based on the test results.

[0049] In this embodiment, the first substrate 100 includes multiple sets of adjacent first device regions 100a and second device regions 100b. The adjacent first device regions 100a and second device regions 100b constitute a test unit region. The semiconductor structure includes multiple spaced test unit regions. In each test unit region, the distance between adjacent deep trench structures 200 that is less than or equal to a preset distance is the test distance. The test distances in the multiple test unit regions are not equal.

[0050] In multiple test unit areas, the test spacing is not equal. By testing multiple sets of test unit areas with different test spacings, the test spacing when the test path formed by the second substrate 110 of the first device area 100a, the first substrate 100, and the second substrate 110 of the second device area 100b is interrupted is obtained. Since the test path is interrupted, half of the test spacing can be considered as the thickness of the inversion layer. This allows for a more intuitive and convenient way to obtain the thickness of the inversion layer. Directly characterizing the influence of the inversion layer through electrical signals helps to avoid conversion errors caused by converting other signals into electrical signals. This facilitates efficient and accurate acquisition of the thickness of the inversion layer and ion concentration based on the test results.

[0051] The signal loading unit 20 is used to load test signals onto the second substrates 110 of the first device region 100a and the second device region 100b, respectively. The first interconnect structure 301 is used to load a first test signal onto the second substrate 110 of the first device region 100a, and the second interconnect structure 300 is used to load a second test signal onto the second substrate 110 of the second device region 100b, thereby forming a test path connected in series with the first interconnect structure 301, the second substrate 110 of the first device region 100a, the first substrate 100, the second substrate 110 of the second device region 100b, and the second interconnect structure 300.

[0052] In the semiconductor structure provided by this invention, test signals are applied to the second substrates 110 of the first device region 100a and the second device region 100b respectively through the first interconnect structure 301 and the second interconnect structure 300. This forms a test path consisting of the first interconnect structure 301, the second substrate 110 of the first device region 100a, the first substrate 100, the second substrate 110 of the second device region 100b, and the second interconnect structure 300. The test path is then tested to obtain electrical signals, characterizing the distribution of doped ions in the second substrate 110. Compared to semiconductor structures tested by setting probes on the cross-section of the semiconductor structure, this invention avoids the need to expose the cross-section of the semiconductor structure, thus preventing damage. It also avoids sample preparation errors caused by cutting the semiconductor structure to obtain the cross-section, and avoids cost waste due to damage to the semiconductor structure. Furthermore, compared to the method of testing semiconductor structures by setting probes, which has higher requirements for probe setup, greater influence of probe signals on test results, and larger human error, this invention effectively avoids large test errors caused by repeated use of probes, thereby improving the testing accuracy of the semiconductor structure.

[0053] The first interconnect structure 301 is used as a first test signal loading terminal, and the second interconnect structure 300 is used as a second test signal loading terminal. The first test signal loading terminal and the second test signal loading terminal are used to load corresponding test signals, so that the first substrate, the second substrate of the first device region, the second substrate of the second device region, the first interconnect structure and the second interconnect structure constitute a test path.

[0054] In this embodiment, either the first test signal loading terminal or the second test signal loading terminal is used to load a positive potential, and the other is used to load a zero potential. Thus, the first test signal and the second test signal form a voltage difference, which enables the test path of the first interconnect structure 301, the second substrate 110 of the first device region 100a, the first substrate 100, the second substrate 110 of the second device region 100b, and the second interconnect structure 300 connected in series to be turned on.

[0055] In this embodiment, the first interconnect structure 301 includes: a first conductive plug 312 located on top of the second substrate 110 of the first device region 100a; one or more first interconnect lines 321 spaced apart in the longitudinal direction, located on top of the first conductive plug 312 and electrically connected to the first conductive plug 312, and when the number of layers of the first interconnect lines 321 is multiple, the interconnect lines of adjacent layers of first interconnect lines 321 are connected by a first interconnect via structure 311, and the first interconnect line 321 at the top layer of the first interconnect structure 301 is used as the first test signal loading terminal.

[0056] The second interconnect structure 300 includes: a second conductive plug 313 located on top of the second substrate 110 of the second device region 100b; one or more second interconnect lines 320 spaced apart in the longitudinal direction, located on top of the second conductive plug 313 and electrically connected to the second conductive plug 313, and when the number of layers of the second interconnect lines 320 is multiple, the interconnect lines of adjacent layers of second interconnect lines 320 are connected by a second interconnect via structure 310, and the second interconnect line 320 at the top layer of the second interconnect structure 300 is used as a second test signal loading terminal.

[0057] In this embodiment, taking the first interconnect structure 301 including multiple layers of first interconnect lines 321 spaced apart in the longitudinal direction and the second interconnect structure 300 including multiple layers of second interconnect lines 320 spaced apart in the longitudinal direction as an example, for example: when the first interconnect structure 301 includes two layers of first interconnect lines 321 and the second interconnect structure 300 includes two layers of second interconnect lines 320, the first interconnect lines 321 and the second interconnect lines 320 used for loading test signals are both corresponding to second interlayer metal lines (i.e., M2 layer).

[0058] The first conductive plug 312 is used to electrically bring out the second substrate 110 of the first device region 100a, the first interconnect via structure 311 and the first interconnect line 321 are used to realize electrical connection, and the topmost first interconnect line 321 is used to load a first test signal; the second conductive plug 313 is used to electrically bring out the second substrate 110 of the second device region 100b, the second via interconnect structure 310 and the second interconnect line 320 are used to realize electrical connection, and the topmost second interconnect line 320 is used to load a second test signal.

[0059] In other embodiments, depending on actual process requirements, the first interconnect structure may include a first interconnect layer, and the second interconnect structure may include a second interconnect layer. The first and second interconnects used for loading test signals are both first interlayer metal lines (i.e., M1 layer).

[0060] In this embodiment, both the first interconnect structure 301 and the second interconnect structure 300 are back-end interconnect structures. This embodiment utilizes a conventional back-end interconnect structure to load test signals onto the second substrate 110 of the first device region 100a and the second device region 100b, which is beneficial for improving the process compatibility of forming the semiconductor structure. Furthermore, by using a first via interconnect structure 311 and a first interconnect line 321 to form the first interconnect structure 301, and a second via interconnect structure 310 and a second interconnect line 320 to form the second interconnect structure 300, the resistance of the first interconnect structure 301 and the second interconnect structure 300 is relatively small. This allows the resistance of the test path formed by the first interconnect structure 301, the second substrate 110 of the first device region 100a, the first substrate 100, the second substrate 110 of the second device region 100b, and the second interconnect structure 300 to be used as the resistance of the second substrate 110.

[0061] In this embodiment, both the first interconnect structure 301 and the second interconnect structure 300 are made of conductive materials. Specifically, the materials of the first interconnect structure 301 and the second interconnect structure 300 include one or more of copper or aluminum, which have good conductivity and low resistance.

[0062] In this embodiment, the semiconductor structure further includes: a dielectric layer 200 covering the top of the second substrate 110 and the deep trench isolation structure 200; the first interconnect structure 301 and the second interconnect structure 300 are located in the dielectric layer 200; and the dielectric layer 200 exposes the top of the first interconnect 321 and the second interconnect 320.

[0063] The dielectric layer 200 is used to electrically isolate the first interconnect structure 301 and the second interconnect structure 300.

[0064] The dielectric layer 200 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the dielectric layer 200 is made of silicon oxide.

[0065] In this embodiment, the semiconductor structure further includes a doped layer 120 located on top of the second substrate 110, wherein the doped layer 120 has a third doped ion of a third concentration, wherein the third doped ion has the same conductivity type as the second doped ion, and the third concentration is greater than the second concentration.

[0066] Correspondingly, the first interconnect structure 301 and the second interconnect structure 300 are located on top of the doped layer 120, forming a test path in series of the first interconnect structure 301, the second substrate 110 of the first device region 100a, the first substrate 100, the second substrate 110 of the second device region 100b, the second interconnect structure 300, and the doped layer 120.

[0067] In this embodiment, the third doped ion has the same conductivity type as the second doped ion, so as to achieve normal function in the optical device and avoid the formation of a PN junction between the second substrate 110 and the doped layer 120 due to the different conductivity types of the doped ions, which would affect the normal function in the optical device and the test results in the semiconductor structure.

[0068] Correspondingly, the third dopant ion is a p-type ion.

[0069] In this embodiment, the concentration of the third doped ion is greater than the concentration of the second doped ion. As a result, in the test path formed by the first interconnect structure 301, the second substrate 110 of the first device region 100a, the first substrate 100, the second substrate 110 of the second device region 100b, the second interconnect structure 300, and the doped layer 120, the resistance of the second substrate 110 is greater than the resistance of the doped layer 120. Therefore, the resistance of the obtained test path is closer to the resistance of the second substrate 110, which is beneficial to obtaining more accurate test results.

[0070] It should be noted that the concentration of the third dopant ion should not be too low. If the concentration of the third dopant ion is too low, the conductivity of the doped layer 120 will be poor, and the resistance will be high. In the test path formed by the first interconnect structure 301, the second substrate 110 of the first device region 100a, the first substrate 100, the second substrate 110 of the second device region 100b, the second interconnect structure 300, and the doped layer 120, the resistance of the doped layer 120 will be high, and the contact resistance between the doped layer 120 and the first interconnect structure 301, as well as between the doped layer 120 and the second interconnect structure 300, will also be high. This can easily affect the test results of the semiconductor structure and cause a large test error. Therefore, in this embodiment, the concentration of the third dopant ion is greater than 1E15 atoms / cm³. 2 Among them, atoms / cm 2 This is a unit of ion concentration for ion implantation per unit area.

[0071] The concentration of the third doped ion is greater than 1E15 atoms / cm². 2 If the concentration of the third doped ion is relatively high, in the test path consisting of the first interconnect structure 301, the second substrate 110 of the first device region 100a, the first substrate 100, the second substrate 110 of the second device region 100b, the second interconnect structure 300, and the doped layer 120 connected in series, the resistance of the doped layer 120 is relatively low, and its impact on the resistance of the test path is relatively small.

[0072] It should be noted that in this embodiment, along the normal direction of the surface of the first substrate 100 (e.g., Figure 3As shown in the Z-direction, the depth of the doped layer 120 should not be too large or too small. If the depth of the doped layer 120 is too large, the resistance of the doped layer 120 will easily become too large, which will easily affect the test results of the semiconductor structure and cause a large test error. In order to ensure good contact between the first interconnect structure 301 and the second interconnect structure 300 and the doped layer 120, the first interconnect structure 301 and the second interconnect structure 300 will extend into the doped layer 120 of a certain thickness. That is, the bottom surface of the first interconnect structure 301 and the second interconnect structure 300 is lower than the top surface of the doped layer 120. Therefore, if the depth of the doped layer 120 is too small, the first interconnect structure 301 and the second interconnect structure 300 will easily come into contact with the second substrate 110, which will result in a large contact resistance between the first interconnect structure 301 and the second interconnect structure 300 and the doped layer 120, which will easily affect the test results of the semiconductor structure and cause a large test error. Therefore, in this embodiment, the depth of the doped layer 120 along the normal direction of the surface of the first substrate 100 is to

[0073] The depth of doped layer 120 is to Since the depth of the doped layer 120 is relatively small, in the test path formed by the first interconnect structure 301, the second substrate 110 of the first device region 100a, the first substrate 100, the second substrate 110 of the second device region 100b, the second interconnect structure 300, and the doped layer 120 connected in series, the resistance of the doped layer 120 is relatively small, and its impact on the resistance of the test path is relatively small.

[0074] In order to isolate the doped layers 120 of the first device region 100a and the second device region 100b, and to connect the doped layers 120 of the first device region 100a and the second device region 100b in series, the deep trench isolation structure 200 also penetrates the doped layers 120.

[0075] In this embodiment, the semiconductor structure is disposed on a wafer, which includes dicing channels. The semiconductor structure is located in the dicing channels, thereby enabling the simultaneous formation of the semiconductor structure on the wafer and the fabrication of the device product. This simplifies the process flow, improves process efficiency, and saves process costs. It also enables online testing, saving testing time and further reducing process costs. Moreover, it helps ensure the consistency between the semiconductor structure and the device product. Furthermore, since the semiconductor structure is located in the dicing channels, it can be removed by cutting through the dicing channels after testing, thus directly obtaining the device product on the wafer.

[0076] Accordingly, the present invention also provides a testing method. Figure 4 This is a flowchart of an embodiment of the testing method of the present invention.

[0077] In this embodiment, the testing method includes the following basic steps:

[0078] Step S1: Provide the semiconductor structure of the aforementioned embodiments of the invention.

[0079] Step S2: Apply test signals to the first test signal loading terminal and the second test signal loading terminal to enable the first substrate, the second substrate of the first device region, the second substrate of the second device region, the first interconnect structure and the second interconnect structure to form a test path.

[0080] Step S3: Obtain the resistance of the test path.

[0081] Step S4: Based on the resistance, obtain the corresponding inversion layer thickness of the second substrate sidewall.

[0082] In the testing method provided by this invention, test signals are applied to the second substrates of the first and second device regions, respectively, through a first interconnect structure and a second interconnect structure. This forms a test path comprised of the first interconnect structure, the second substrate of the first device region, the first substrate, the second substrate of the second device region, and the second interconnect structure. The test path is then tested to obtain its electrical signal, characterizing the distribution of doped ions in the second substrate. Compared to testing semiconductor structures by setting probes on the cross-section of the semiconductor structure, this invention avoids the need to expose the cross-section of the semiconductor structure, thus preventing damage. It also avoids sample preparation errors caused by cutting the semiconductor structure to obtain the cross-section, and avoids cost waste due to damage to the semiconductor structure. Furthermore, compared to the method of testing semiconductor structures by setting probes, which has higher requirements for probe setup, a greater impact of probe signals on test results, and larger human error, this invention effectively avoids large test errors caused by repeated use of probes, thereby improving the testing accuracy of semiconductor structures.

[0083] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the following description is provided in conjunction with the accompanying drawings. Figure 3 Specific embodiments of the present invention will be described in detail below.

[0084] refer to Figure 3 Step S1: Provide the semiconductor structure of the aforementioned embodiment of the invention.

[0085] For a detailed description of the foregoing embodiments of the invention, please refer to the description of the semiconductor structure, which will not be repeated here.

[0086] Execution step S2: Load test signals onto the first test signal loading terminal and the second test signal loading terminal to enable the first substrate 100, the second substrate 110 of the first device region 100a, the second substrate 110 of the second device region 110b, the first interconnect structure 301 and the second interconnect structure 300 to form a test path.

[0087] In this embodiment, in the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the actual resistance of the second substrate 110 is obtained by testing the semiconductor structure, thereby obtaining the thickness and ion concentration of the inversion layer at the sidewall 100a position of the second substrate 110, which serves as a reference for subsequent formulation of device design rules and adjustment of manufacturing process.

[0088] In this embodiment, the absolute value of the voltage difference between the test signals applied to the first test signal loading terminal and the second test signal loading terminal should not be too large. If the absolute value of the voltage difference between the first test signal loading terminal and the second test signal loading terminal is too large, it will have a significant impact on the depletion region of the PN junction between the second substrate 110 and the inversion layer, thereby affecting the charge adsorption of the inversion layer and consequently affecting the test results. Therefore, in this embodiment, the voltage difference between the test signals applied to the first test signal loading terminal and the second test signal loading terminal is less than or equal to 0.1V.

[0089] Specifically, when the doped ions of the second substrate 110 are N-type, either the first test signal loading terminal or the second test signal loading terminal is used to load a positive potential, and the other is used to load a zero potential; when the doped ions of the second substrate 110 are P-type, either the first test signal loading terminal or the second test signal loading terminal is used to load a negative potential, and the other is used to load a zero potential.

[0090] Perform step S3: Obtain the resistance of the test path.

[0091] The resistance of the test path is obtained to characterize the distribution of the inversion layer of the second substrate 110.

[0092] In this embodiment, the distance between adjacent deep trench isolation structures 200 in the first device area 100a is the first spacing d1, and the distance between adjacent deep trench isolation structures 200 in the second device area 100b is the second spacing d2. Both the first spacing d1 and the second spacing d2 are less than or equal to a preset spacing, and the first spacing d1 and the second spacing d2 are equal.

[0093] If the distance between adjacent deep trench isolation structures 200 is too large, the corresponding dimension of the second substrate 110 located between the adjacent deep trench isolation structures 200 along the second direction will be large. Therefore, at the sidewall 100a position of the second substrate 110, the thickness of the inversion layer is smaller than the width dimension of the second substrate 110 along the second direction. Consequently, the inversion layer has a small, or even negligible, effect on the resistance of the second substrate 110. Thus, in the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the test results obtained are insufficient to characterize the effect of the inversion layer on the resistance of the second substrate 110, making it difficult to obtain the thickness and ion concentration of the inversion layer at the sidewall 100a position of the second substrate 110. Therefore, in this embodiment, both the first spacing d1 and the second spacing d2 are less than or equal to a preset spacing.

[0094] It should be noted that the preset spacing should not be too large or too small. If the preset spacing is too large, the condition that both the first spacing d1 and the second spacing d2 are less than or equal to the preset spacing will be met when they are large. This can easily lead to the test results being unable to characterize the effect of the inversion layer on the resistance of the second substrate 110, making it difficult to obtain the thickness and ion concentration of the inversion layer at the sidewall 100a position of the second substrate 110, thus affecting the test results of the semiconductor structure. If the preset spacing is too small, the requirements for the first spacing d1 and the second spacing d2 are too stringent, and the process requirements for forming the semiconductor structure are too high, which can easily lead to unnecessary process problems. For example, if the first spacing d1 and the second spacing d2 are too small during the formation of the semiconductor structure, the width of the photoresist used to pattern the second substrate 110 to form the deep trench isolation structure 200 along the second direction will be too small when forming the deep trench. This can easily lead to the problem of photoresist tipping over, affecting the formation of the semiconductor structure. Therefore, in this embodiment, the spacing is set to 10μm to 30μm.

[0095] In this embodiment, both the first spacing d1 and the second spacing d2 are less than or equal to a preset spacing. The test results of the semiconductor structure characterize the influence of the inversion layer on the electrical properties of the second substrate 110 of the first device region 100a and the second device region 100b. That is, in the test path formed by the second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b, the resistance obtained by the test is the sum of the resistances of the second substrate 110 of the first device region 100a and the second substrate 110 of the second device region 100b. If the first spacing d1 and the second spacing d2 are not equal, it is difficult to accurately obtain the resistances of the second substrate 110 of the first device region 100a and the second substrate 110 of the second device region 100b respectively. Therefore, in this embodiment, the first spacing d1 and the second spacing d2 are equal, so that the resistance of the second substrate 110 in the first device region 100a and the resistance of the second substrate 110 in the second device region 100b are both half of the resistance obtained by the test. This is beneficial to obtain the thickness of the inversion layer and the ion concentration at the sidewall 100a position of the second substrate 110 more accurately based on the test results.

[0096] Alternatively, in other embodiments, either the first spacing or the second spacing is less than or equal to a preset spacing, and the other is greater than the preset spacing. Correspondingly, the resistance of the second substrate less than or equal to the preset spacing is larger, and the resistance of the second substrate greater than the preset spacing is smaller. Thus, in the test path formed by the second substrate of the first device region and the second substrate of the first and second device regions, the resistance of the second substrate greater than the preset spacing has almost no effect on the electrical properties of the test path. The resistance obtained by the test can be considered to characterize the resistance of the second substrate less than or equal to the preset spacing, and the thickness and ion concentration of the inversion layer at the sidewall position of the second substrate less than or equal to the preset spacing can be obtained more accurately based on the test results.

[0097] Among the adjacent first device area 100a and second device area 100b, the test spacing is the one that is less than or equal to the preset spacing between the first spacing d1 and the second spacing d2.

[0098] In this embodiment, the first substrate 100 includes multiple sets of first device regions 100a and second device regions 100b. Adjacent first device regions 100a and second device regions 100b constitute a test unit region. The semiconductor structure includes multiple phase-spaced test unit regions, and the test spacing in the multiple test unit regions is not equal.

[0099] In multiple test unit areas, the test spacing is not equal. Therefore, by testing multiple sets of first device area 100a and second device area 200b with different test spacing, the test spacing when the test path formed by the second substrate 110 of the first device area 100a and the second substrate 110 of the second device area 100b is interrupted is obtained. Since the test path is interrupted, half of the test spacing can be considered as the thickness of the inversion layer. This allows for a more intuitive and convenient way to obtain the thickness of the inversion layer. Directly characterizing the influence of the inversion layer through electrical signals helps to avoid conversion errors caused by converting other signals into electrical signals. This facilitates efficient and accurate acquisition of the thickness of the inversion layer and ion concentration based on the test results.

[0100] Execute step S4: Based on the resistance, obtain the corresponding inversion layer thickness of the second substrate 110 sidewall.

[0101] In this embodiment, the equivalent width of the test path is obtained based on the resistance, and half of the difference between the test spacing and the equivalent width is taken as the inversion layer thickness.

[0102] The test spacing is the actual width of the second substrate 110 in the test path. The difference between the actual width and the equivalent width is the sum of the inversion layer thicknesses on both sides of the second substrate 110. In other words, the inversion layer thickness is half of the difference between the test spacing and the equivalent width.

[0103] In this embodiment, for multiple adjacent first device regions 100a and second device regions 100b, the largest test spacing among one or more test unit regions with a resistance greater than or equal to a preset resistance is taken as the target spacing, and half of the target spacing is taken as the inversion layer thickness.

[0104] If the resistance is greater than or equal to the preset resistance, that is, the test path is pinched off by the inversion layer. Therefore, by taking the largest test spacing among the pinched test spacings as the target spacing, the target spacing closest to the inversion layer pinching off the second substrate 110 can be obtained more accurately, thereby obtaining the thickness of the inversion layer more intuitively and accurately.

[0105] In this embodiment, the step of obtaining the equivalent width of the test path based on the resistance includes: obtaining the geometric area of ​​the current path according to the expression: resistance = resistivity × geometric length of the current path parallel to the current density direction ÷ geometric area of ​​the current path perpendicular to the current density direction, wherein the resistivity is the resistivity of the second substrate, when both the first spacing d1 and the second spacing d2 are less than or equal to a preset spacing, the geometric length of the current path is twice the thickness of the second substrate 110, when either the first spacing d1 or the second spacing d2 is less than or equal to the preset spacing and the other is greater than the preset spacing, the geometric length of the current path is the thickness of the second substrate 110, and the geometric area of ​​the current path is the equivalent area of ​​the test path; and obtaining the equivalent width of the test path based on the equivalent area.

[0106] The second substrate 110 of the first device region 100a, the first substrate 100, and the second substrate 110 of the second device region 100b form a series test path. The current passes perpendicularly through the second substrate 110. The geometric length of the current path is the thickness of the second substrate 110, and the geometric area of ​​the current path is the area through which the actual current flows in the cross-section of the second substrate 110 along the second direction.

[0107] The geometric area of ​​the current path is obtained using the expression: resistance = resistivity × geometric length of the current path parallel to the current density direction ÷ geometric area of ​​the current path perpendicular to the current density direction. This is the area through which the actual current flows in the cross-section of the second substrate 110 along the second direction. The inversion layer is located on both sides of the second substrate 110 along the second direction. Therefore, the size of the second substrate 110 minus the size of the inversion layer along the second direction is the size of the first substrate along the second direction in the area through which the actual current flows in the cross-section of the second substrate 110 along the second direction. This size of the first substrate along the second direction is the equivalent width of the test path.

[0108] In this embodiment, in the steps of obtaining the equivalent width of the test path based on the resistance and obtaining the corresponding inversion layer thickness of the sidewall 110a of the second substrate 110, after obtaining the resistance of the test path, the resistance of the test path and the size effect of the deep trench isolation structure 200 can be corrected by combining T-CAD simulation methods and online data test results, so as to obtain a more accurate equivalent width and average thickness of adsorbed charge, which is the inversion layer thickness. The ion concentration of the inversion layer can also be obtained from the average thickness of adsorbed charge, which can be used as a reference for subsequent formulation of device design rules and adjustment of manufacturing process.

[0109] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The test body includes a first substrate, a second substrate, and a deep trench isolation structure, wherein the first substrate includes an adjacent first device region and a second device region, and the first substrate has a first doped ion; The second substrate is located on the first substrate of the first device region and the second device region. The second substrate has a second doped ion, wherein the first doped ion and the second doped ion have the same conductivity type, and the concentration of the second doped ion is less than the concentration of the first doped ion. The deep trench isolation structure penetrates the second substrate on both sides of the first device region and the second device region respectively, and extends into the first substrate. The first device region and the second device region share the same deep trench isolation structure at the junction. The signal loading section includes a first interconnect structure and a second interconnect structure. The first interconnect structure is located on top of the second substrate of the first device region and is electrically connected to the second substrate. The first interconnect structure is used as a first test signal loading terminal. The second interconnect structure is located on top of the second substrate in the second device region and is electrically connected to the second substrate. The second interconnect structure is used as a second test signal loading terminal.

2. The semiconductor structure as described in claim 1, characterized in that, The first device region and the second device region extend along a first direction and are arranged adjacent to each other along a second direction, wherein the first direction and the second direction are perpendicular to each other; or, The first device region surrounds the second device region.

3. The semiconductor structure as described in claim 1, characterized in that, The distance between adjacent deep trench isolation structures in the first device area is the first spacing, and the distance between adjacent deep trench isolation structures in the second device area is the second spacing. Both the first spacing and the second spacing are less than or equal to a preset spacing, and the first spacing and the second spacing are equal. or, Either the first spacing or the second spacing is less than or equal to the preset spacing, and the other is greater than the preset spacing.

4. The semiconductor structure as described in claim 3, characterized in that, The first substrate includes multiple sets of first device regions and second device regions. Adjacent first device regions and second device regions constitute test unit regions. The semiconductor structure includes multiple spaced-apart test unit regions. In each test unit region, the distance between adjacent deep trench structures that is less than or equal to the preset distance is the test distance. The test distances in the multiple test unit regions are not equal.

5. The semiconductor structure as described in claim 3, characterized in that, The preset spacing is 10μm to 30μm.

6. The semiconductor structure as described in claim 1, characterized in that, Either the first test signal loading terminal or the second test signal loading terminal is used to load a positive or negative potential, and the other is used to load a zero potential.

7. The semiconductor structure as described in claim 1, characterized in that, The first interconnect structure includes: a first conductive plug located on top of a second substrate in the first device region; one or more first interconnect lines spaced apart in the longitudinal direction located on top of the first conductive plug and electrically connected to the first conductive plug, and when the number of layers of the first interconnect lines is multiple, adjacent layers of first interconnect lines are connected through a first interconnect via structure, and the topmost first interconnect line in the first interconnect structure is used as a first test signal loading terminal. The second interconnect structure includes: a second conductive plug located on top of a second substrate in the second device region; one or more second interconnect lines spaced apart in the longitudinal direction, located on top of the second conductive plug and electrically connected to the second conductive plug, and when the number of layers of the second interconnect lines is multiple, adjacent layers of second interconnect lines are connected through a second interconnect via structure, and the topmost second interconnect line in the second interconnect structure is used as a second test signal loading terminal.

8. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a doped layer located on top of the second substrate, wherein the doped layer has a third doped ion, wherein the third doped ion has the same conductivity type as the second doped ion, and the concentration of the third doped ion is greater than the concentration of the second doped ion; The first interconnect structure and the second interconnect structure are located on top of the doped layer; The deep trench isolation structure also extends through the doped layer.

9. The semiconductor structure as described in claim 8, characterized in that, The depth of the doped layer along the normal direction of the first substrate surface is . to 10. The semiconductor structure as described in claim 8, characterized in that, The concentration of the third doped ion is greater than 1E15 atoms / cm². 2 .

11. The semiconductor structure as claimed in claim 1, characterized in that, The material of the first substrate includes silicon; the material of the second substrate includes silicon.

12. The semiconductor structure as claimed in claim 1, characterized in that, The deep trench isolation structure is made of silicon oxide or high-K material, wherein the high-K material is a material with a K value greater than or equal to 7.

13. The semiconductor structure as claimed in claim 1, characterized in that, The resistivity of the first substrate is less than or equal to 20 Ω*cm.

14. The semiconductor structure as claimed in claim 1, characterized in that, The resistivity of the second substrate is greater than or equal to 100 Ω*cm.

15. The semiconductor structure as claimed in claim 1, characterized in that, The semiconductor structure is the semiconductor structure of an optical device, and the optical device has the same second substrate and deep trench isolation structure as the semiconductor structure.

16. The semiconductor structure as claimed in claim 1, characterized in that, The semiconductor structure is disposed on a wafer, the wafer includes dicing channels, and the semiconductor structure is located in the dicing channels.

17. A testing method, characterized in that, include: Provides a semiconductor structure as described in any one of claims 1-16; The first test signal loading terminal and the second test signal loading terminal are loaded with corresponding test signals to enable the first substrate, the second substrate of the first device region, the second substrate of the second device region, the first interconnect structure and the second interconnect structure to form a test path; Obtain the resistance of the test path; The inversion layer thickness of the corresponding second substrate sidewall is obtained based on the resistance.

18. The test method as described in claim 17, characterized in that, The distance between adjacent deep trench isolation structures in the first device area is the first spacing, and the distance between adjacent deep trench isolation structures in the second device area is the second spacing. Both the first spacing and the second spacing are less than or equal to a preset spacing, and the first spacing and the second spacing are equal; or, either the first spacing or the second spacing is less than or equal to the preset spacing, and the other is greater than the preset spacing. Among the adjacent first device area and second device area, the test spacing is the one that is less than or equal to the preset spacing between the first spacing and the second spacing. The step of obtaining the corresponding inversion layer thickness of the second substrate sidewall based on the resistance includes: The equivalent width of the test path is obtained based on the resistance, and half of the difference between the test spacing and the equivalent width is taken as the thickness of the inversion layer.

19. The test method as described in claim 18, characterized in that, The first substrate includes multiple sets of first device regions and second device regions. Adjacent first device regions and second device regions constitute a test unit region. The semiconductor structure includes multiple phase-spaced test unit regions, and the test spacing of the multiple test unit regions is not equal. In the step of obtaining the inversion layer thickness of the corresponding second substrate sidewall based on the resistance, the largest test spacing among one or more test unit areas where the resistance is greater than or equal to the preset resistance is taken as the target spacing, and half of the target spacing is taken as the inversion layer thickness.

20. The test method as described in claim 18, characterized in that, The step of obtaining the equivalent width of the test path based on the resistance includes: obtaining the geometric area of ​​the current path according to the formula R = ρL / S, where R represents the resistance, ρ represents the resistivity, and the resistivity is the resistivity of the second substrate, L represents the geometric length of the current path parallel to the current density direction of the first substrate, and when both the first spacing and the second spacing are less than or equal to a preset spacing, the geometric length of the current path is twice the thickness of the second substrate; when either the first spacing or the second spacing is less than or equal to the preset spacing, and the other is greater than the preset spacing, the geometric length of the current path is the thickness of the second substrate, and S represents the geometric area of ​​the current path perpendicular to the current density direction, and the geometric area of ​​the current path is the equivalent area of ​​the test path; The equivalent width of the test path is obtained based on the equivalent area.

21. The test method as described in claim 17, characterized in that, The absolute value of the voltage difference between the test signals applied to the first test signal loading terminal and the second test signal loading terminal is less than or equal to 0.1V.

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