A high-voltage electrostatic protection structure and a forming method thereof, and a d-tof device

Abstract

The application provides a high-voltage electrostatic protection structure and a forming method thereof and a d-TOF device. The high-voltage electrostatic protection structure comprises a logic wafer, a first diode structure is arranged in the logic wafer, and the first diode structure is electrically connected at a first threshold voltage; a pixel wafer, a second diode structure is arranged in the pixel wafer, the second diode structure is connected in series with the first diode structure, and the second diode structure is electrically connected at a second threshold voltage; wherein a first end of the second diode structure is electrically connected to a high-voltage power supply end of the d-TOF device, a second end of the second diode structure is electrically connected to a first end of the first diode structure, and a second end of the first diode structure is electrically connected to a ground end of the d-TOF device. The high-voltage electrostatic protection structure can protect the d-TOF device from being damaged in a packaging or wire bonding process and in a power-on process of a high-voltage power supply or in a voltage unstable condition.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a high voltage electrostatic protection structure and its formation method, as well as a d-TOF device. Background Technology

[0002] Single-photon avalanche diodes (SPADs) are currently the only solution for realizing direct time-of-flight (d-TOF) sensors. Single-photon applications require SPADs to operate in Geiger mode; therefore, SPAD arrays typically require a common terminal connected to a high-voltage power supply.

[0003] With the strong demand for 3D imaging in fields such as autonomous driving and AR / VR, the technology of realizing d-TOF sensing through 3D stacking of SPAD arrays and time-to-digital circuits (TDC) circuits has become increasingly mature and will be mass-produced in the near future.

[0004] However, a current problem is that the high-voltage power supply at the external common terminal can cause instantaneous high-voltage surges to the SPAD array during power-on or under unstable voltage conditions. This can also occur during chip packaging and wire bonding. These instantaneous high-voltage pulses may cause some damage to the SPAD device itself, and more seriously, can cause severe physical damage to the low-voltage logic circuits (mainly TDC circuits) connected in series at the other end of the SPAD. How to implement high-voltage electrostatic protection in the SPAD array has become the most urgent problem to be solved for the future mass production of d-TOF chips.

[0005] Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the Invention

[0006] This application provides a high-voltage electrostatic protection structure and its formation method, as well as a d-TOF device, which can protect the d-TOF device from damage during the packaging or wire bonding process, as well as during the power-on process of the high-voltage power supply or under unstable voltage conditions.

[0007] One aspect of this application provides a high-voltage electrostatic protection structure, comprising: a logic wafer having a first diode structure disposed therein, the first diode structure being electrically connected under a first threshold voltage; and a pixel wafer having a second diode structure disposed therein, connected in series with the first diode structure, the second diode structure being electrically connected under a second threshold voltage; wherein the logic wafer and the pixel wafer are bonded together, a first end of the second diode structure is electrically connected to the high-voltage power supply terminal of a d-TOF device, a second end of the second diode structure is electrically connected to the first end of the first diode structure, and the second end of the first diode structure is electrically connected to the ground terminal of the d-TOF device.

[0008] In some embodiments of this application, the logic wafer includes: a first substrate, in which a well region is disposed, and a first doped region and a second doped region are disposed on the surface of the well region, the first doped region, the second doped region and the well region constituting the first diode structure; a first dielectric layer located on the surface of the first substrate, in which a first metal connection structure and a second metal connection structure are disposed, penetrating the first dielectric layer and respectively electrically connecting the first doped region and the second doped region.

[0009] In some embodiments of this application, at least one of the first doped region and the second doped region has a doping type opposite to that of the well region, and the first doped region and the second doped region are electrically connected at the first threshold voltage.

[0010] In some embodiments of this application, the first threshold voltage is 5 to 15V.

[0011] In some embodiments of this application, the pixel wafer includes: a second substrate, in which a buried well region is disposed, and a third doped region and a fourth doped region are disposed in the buried well region, the third doped region, the fourth doped region and the buried well region constituting a second diode structure; and a second dielectric layer located on the surface of the second substrate, in which a third metal connection structure electrically connecting the first doped region and the fourth doped region is disposed.

[0012] In some embodiments of this application, the pixel wafer further includes: a first through-silicon via (TSV) structure located on one side of the buried well region, the TSV structure penetrating the second substrate and extending into the second dielectric layer, the TSV structure being electrically connected to the third doped region and the high-voltage power supply terminal of the d-TOF device; and a second TSV structure located on the other side of the buried well region, the second TSV structure penetrating the second substrate and extending into the second dielectric layer, the second TSV structure being electrically connected to the second doped region and the ground terminal of the d-TOF device.

[0013] In some embodiments of this application, the third doped region and the fourth doped region have opposite doping types, one of the third doped region and the fourth doped region has the same doping type as the buried well region, and the third doped region and the fourth doped region are electrically connected at the second threshold voltage.

[0014] In some embodiments of this application, the second threshold voltage is 20 to 60V.

[0015] In some embodiments of this application, the doping concentration of the third doped region and the fourth doped region is 5e16 to 1e18 atom / cm. 3 .

[0016] In some embodiments of this application, the third doped region and the fourth doped region have the same doping type, and the doping type of the third doped region and the fourth doped region is opposite to that of the buried well region.

[0017] In some embodiments of this application, a fifth doped region is further provided on both sides of the third doped region and the fourth doped region, and the doping type of the fifth doped region is opposite to that of the third doped region and the fourth doped region.

[0018] In some embodiments of this application, the spacing between the third doped region and the fourth doped region is 0.4 to 2 micrometers.

[0019] In some embodiments of this application, the bonding method between the logic wafer and the pixel wafer is hybrid bonding.

[0020] Another aspect of this application provides a method for forming a high-voltage electrostatic protection structure as described above, comprising: providing a logic wafer in which a first diode structure is disposed, the first diode structure being electrically connected under a first threshold voltage; providing a pixel wafer in which a second diode structure is disposed, connected in series with the first diode structure, the second diode structure being electrically connected under a second threshold voltage; bonding the logic wafer and the pixel wafer, wherein a first end of the second diode structure is electrically connected to a high-voltage power supply terminal of a d-TOF device, a second end of the second diode structure is electrically connected to a first end of the first diode structure, and a second end of the first diode structure is electrically connected to a ground terminal of the d-TOF device.

[0021] Another aspect of this application provides a d-TOF device, comprising: a high-voltage power supply; a single-photon avalanche diode connected to the high-voltage power supply; a time-to-digital converter, one end of which is connected to the single-photon avalanche diode and the other end of which is connected to a detection voltage; a reset circuit, one end of which is connected to the single-photon avalanche diode and the other end of which is connected to an operating voltage; a quenching circuit, one end of which is connected to the single-photon avalanche diode and the other end of which is grounded; and a high-voltage electrostatic protection structure as described above, wherein a first end of the second diode structure is connected to the high-voltage power supply, a second end of the first diode structure is grounded, and when the voltage of the high-voltage power supply is greater than or equal to the sum of the first threshold voltage and the second threshold voltage, the high-voltage electrostatic protection structure is electrically connected to the high-voltage power supply and the ground terminal.

[0022] This application provides a high-voltage electrostatic protection structure and its forming method, as well as a d-TOF device. The high-voltage electrostatic protection structure includes two diodes connected in series. The diodes can be electrically connected under a certain threshold voltage to ground the high-voltage power supply, thereby preventing damage to the d-TOF device from the high-voltage power supply during packaging or wire bonding, as well as during power-on or under unstable voltage conditions. Attached Figure Description

[0023] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0024] Figures 1 to 8 This is a schematic diagram of each step in the method for forming a high-voltage electrostatic protection structure according to the embodiments of this application;

[0025] Figure 9 This is a schematic diagram of the structure of the d-TOF device described in the embodiments of this application. Detailed Implementation

[0026] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0027] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0028] Regarding the issue of high-voltage current damage to d-TOF devices, current high-voltage electrostatic discharge (ESD) protection solutions mainly include: For ESD pulses introduced during the packaging and wire bonding process, this is currently achieved primarily through process control of the wire bonding machine and process, but process control reduces efficiency and increases costs; for situations involving external high-voltage power supply or unstable supply voltage, some solutions employ external ESD protection devices on the chip, but these increase the chip's size and weight. Furthermore, both solutions are specific to certain situations and cannot address both simultaneously.

[0029] In summary, since d-TOF technology is still in its nascent exploratory stage, there is no unified and effective approach for electrostatic discharge protection of the high-voltage side of SPAD.

[0030] To address the aforementioned issues, this application provides a high-voltage electrostatic protection structure and its formation method, as well as a d-TOF device. The high-voltage electrostatic protection structure includes two diodes connected in series. The diodes can be electrically connected under a certain threshold voltage to ground the high-voltage power supply, thereby preventing damage to the d-TOF device from the high-voltage power supply during packaging or wire bonding, as well as during power-on or under unstable voltage conditions.

[0031] Figures 1 to 8 This is a schematic diagram of each step in the method for forming a high-voltage electrostatic protection structure according to an embodiment of this application. The method for forming a high-voltage electrostatic protection structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0032] refer to Figures 1 to 2 As shown, a logic wafer 100 is provided, in which a first diode structure is disposed. The first diode structure is electrically connected under a first threshold voltage. The technical solution of this application is to protect the d-TOF device from damage by high-voltage current exceeding the operating voltage. Therefore, the first diode structure will not be connected under normal operating voltage and will not affect the operation of the device. Only when the operating voltage fluctuates and causes the actual voltage to exceed the set maximum operating voltage will the first diode structure be connected, thereby grounding the high-voltage current and protecting the device.

[0033] In some embodiments of this application, the logic wafer 100 is the wafer used to fabricate logic devices in the d-TOF device. The first diode structure can be fabricated in the logic wafer like other logic devices, utilizing unused space in the logic wafer to fabricate the first diode structure, etc., without increasing the area of ​​the original device.

[0034] refer to Figure 1As shown, a first substrate 110 is provided, in which a well region 120 is formed. A first doped region 130 and a second doped region 140 are also formed on the surface of the well region 120. The first doped region 130, the second doped region 140 and the well region 120 constitute the first diode structure.

[0035] In some embodiments of this application, the method for forming the first doped region 130, the second doped region 140, and the well region 120 includes an ion implantation process.

[0036] In some embodiments of this application, at least one of the first doped region 130 and the second doped region 140 has a doping type opposite to that of the well region 120, and the first doped region 130 and the second doped region 140 are electrically connected at the first threshold voltage.

[0037] In this embodiment, the doping type of the first doped region 130 is opposite to that of the well region 120, and the doping type of the second doped region 140 is the same as that of the well region 120. For example, the doping type of the first doped region 130 is P-type, the doping type of the second doped region 140 is N-type, and the doping type of the well region 120 is N-type. The working principle of the first diode structure (composed of the first doped region 130, the second doped region 140, and the well region 120) is as follows: When the voltage applied to the first diode structure is below the first voltage threshold, a PN junction is formed between the first doped region 130 and the well region 120 due to their different doping types. Therefore, the first doped region 130 and the well region 120 are not electrically connected, and consequently, the first doped region 130 and the second doped region 140 are also not electrically connected. When the voltage applied to the first diode structure is greater than or equal to the first voltage threshold, the PN junction is broken down, causing the first doped region 130 and the well region 120 to become electrically connected, and consequently, the first doped region 130 and the second doped region 140 also become electrically connected.

[0038] In some other embodiments of this application, the doping type of the first doped region 130 may be the same as the doping type of the well region 120, and the doping type of the second doped region 140 may be opposite to the doping type of the well region 120. In some other embodiments of this application, the doping types of both the first doped region 130 and the second doped region 140 may be opposite to the doping type of the well region 120.

[0039] In some embodiments of this application, the doping types of the first doped region 130, the second doped region 140, and the well region 120 can be set according to the P / N type of the second diode structure. Specifically, the unidirectional conduction directions of the PN junctions of the first diode and the second diode are consistent.

[0040] In some embodiments of this application, the doping concentration of the first doped region 130 and the second doped region 140 is greater than the doping concentration of the well region 120. This is because the first doped region 130 and the second doped region 140 need to maintain an ohmic contact between the metal and semiconductor materials, thus requiring a relatively high doping concentration. For example, the doping concentration of the first doped region 130 is 5e19 to 5e20 atoms / cm³; the doping concentration of the second doped region 140 is 5e19 to 5e20 atoms / cm³; and the doping concentration of the well region 120 is 5e15 to 1e18 atoms / cm³. By controlling the doping concentration difference between the first doped region 130, the second doped region 140, and the well region 120, the magnitude of the first threshold voltage can be controlled.

[0041] In some embodiments of this application, the first threshold voltage is 5 to 15V.

[0042] In some embodiments of this application, the number of first diode structures formed in the first substrate 110 may be multiple. For simplicity, only one first diode structure is shown in the accompanying drawings.

[0043] In some embodiments of this application, the first diode structure in the first substrate 110 can also be replaced with other structures that can perform the same function, such as GGNMOS and GDPMOS structures.

[0044] refer to Figure 2 As shown, a first dielectric layer 150 is formed on the surface of the first substrate 110. A first metal connection structure 160 and a second metal connection structure 170 are formed in the first dielectric layer 150, which penetrate the first dielectric layer 150 and electrically connect the first doped region 130 and the second doped region 140, respectively.

[0045] In some embodiments of this application, the material of the first dielectric layer 150 is silicon oxide. Methods for forming the first dielectric layer 150 include chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0046] It should be noted that the accompanying drawings only roughly show the connection relationship, position, and shape of the first metal connection structure 160 and the second metal connection structure 170. In reality, the first metal connection structure 160 and the second metal connection structure 170 are multi-layer metal interconnects, similar to the multi-layer metal interconnects formed in conventional back-end processes.

[0047] In some embodiments of this application, a plurality of bonding pads (not shown in the figure) embedded in the first dielectric layer 150 are also formed on the surface of the first dielectric layer 150 for mixed bonding.

[0048] refer to Figures 3 to 6 As shown, a pixel wafer 200 is provided, in which a second diode structure is formed in series with the first diode structure. The second diode structure is electrically connected under a second threshold voltage. The technical solution of this application is to protect the d-TOF device from damage by high-voltage current exceeding the operating voltage. Therefore, the second diode structure will not be connected under normal operating voltage and will not affect the device's operation. Only when the operating voltage fluctuates, causing the actual voltage to exceed the set maximum operating voltage, will the second diode structure connect, thereby grounding the high-voltage current and protecting the device. Since the first diode structure and the second diode structure are connected in series, the comprehensive threshold voltage of the high-voltage electrostatic protection structure is the sum of the first threshold voltage and the second threshold voltage.

[0049] In some embodiments of this application, the pixel wafer 200 is the wafer used to fabricate pixel elements in the d-TOF device. The second diode structure can be fabricated in the pixel wafer in the same way as the pixel elements, utilizing unused space in the pixel wafer to fabricate the second diode structure, etc., in the technical solution of this application, without increasing the area of ​​the original device.

[0050] refer to Figure 3 As shown, a second substrate 210 is provided, in which a buried well region 220 is formed. A third doped region 230 and a fourth doped region 240 are formed in the buried well region 220. The third doped region 230, the fourth doped region 240 and the buried well region 220 constitute the second diode structure.

[0051] In some embodiments of this application, the method for forming the third doped region 230, the fourth doped region 240, and the buried trap region 220 includes an ion implantation process.

[0052] In some embodiments of this application, the second diode structure is a multi-finger structure in which the third doped region 230 and the fourth doped region 240 have opposite doping types, one of the third doped region 230 and the fourth doped region 240 has the same doping type as the buried well region 220, and the third doped region 230 and the fourth doped region 240 are electrically connected at the second threshold voltage.

[0053] In this embodiment, the third doped region 230 and the fourth doped region 240 have opposite doping types, while the fourth doped region 240 has the same doping type as the buried well region 220. For example, the third doped region 230 has a P-type doping type, the fourth doped region 240 has an N-type doping type, and the buried well region 220 has an N-type doping type. The working principle of the second diode structure (composed of the third doped region 230, the fourth doped region 240, and the buried well region 220) is as follows: When the voltage applied to the second diode structure is below the second voltage threshold, a PN junction is formed between the third doped region 230 and the buried well region 220 due to their different doping types. Therefore, the third doped region 230 and the buried well region 220 are not electrically connected, and consequently, the third doped region 230 and the fourth doped region 240 are also not electrically connected. When the voltage applied to the second diode structure is greater than or equal to the second voltage threshold, the PN junction is broken down, causing the third doped region 230 and the buried well region 220 to become electrically connected, and consequently, the third doped region 230 and the fourth doped region 240 also become electrically connected.

[0054] In some other embodiments of this application, the doping type of the third doped region 230 may be the same as that of the buried well region 220, and the doping type of the fourth doped region 240 may be opposite to that of the buried well region 220.

[0055] In some embodiments of this application, the doping types of the third doped region 230, the fourth doped region 240, and the buried well region 220 can be set according to the type of the d-TOF device. For a P-type SPAD (where N / P type is defined by the common terminal of the lightly doped SPAD), the third doped region 230 is P-type, while the fourth doped region 240 is N-type, and the buried well region 220 can be either N-type or P-type. For an N-type SPAD, the third doped region 230 is N-type, while the fourth doped region 240 is P-type, and the buried well region 220 can be either N-type or P-type.

[0056] In some embodiments of this application, the doping concentrations of the third doped region 230 and the fourth doped region 240 are greater than the doping concentration of the buried well region 220. The doping concentration of the third doped region 230 is, for example, 5e16 to 1e18 atoms / cm². 3 The doping concentration of the fourth doped region 240 is, for example, 5e16 to 1e18 atom / cm³. 3 The doping depths of the third doped region 230 and the fourth doped region 240 are greater than 0.5 μm to reduce on-resistance. The doping concentration of the buried well region 220 is, for example, 1e15 to 5e16 atom / cm. 3 When the doping concentration of the buried well region 220 is too low, the on-resistance will be relatively high; when the doping concentration of the buried well region 220 is too high, the threshold voltage will be too low. By controlling the doping concentration difference between the third doping region 230, the fourth doping region 240, and the buried well region 220, the magnitude of the second threshold voltage can be controlled.

[0057] In some embodiments of this application, the second threshold voltage is 20 to 60V.

[0058] In some embodiments of this application, the total width of the third doped region 230 and the fourth doped region 240 is greater than 500 micrometers.

[0059] In some embodiments of this application, a third highly doped region 231 may be formed on the surface of the third doped region 230, wherein the doping concentration of the third highly doped region 231 is higher than that of the third doped region 230, and the third highly doped region 231 is used to improve the electrical connectivity of the third doped region 230; a fourth highly doped region 241 may be formed on the surface of the fourth doped region 240, wherein the doping concentration of the fourth highly doped region 241 is higher than that of the fourth doped region 240, and the fourth highly doped region 241 is used to improve the electrical connectivity of the fourth doped region 240. To achieve an ohmic contact, the doping concentrations of the third highly doped region 231 and the fourth highly doped region 241 are greater than 5e19atom / cm². 3 .

[0060] In some other embodiments of this application, the second diode structure may also be a BJT structure, in which the third doped region 230 and the fourth doped region 240 have the same doping type, the third doped region 230 and the fourth doped region 240 have the opposite doping type to the buried well region 220, and the third doped region 230 and the fourth doped region 240 are electrically connected at the second threshold voltage.

[0061] For example, the third doping region 230 is P-type, the fourth doping region 240 is P-type, and the buried well region 220 is N-type. The second diode structure (composed of the third doped region 230, the fourth doped region 240, and the buried well region 220) operates as follows: When the voltage applied to the second diode structure is below the second voltage threshold, the third doped region 230, the fourth doped region 240, and the buried well region 220 form PNP or NPN junctions due to their different doping types. Therefore, the third doped region 230 and the buried well region 220 are not electrically connected, or the fourth doped region 240 and the buried well region 220 are not electrically connected, and consequently, the third doped region 230 and the fourth doped region 240 are not electrically connected. When the voltage applied to the second diode structure is greater than or equal to the second voltage threshold, the third doped region 230 and the fourth doped region 240 expand, causing them to directly contact and thus become electrically connected.

[0062] In some embodiments of this application, the spacing between the third doped region 230 and the fourth doped region 240 is 0.4 to 2 micrometers. The magnitude of the second threshold voltage can be controlled by controlling this spacing; the larger the spacing, the larger the second threshold voltage.

[0063] In some embodiments of this application, in this BJT structure, a fifth doped region is further provided on both sides of the third doped region 230 and the fourth doped region 240. Figure 3 (Not shown in the text, but will be explained and shown later), the fifth doped region has the opposite doping type to the third doped region 230 and the fourth doped region 240. The fifth doped region is used to form a PN junction with the third doped region 230 and the fourth doped region 240 to protect the third doped region 230 and the fourth doped region 240.

[0064] In some embodiments of this application, the number of second diode structures formed in the second substrate 210 may be multiple. For simplicity, only one second diode structure is shown in the accompanying drawings.

[0065] refer to Figure 4 As shown, a second dielectric layer 250 is formed on the surface of the second substrate 210, and a third metal connection structure 260 for electrically connecting the first doped region 130 and the fourth doped region 240 is disposed in the second dielectric layer 250.

[0066] In some embodiments of this application, the material of the second dielectric layer 250 is silicon oxide. Methods for forming the second dielectric layer 250 include chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0067] It should be noted that the accompanying drawings only roughly show the connection relationship, position, and shape of the third metal connection structure 260. In reality, the third metal connection structure 260 is a multi-layer metal interconnect, similar to the multi-layer metal interconnects formed in conventional back-end processes.

[0068] In some embodiments of this application, a plurality of bonding pads (not shown in the figure) embedded in the second dielectric layer 250 are also formed on the surface of the second dielectric layer 250 for mixed bonding.

[0069] refer to Figure 5 As shown, a first through-silicon via (TSV) structure 270 is formed in the second substrate 210, located on one side of the buried well region 220. The first TSV structure 270 penetrates the second substrate 210 and extends into the second dielectric layer 250. The first TSV structure 270 is electrically connected to the third doped region 230 and the high-voltage power supply terminal of the d-TOF device. A second TSV structure 280 is formed in the second substrate 210, located on the other side of the buried well region 220. The second TSV structure 280 penetrates the second substrate 210 and extends into the second dielectric layer 250. The second TSV structure 280 is used to electrically connect the second doped region 140 and the ground terminal of the d-TOF device.

[0070] Specifically, the electrical connection relationship of the high-voltage electrostatic protection structure can be simplified as follows: high-voltage power supply - second diode structure - first diode structure - ground. When the voltage at the high-voltage power supply terminal is greater than or equal to the sum of the first threshold voltage and the second threshold voltage, the first diode structure and the second diode structure are connected, thereby grounding the high-voltage power supply and protecting the d-TOF device from high-voltage damage.

[0071] refer to Figure 6 As shown, Figure 6 This is a schematic diagram of the electrical connections of the second diode structure of the multi-finger structure described in this application embodiment. Several third doped regions 230 and fourth doped regions 240 are alternately distributed in the second substrate 220. The third doped regions 230 are electrically connected to a high-voltage power supply HV, and the fourth doped regions 240 are grounded GND.

[0072] refer to Figure 7 As shown, Figure 7This is a schematic diagram of the electrical connections of the second diode structure of the BJT structure described in this application embodiment. Several third doped regions 230 and fourth doped regions 240 are alternately distributed in the second substrate 220. The third doped regions 230 are electrically connected to a high-voltage power supply HV, and the fourth doped regions 240 are grounded (GND). Fifth doped regions 290, as described above, are also provided on both sides of the third doped regions 230 and the fourth doped regions 240. Depending on the type of SPAD and the type of BJT structure, the fifth doped region 290 can be electrically connected to the high-voltage power supply HV or grounded (GND).

[0073] refer to Figure 8 As shown, the logic wafer 100 and the pixel wafer 200 are bonded together, wherein the first end of the second diode structure is electrically connected to the high-voltage power supply terminal of the d-TOF device, the second end of the second diode structure is electrically connected to the first end of the first diode structure, and the second end of the first diode structure is electrically connected to the ground terminal of the d-TOF device.

[0074] In some embodiments of this application, the logic wafer 100 and the pixel wafer 200 are bonded using a hybrid bonding method. This bonding method can directly utilize bonding pads to achieve electrical connection between the two wafers, and its structure is simpler than that of fused bonding.

[0075] The present application discloses a method for forming a high-voltage electrostatic protection structure, wherein the high-voltage electrostatic protection structure includes two diodes connected in series. The diodes can be electrically connected under a certain threshold voltage to ground the high-voltage power supply, thereby preventing the high-voltage power supply from damaging the d-TOF device during the packaging or wire bonding process, as well as during the power-on process or under unstable voltage conditions.

[0076] Embodiments of this application also provide a high-voltage electrostatic protection structure, see reference. Figure 8 As shown, the device includes: a logic wafer 100, in which a first diode structure is disposed, the first diode structure being electrically connected under a first threshold voltage; and a pixel wafer 200, in which a second diode structure is disposed, connected in series with the first diode structure, the second diode structure being electrically connected under a second threshold voltage; wherein, the logic wafer 100 and the pixel wafer 200 are bonded together, the first end of the second diode structure is electrically connected to the high-voltage power supply terminal of the d-TOF device, the second end of the second diode structure is electrically connected to the first end of the first diode structure, and the second end of the first diode structure is electrically connected to the ground terminal of the d-TOF device.

[0077] refer to Figure 8As shown, a first diode structure is provided in the logic wafer 100, and the first diode structure is electrically connected under a first threshold voltage. The technical solution of this application is to protect the d-TOF device from damage by high-voltage current exceeding the operating voltage. Therefore, the first diode structure will not be connected under normal operating voltage and will not affect the operation of the device. Only when the operating voltage fluctuates and causes the actual voltage to exceed the set maximum operating voltage will the first diode structure be connected, thereby grounding the high-voltage current and protecting the device.

[0078] In some embodiments of this application, the logic wafer 100 is the wafer used to fabricate logic devices in the d-TOF device. The first diode structure can be fabricated in the logic wafer like other logic devices, utilizing unused space in the logic wafer to fabricate the first diode structure, etc., without increasing the area of ​​the original device.

[0079] Continue to refer to Figure 8 As shown, the logic wafer 100 includes: a first substrate 110, a well region 120 disposed in the first substrate 110, and a first doped region 130 and a second doped region 140 disposed on the surface of the well region 120, wherein the first doped region 130, the second doped region 140 and the well region 120 constitute the first diode structure.

[0080] In some embodiments of this application, at least one of the first doped region 130 and the second doped region 140 has a doping type opposite to that of the well region 120, and the first doped region 130 and the second doped region 140 are electrically connected at the first threshold voltage.

[0081] In this embodiment, the doping type of the first doped region 130 is opposite to that of the well region 120, and the doping type of the second doped region 140 is the same as that of the well region 120. For example, the doping type of the first doped region 130 is P-type, the doping type of the second doped region 140 is N-type, and the doping type of the well region 120 is N-type. The working principle of the first diode structure (composed of the first doped region 130, the second doped region 140, and the well region 120) is as follows: When the voltage applied to the first diode structure is below the first voltage threshold, a PN junction is formed between the first doped region 130 and the well region 120 due to their different doping types. Therefore, the first doped region 130 and the well region 120 are not electrically connected, and consequently, the first doped region 130 and the second doped region 140 are also not electrically connected. When the voltage applied to the first diode structure is greater than or equal to the first voltage threshold, the PN junction is broken down, causing the first doped region 130 and the well region 120 to become electrically connected, and consequently, the first doped region 130 and the second doped region 140 also become electrically connected.

[0082] In some other embodiments of this application, the doping type of the first doped region 130 may be the same as the doping type of the well region 120, and the doping type of the second doped region 140 may be opposite to the doping type of the well region 120. In some other embodiments of this application, the doping types of both the first doped region 130 and the second doped region 140 may be opposite to the doping type of the well region 120.

[0083] In some embodiments of this application, the doping types of the first doped region 130, the second doped region 140, and the well region 120 can be set according to the P / N type of the second diode structure. Specifically, the unidirectional conduction directions of the PN junctions of the first diode and the second diode are consistent.

[0084] In some embodiments of this application, the doping concentration of the first doped region 130 and the second doped region 140 is greater than the doping concentration of the well region 120. This is because the first doped region 130 and the second doped region 140 need to maintain an ohmic contact between the metal and semiconductor materials, thus requiring a relatively high doping concentration. For example, the doping concentration of the first doped region 130 is 5e19 to 5e20 atoms / cm³; the doping concentration of the second doped region 140 is 5e19 to 5e20 atoms / cm³; and the doping concentration of the well region 120 is 5e15 to 1e18 atoms / cm³. By controlling the doping concentration difference between the first doped region 130, the second doped region 140, and the well region 120, the magnitude of the first threshold voltage can be controlled.

[0085] In some embodiments of this application, the first threshold voltage is 5 to 15V.

[0086] In some embodiments of this application, the number of first diode structures formed in the first substrate 110 may be multiple. For simplicity, only one first diode structure is shown in the accompanying drawings.

[0087] In some embodiments of this application, the first diode structure in the first substrate 110 can also be replaced with other structures that can perform the same function, such as GGNMOS and GDPMOS structures.

[0088] Continue to refer to Figure 8 As shown, the logic wafer 100 further includes a first dielectric layer 150 located on the surface of the first substrate 110. The first dielectric layer 150 is provided with a first metal connection structure 160 and a second metal connection structure 170 that penetrate the first dielectric layer 150 and electrically connect the first doped region 130 and the second doped region 140, respectively.

[0089] In some embodiments of this application, the material of the first dielectric layer 150 is silicon oxide.

[0090] It should be noted that the accompanying drawings only roughly show the connection relationship, position, and shape of the first metal connection structure 160 and the second metal connection structure 170. In reality, the first metal connection structure 160 and the second metal connection structure 170 are multi-layer metal interconnects, similar to the multi-layer metal interconnects formed in conventional back-end processes.

[0091] In some embodiments of this application, a plurality of bonding pads (not shown in the figure) embedded in the first dielectric layer 150 are also formed on the surface of the first dielectric layer 150 for mixed bonding.

[0092] Continue to refer to Figure 8 As shown, a second diode structure is provided in the pixel wafer 200, connected in series with the first diode structure. The second diode structure is electrically connected under a second threshold voltage. The technical solution of this application is to protect the d-TOF device from damage by high-voltage current exceeding the operating voltage. Therefore, the second diode structure will not be connected under normal operating voltage, and will not affect the device's operation. Only when the operating voltage fluctuates, causing the actual voltage to exceed the set maximum operating voltage, will the second diode structure connect, thereby grounding the high-voltage current and protecting the device. Since the first diode structure and the second diode structure are connected in series, the comprehensive threshold voltage of the high-voltage electrostatic protection structure is the sum of the first threshold voltage and the second threshold voltage.

[0093] In some embodiments of this application, the pixel wafer 200 is the wafer used to fabricate pixel elements in the d-TOF device. The second diode structure can be fabricated in the pixel wafer in the same way as the pixel elements, utilizing unused space in the pixel wafer to fabricate the second diode structure, etc., in the technical solution of this application, without increasing the area of ​​the original device.

[0094] Continue to refer to Figure 8 As shown, the pixel wafer 200 includes: a second substrate 210, in which a buried well region 220 is disposed, and in which a third doped region 230 and a fourth doped region 240 are disposed, wherein the third doped region 230, the fourth doped region 240 and the buried well region 220 constitute the second diode structure.

[0095] In some embodiments of this application, the second diode structure is a multi-finger structure in which the third doped region 230 and the fourth doped region 240 have opposite doping types, one of the third doped region 230 and the fourth doped region 240 has the same doping type as the buried well region 220, and the third doped region 230 and the fourth doped region 240 are electrically connected at the second threshold voltage.

[0096] In this embodiment, the third doped region 230 and the fourth doped region 240 have opposite doping types, while the fourth doped region 240 has the same doping type as the buried well region 220. For example, the third doped region 230 has a P-type doping type, the fourth doped region 240 has an N-type doping type, and the buried well region 220 has an N-type doping type. The working principle of the second diode structure (composed of the third doped region 230, the fourth doped region 240, and the buried well region 220) is as follows: When the voltage applied to the second diode structure is below the second voltage threshold, a PN junction is formed between the third doped region 230 and the buried well region 220 due to their different doping types. Therefore, the third doped region 230 and the buried well region 220 are not electrically connected, and consequently, the third doped region 230 and the fourth doped region 240 are also not electrically connected. When the voltage applied to the second diode structure is greater than or equal to the second voltage threshold, the PN junction is broken down, causing the third doped region 230 and the buried well region 220 to become electrically connected, and consequently, the third doped region 230 and the fourth doped region 240 also become electrically connected.

[0097] In some other embodiments of this application, the doping type of the third doped region 230 may be the same as that of the buried well region 220, and the doping type of the fourth doped region 240 may be opposite to that of the buried well region 220.

[0098] In some embodiments of this application, the doping types of the third doped region 230, the fourth doped region 240, and the buried well region 220 can be set according to the type of the d-TOF device. For a P-type SPAD (where N / P type is defined by the common terminal of the lightly doped SPAD), the third doped region 230 is P-type, while the fourth doped region 240 is N-type, and the buried well region 220 can be either N-type or P-type. For an N-type SPAD, the third doped region 230 is N-type, while the fourth doped region 240 is P-type, and the buried well region 220 can be either N-type or P-type.

[0099] In some embodiments of this application, the doping concentrations of the third doped region 230 and the fourth doped region 240 are greater than the doping concentration of the buried well region 220. The doping concentration of the third doped region 230 is, for example, 5e16 to 1e18 atoms / cm². 3 The doping concentration of the fourth doped region 240 is, for example, 5e16 to 1e18 atom / cm³. 3 The doping depths of the third doped region 230 and the fourth doped region 240 are greater than 0.5 μm to reduce on-resistance. The doping concentration of the buried well region 220 is, for example, 1e15 to 5e16 atom / cm. 3 When the doping concentration of the buried well region 220 is too low, the on-resistance will be relatively high; when the doping concentration of the buried well region 220 is too high, the threshold voltage will be too low. By controlling the doping concentration difference between the third doping region 230, the fourth doping region 240, and the buried well region 220, the magnitude of the second threshold voltage can be controlled.

[0100] In some embodiments of this application, the second threshold voltage is 20 to 60V.

[0101] In some embodiments of this application, the total width of the third doped region 230 and the fourth doped region 240 is greater than 500 micrometers.

[0102] In some embodiments of this application, a third highly doped region 231 may be formed on the surface of the third doped region 230, wherein the doping concentration of the third highly doped region 231 is higher than that of the third doped region 230, and the third highly doped region 231 is used to improve the electrical connectivity of the third doped region 230; a fourth highly doped region 241 may be formed on the surface of the fourth doped region 240, wherein the doping concentration of the fourth highly doped region 241 is higher than that of the fourth doped region 240, and the fourth highly doped region 241 is used to improve the electrical connectivity of the fourth doped region 240. To achieve an ohmic contact, the doping concentrations of the third highly doped region 231 and the fourth highly doped region 241 are greater than 5e19atom / cm².3 .

[0103] In some other embodiments of this application, the second diode structure may also be a BJT structure, in which the third doped region 230 and the fourth doped region 240 have the same doping type, the third doped region 230 and the fourth doped region 240 have the opposite doping type to the buried well region 220, and the third doped region 230 and the fourth doped region 240 are electrically connected at the second threshold voltage.

[0104] For example, the third doping region 230 is P-type, the fourth doping region 240 is P-type, and the buried well region 220 is N-type. The second diode structure (composed of the third doped region 230, the fourth doped region 240, and the buried well region 220) operates as follows: When the voltage applied to the second diode structure is below the second voltage threshold, the third doped region 230, the fourth doped region 240, and the buried well region 220 form PNP or NPN junctions due to their different doping types. Therefore, the third doped region 230 and the buried well region 220 are not electrically connected, or the fourth doped region 240 and the buried well region 220 are not electrically connected, and consequently, the third doped region 230 and the fourth doped region 240 are not electrically connected. When the voltage applied to the second diode structure is greater than or equal to the second voltage threshold, the third doped region 230 and the fourth doped region 240 expand, causing them to directly contact and thus become electrically connected.

[0105] In some embodiments of this application, the spacing between the third doped region 230 and the fourth doped region 240 is 0.4 to 2 micrometers. The magnitude of the second threshold voltage can be controlled by controlling this spacing; the larger the spacing, the larger the second threshold voltage.

[0106] In some embodiments of this application, in this BJT structure, a fifth doped region is further provided on both sides of the third doped region 230 and the fourth doped region 240. The fifth doped region has the opposite doping type to the third doped region 230 and the fourth doped region 240. The fifth doped region is used to form a PN junction with the third doped region 230 and the fourth doped region 240, thereby protecting the third doped region 230 and the fourth doped region 240.

[0107] In some embodiments of this application, the number of second diode structures formed in the second substrate 210 may be multiple. For simplicity, only one second diode structure is shown in the accompanying drawings.

[0108] Continue to refer to Figure 8As shown, the pixel wafer 200 further includes a second dielectric layer 250 located on the surface of the second substrate 210. The second dielectric layer 250 is provided with a third metal connection structure 260 for electrically connecting the first doped region 130 and the fourth doped region 240.

[0109] In some embodiments of this application, the material of the second dielectric layer 250 is silicon oxide.

[0110] It should be noted that the accompanying drawings only roughly show the connection relationship, position, and shape of the third metal connection structure 260. In reality, the third metal connection structure 260 is a multi-layer metal interconnect, similar to the multi-layer metal interconnects formed in conventional back-end processes.

[0111] In some embodiments of this application, a plurality of bonding pads (not shown in the figure) embedded in the second dielectric layer 250 are also formed on the surface of the second dielectric layer 250 for mixed bonding.

[0112] Continue to refer to Figure 8 As shown, the pixel wafer 200 further includes: a first through-silicon via (TSV) structure 270 located on one side of the buried well region 220, the first TSV structure 270 penetrating the second substrate 210 and extending into the second dielectric layer 250, the first TSV structure 270 electrically connecting the third doped region 230 and the high-voltage power supply terminal of the d-TOF device; and a second TSV structure 280 located on the other side of the buried well region 220, the second TSV structure 280 penetrating the second substrate 210 and extending into the second dielectric layer 250, the second TSV structure 280 being used to electrically connect the second doped region 140 and the ground terminal of the d-TOF device.

[0113] Specifically, the electrical connection relationship of the high-voltage electrostatic protection structure can be simplified as follows: high-voltage power supply - second diode structure - first diode structure - ground. When the voltage at the high-voltage power supply terminal is greater than or equal to the sum of the first threshold voltage and the second threshold voltage, the first diode structure and the second diode structure are connected, thereby grounding the high-voltage power supply and protecting the d-TOF device from high-voltage damage.

[0114] refer to Figure 6 As shown, Figure 6 This is a schematic diagram of the electrical connections of the second diode structure of the multi-finger structure described in this application embodiment. Several third doped regions 230 and fourth doped regions 240 are alternately distributed in the second substrate 220. The third doped regions 230 are electrically connected to a high-voltage power supply HV, and the fourth doped regions 240 are grounded GND.

[0115] refer to Figure 7As shown, Figure 7 This is a schematic diagram of the electrical connections of the second diode structure of the BJT structure described in this application embodiment. Several third doped regions 230 and fourth doped regions 240 are alternately distributed in the second substrate 220. The third doped regions 230 are electrically connected to a high-voltage power supply HV, and the fourth doped regions 240 are grounded (GND). Fifth doped regions 290, as described above, are also provided on both sides of the third doped regions 230 and the fourth doped regions 240. Depending on the type of SPAD and the type of BJT structure, the fifth doped region 290 can be electrically connected to the high-voltage power supply HV or grounded (GND).

[0116] Continue to refer to Figure 8 As shown, the logic wafer 100 and the pixel wafer 200 are bonded together, wherein the first end of the second diode structure is electrically connected to the high-voltage power supply terminal of the d-TOF device, the second end of the second diode structure is electrically connected to the first end of the first diode structure, and the second end of the first diode structure is electrically connected to the ground terminal of the d-TOF device.

[0117] In some embodiments of this application, the logic wafer 100 and the pixel wafer 200 are bonded using a hybrid bonding method. This bonding method can directly utilize bonding pads to achieve electrical connection between the two wafers, and its structure is simpler than that of fused bonding.

[0118] The high-voltage electrostatic protection structure described in this application includes two diodes connected in series. The diodes can be electrically connected under a certain threshold voltage to ground the high-voltage power supply, thereby preventing damage to the d-TOF device during the packaging or wire bonding process, as well as during power-on or under unstable voltage conditions.

[0119] Figure 9 This is a schematic diagram of the structure of the d-TOF device described in the embodiments of this application.

[0120] Embodiments of this application also provide a d-TOF device, referenced Figure 9 As shown, it includes: a high-voltage power supply HV; a single-photon avalanche diode 340 (SPAD) connected to the high-voltage power supply HV; and a time-to-digital converter 310 (TDC), one end of which is connected to the single-photon avalanche diode 340, and the other end of which is connected to the detection voltage V. senseThe system includes a reset circuit 320, with one end connected to the single-photon avalanche diode 340 and the other end connected to the operating voltage VDD; a quench circuit 330, with one end connected to the single-photon avalanche diode 340 and the other end grounded to GND; and a high-voltage electrostatic discharge (ESD) protection structure 350, as described above, with one end connected to the high-voltage power supply HV and the other end grounded to GND. Specifically, the first end of the second diode structure (i.e., the first through-silicon via structure 270) is connected to the high-voltage power supply HV, and the second end of the first diode structure (i.e., the second through-silicon via structure 280) is grounded to GND. When the voltage of the high-voltage power supply HV is greater than or equal to the sum of the first threshold voltage and the second threshold voltage, the high-voltage ESD protection structure 350 electrically connects the high-voltage power supply HV and the grounded terminal GND, thereby introducing high-voltage current into the bottom surface and protecting the device from damage by high-voltage current.

[0121] The single-photon avalanche diode 340, time-to-digital converter 310, reset circuit 320, and quenching circuit 330 in the d-TOF device are all the same as their corresponding structures in conventional d-TOF devices, and will not be described in detail here.

[0122] This application provides a high-voltage electrostatic protection structure and its forming method, as well as a d-TOF device. The high-voltage electrostatic protection structure includes two diodes connected in series. The diodes can be electrically connected under a certain threshold voltage to ground the high-voltage power supply, thereby preventing damage to the d-TOF device from the high-voltage power supply during packaging or wire bonding, as well as during power-on or under unstable voltage conditions.

[0123] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0124] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0125] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0126] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0127] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A high-voltage electrostatic protection structure, characterized in that, include: A logic wafer, wherein a first diode structure is disposed in the logic wafer, and the first diode structure is electrically connected under a first threshold voltage; A pixel wafer, wherein a second diode structure is disposed therein, which is connected in series with the first diode structure, and the second diode structure is electrically connected under a second threshold voltage; The logic wafer and the pixel wafer are bonded together. The first end of the second diode structure is electrically connected to the high-voltage power supply terminal of the d-TOF device, the second end of the second diode structure is electrically connected to the first end of the first diode structure, and the second end of the first diode structure is electrically connected to the ground terminal of the d-TOF device.

2. The high-voltage electrostatic protection structure as described in claim 1, characterized in that, The logic wafer includes: A first substrate has a well region therein, and a first doped region and a second doped region are further disposed on the surface of the well region. The first doped region, the second doped region and the well region constitute the first diode structure. A first dielectric layer is located on the surface of the first substrate. The first dielectric layer has a first metal connection structure and a second metal connection structure that penetrate the first dielectric layer and electrically connect the first doped region and the second doped region, respectively.

3. The high-voltage electrostatic protection structure as described in claim 2, characterized in that, At least one of the first doped region and the second doped region has a doping type opposite to that of the well region, and the first doped region and the second doped region are electrically connected at the first threshold voltage.

4. The high-voltage electrostatic protection structure as described in claim 3, characterized in that, The first threshold voltage is 5 to 15V.

5. The high-voltage electrostatic protection structure as described in claim 2, characterized in that, The pixel wafer includes: A second substrate is provided in which a buried well region is provided, and a third doped region and a fourth doped region are provided in the buried well region. The third doped region, the fourth doped region and the buried well region constitute the second diode structure. A second dielectric layer is located on the surface of the second substrate, and a third metal connection structure is disposed in the second dielectric layer to electrically connect the first doped region and the fourth doped region.

6. The high-voltage electrostatic protection structure as described in claim 5, characterized in that, The pixel wafer also includes: A first through-silicon via (TSV) structure is located on one side of the buried well region. The TSV structure penetrates the second substrate and extends into the second dielectric layer. The TSV structure is electrically connected to the third doped region and the high-voltage power supply terminal of the d-TOF device. A second through-silicon via (TSV) structure is located on the other side of the buried well region. The TSV structure penetrates the second substrate and extends into the second dielectric layer. The TSV structure is electrically connected to the second doped region and the ground terminal of the d-TOF device.

7. The high-voltage electrostatic protection structure as described in claim 5, characterized in that, The third doped region and the fourth doped region have opposite doping types. One of the third doped region and the fourth doped region has the same doping type as the buried well region. The third doped region and the fourth doped region are electrically connected at the second threshold voltage.

8. The high-voltage electrostatic protection structure as described in claim 7, characterized in that, The second threshold voltage is 20 to 60V.

9. The high-voltage electrostatic protection structure as described in claim 7, characterized in that, The doping concentration of the third and fourth doped regions is 5e16 to 1e18 atom / cm³. 3 .

10. The high-voltage electrostatic protection structure as described in claim 5, characterized in that, The third doped region and the fourth doped region have the same doping type, while the doping type of the third doped region and the fourth doped region is opposite to that of the buried trap region.

11. The high-voltage electrostatic protection structure as described in claim 10, characterized in that, A fifth doping region is provided on both sides of the third and fourth doping regions, and the doping type of the fifth doping region is opposite to that of the third and fourth doping regions.

12. The high-voltage electrostatic protection structure as described in claim 11, characterized in that, The spacing between the third doped region and the fourth doped region is 0.4 to 2 micrometers.

13. The high-voltage electrostatic protection structure as described in claim 1, characterized in that, The bonding method between the logic wafer and the pixel wafer is hybrid bonding.

14. A method for forming a high-voltage electrostatic protection structure as described in claims 1-13, characterized in that, include: A logic wafer is provided, wherein a first diode structure is disposed in the logic wafer, and the first diode structure is electrically connected under a first threshold voltage; A pixel wafer is provided, wherein a second diode structure is disposed in the pixel wafer and connected in series with the first diode structure, and the second diode structure is electrically connected under a second threshold voltage; The logic wafer and the pixel wafer are bonded together, wherein the first end of the second diode structure is electrically connected to the high-voltage power supply terminal of the d-TOF device, the second end of the second diode structure is electrically connected to the first end of the first diode structure, and the second end of the first diode structure is electrically connected to the ground terminal of the d-TOF device.

15. A d-TOF device, characterized in that, include: High-voltage power supply; A single-photon avalanche diode is connected to the high-voltage power supply. A time-to-digital converter, one end of which is connected to the single-photon avalanche diode, and the other end of which is connected to the detection voltage; The reset circuit is connected at one end to the single-photon avalanche diode and at the other end to the operating voltage; The quenching circuit has one end connected to the single-photon avalanche diode and the other end grounded. According to any one of claims 1-13, in the high-voltage electrostatic protection structure, the first end of the second diode structure is connected to the high-voltage power supply, the second end of the first diode structure is grounded, and when the voltage of the high-voltage power supply is greater than or equal to the sum of the first threshold voltage and the second threshold voltage, the high-voltage electrostatic protection structure is electrically connected to the high-voltage power supply and the grounding terminal.

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