Light sensor

Abstract

Embodiments of the present disclosure relate to a photosensor. A photosensor includes an integrated circuit chip and a boost DC / DC converter. The integrated circuit chip supports an array of pixels, each pixel including a SPAD. The boost DC / DC converter delivers a bias potential to the SPADs, enabling the SPADs to be placed in Geiger mode. The boost DC / DC converter includes an inductive element, a first switch, a second switch, and a circuit that controls the on / off of the first switch. The inductive element and the first and second switches are disposed external to the integrated circuit chip, while the control circuit forms part of the integrated circuit chip.

Description

[0001] priority

[0002] This application claims priority to French Patent Application No. 2200116, filed on 7 January 2022, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic circuits, and more specifically, to optical sensors, such as time-of-flight sensors. Background Technology

[0004] Optical sensors incorporating single-photon avalanche diodes (SPADs) are known. Such sensors, such as time-of-flight sensors, include a pixel array, where each pixel in the array includes at least one SPAD, and are referred to, for example, as SPAD pixels or single-photon avalanche diode pixels. This pixel array is implemented internally and on top of an integrated circuit chip, which is implemented using semiconductor layers. Other circuitry of the sensor, such as pixel driving circuitry and / or pixel readout circuitry, is typically implemented on the same integrated circuit chip as the pixel array.

[0005] As is well known to those skilled in the art, in order to detect a single photon, a SPAD must first be biased at a potential greater than its breakdown voltage. This bias potential is determined so that the electric field in the diode's PN junction is high enough that when the SPAD receives a photon and causes the generation of charge carriers, these charge carriers are injected into the SPAD's depletion region to trigger avalanche phenomena in the SPAD. This operating mode of the diode is referred to in the literature as Geiger mode.

[0006] Various solutions exist for generating this bias potential and delivering it to the SPAD of the sensor pixel array. However, these known solutions all have drawbacks.

[0007] There is a need for a light sensor that includes an integrated circuit chip comprising a SPAD pixel array, wherein the generation of a potential for biasing the SPADs above their breakdown voltage addresses at least some of the drawbacks of known light sensors. Summary of the Invention

[0008] One embodiment overcomes all or part of the disadvantages of known light sensors, such as known light sensors including SPAD pixel arrays.

[0009] One embodiment provides an optical sensor including an integrated circuit chip and a boost DC / DC converter, wherein: the integrated circuit chip includes a pixel array, each pixel including at least one single-photon avalanche diode; the converter is configured to provide a bias potential to the diode of the pixel, the bias potential being capable of placing the diode in Geiger mode; the converter includes: an inductor element coupled to an intermediate node of a node configured to receive a first power supply potential; a first switch coupled to a reference potential; a second switch coupled to an output node of the converter, the output node being configured to deliver the bias potential; and control circuitry configured to control the switching of the first switch, the inductor element of the converter, the first switch, and the second switch being disposed externally to the integrated circuit chip, and the control circuitry forming part of the integrated circuit chip.

[0010] According to one embodiment, the second switch is a diode.

[0011] According to one embodiment, the converter further includes a first capacitor element that couples the output node to a reference potential, the first capacitor element being disposed outside the integrated circuit chip.

[0012] According to one embodiment, the output node of the converter is connected to the input node of the integrated circuit chip.

[0013] According to one embodiment, the input terminals of the integrated circuit chip are coupled to, and preferably connected to, the input of the control circuit.

[0014] According to one embodiment, the chip's input terminal is coupled to the pixel array such that the potential on the input terminal is supplied to each single-photon avalanche diode of the pixel array of the integrated circuit chip.

[0015] According to one embodiment, the bias potential has a target value greater than 15V, preferably greater than or equal to 20V.

[0016] According to one embodiment, the sensor is configured to perform time-of-flight capture functionality.

[0017] According to one embodiment, the control terminal of the first switch of the converter is connected to the output terminal of the integrated circuit chip.

[0018] According to one embodiment, the output of the control circuit is coupled, preferably connected, to the output terminal of the integrated circuit chip.

[0019] According to one embodiment, the converter further includes a second capacitor element, which is coupled to a node configured to receive a first power supply potential to a reference potential, and the second capacitor element is disposed outside the integrated circuit chip.

[0020] According to one embodiment, the integrated circuit chip includes a terminal configured to receive a reference potential.

[0021] According to one embodiment, the converter further includes a resistor connected in series with the inductor between the node configured to receive the first power supply potential and the intermediate node. The resistor is disposed outside the integrated circuit chip, and the chip includes two terminals, each terminal being connected to a different end of the resistor and connected to a control circuit.

[0022] According to one embodiment, the sensor includes a substrate having an integrated circuit chip and a converter assembly disposed outside and assembled thereon. A support includes conductive rails configured to connect the chip and the sensor assembly disposed outside the integrated circuit chip. The converter assembly disposed outside the chip and assembled on the support includes, for example, first and second switches and an inductor element.

[0023] According to one embodiment, the sensor further includes: a protective package assembled on the support; at least one light source assembled on the support; the chip, the inductive element of the converter, the first and second switches of the converter, and the at least one light source are encapsulated in the package, and the sensor forms a plug-and-play module. Attached Figure Description

[0024] The above-described features and advantages, as well as others, will be described in detail below in conjunction with the accompanying drawings, which are given by way of example rather than limitation, in particular, in which:

[0025] Figure 1 An embodiment of the optical sensor is schematically shown at least in part in block form;

[0026] Figure 2 An example of a pixel including a single-photon avalanche diode is shown schematically;

[0027] Figure 3 At least partially illustrated in block form Figure 1 Example of a sensor circuit; and

[0028] Figure 4 At least partially shown schematically in block form. Figure 1 Alternative embodiments of the sensor. Detailed Implementation

[0029] In all figures, the same features are represented by the same reference numerals. Specifically, common structural and / or functional features in various embodiments may have the same references and may be arranged with the same structure, dimensions, and material properties.

[0030] For clarity, only the steps and elements useful for understanding the embodiments described herein are detailed and described. Specifically, not all known SPAD pixels are described, and this description applies to all such known SPAD pixels. Similarly, not all common methods for controlling the switching on / off of a switch-mode power boost converter (“SMPS boost converter”) and the common control circuits for implementing these common control methods are fully described, and this specification applies to these common control methods and these common control circuits.

[0031] In the following description, unless otherwise stated, each potential refers to the same reference potential, such as ground (GND), and the potential of the same node has the same value as the voltage between that node and the reference potential node.

[0032] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except to the outside of the conductor, and when referring to two elements connected together, it means that the two elements can be connected or can be connected by one or more other elements.

[0033] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative position qualifiers, such as “above,” “below,” “above,” “below,” etc., or direction qualifiers, such as “horizontal,” “vertical,” etc., refer to the direction shown in the figure.

[0034] Unless otherwise stated, the order of “approximately,” “roughly,” “basically,” and “about” indicates a percentage of less than 10%, preferably less than 5%.

[0035] Figure 1 An embodiment of the light sensor 1 is schematically shown in block form.

[0036] For example, the light sensor 1 is a time-of-flight sensor that can generate a depth map of the scene captured by the sensor 1.

[0037] The light sensor 1 includes an integrated circuit chip 100. For example, the chip 100 includes a portion of a semiconductor layer made of, for example, silicon, and all electronic components of the chip 100 are formed therein and on top.

[0038] Specifically, the integrated circuit chip 100 includes an array 102 of pixels 104. Figure 1 In the example, array 102 includes seven columns and ten rows of pixels 104, that is, seventy pixels 104. Figure 1A single pixel 104 is used for reference to avoid drawing overload. However, array 102 may include different numbers of columns and / or rows of pixels 104, and therefore include different numbers (e.g., fewer or more) of pixels 104.

[0039] Each pixel (104) includes a single-photon avalanche diode (SPD). Figure 1 (Not shown in the image). In other words, each pixel 102 includes a diode configured to receive a bias potential VHV higher than its breakdown voltage, enabling it to be placed in Geiger mode. For example, in each pixel, the cathode of a single-photon avalanche diode is coupled to the potential VHV, and the anode is coupled to a reference potential, such as ground GND. As an example, the potential VHV of the reference potential GND has a value greater than 15V, preferably greater than or equal to 20V, for example, having a value substantially equal to 25V. As an example, each pixel 102 includes a single-photon avalanche diode. As an alternative example, a pixel may include multiple single-photon avalanche diodes, each of which may be associated with its own quenching circuit, and this component is referred to, for example, as a macropixel.

[0040] Figure 2 An example of pixel 104 that can be implemented in array 102 is illustrated. This example of pixel 104 is similar to that in U.S. Patent No. 11,336,853 (corresponding to EP3806162 and CN112702546). Figure 1 The pixels shown in 5, 6, 7 and 8, are incorporated herein by reference. Figure 2 The example of pixel 104 is more specifically similar to the pixel in Figure 5 of U.S. Patent No. 11,336,853.

[0041] In this example, pixel 104 includes a single-photon avalanche diode 200. The anode of diode 200 is coupled to potential GND, i.e., coupled to node 202 configured to receive potential GND. The cathode of diode 200 is coupled to potential VHV, i.e., coupled to node 204 configured to receive potential VHV.

[0042] More specifically, in this example, the cathode of diode 200 is coupled to node 204 via resistor 205. Resistor 205, referred to as the quench resistor, is configured to quench, i.e., stop, the avalanche phenomenon 200 in the diode. In this example, the anode of diode 200 is coupled to node 202 via two MOS ("Metal-Oxide-Semiconductor") transistors T1 and T2. Transistor T1 is configured, for example, to suppress the avalanche phenomenon in diode 200 when it is switched to the off state. Transistor T2 is configured, for example, to deactivate pixel 104 when it is switched to the off state.

[0043] In this example, pixel 104 also includes a pull-up diode 206, whose anode is connected to the anode of diode 200 and whose cathode is connected to node 208 configured to receive potential V2. Potential V2 is less than potential VHV. For example, potential V2 is approximately 7V.

[0044] In this example, pixel 104 also includes two capacitor elements C1 and C2. Capacitor element C1 is connected between node 210 and node 212, which connects diode 200 to resistor 205. Capacitor element C2 is connected between node 212 and node 202. Capacitor elements C1 and C2 form a capacitive voltage divider bridge and are configured to repeat or transmit changes in the cathode of diode 200 at node 212.

[0045] In this example, pixel 104 also includes circuitry 216, which is an inverter configured to switch its output in response to potential changes at node 212 caused by avalanche phenomena in diode 200. In other words, circuitry 216 is configured to detect avalanche phenomena in diode 200.

[0046] In this example, pixel 104 also includes an optional MOS transistor T3. Transistor T3 couples node 212 to node 214, which is configured to receive a potential V1. Potential V1 is less than potential VHV. Potential V1 is, for example, a power supply potential of approximately 1.2V. The potential received by the gate of transistor T3 can modify the duration of the pulse provided at the output of circuit 216.

[0047] Those skilled in the art can provide with Figure 2 Different single-photon avalanche diodes have 104 pixels, such as Figure 2 As shown, a single-photon avalanche diode, for example, receives a potential VHV on its cathode to be able to be placed in Geiger mode. In other words, what will be within the capabilities of those skilled in the art is to provide something different from... Figure 2 The single-photon avalanche diode pixel 104 requires its own receiving potential VHV to operate.

[0048] Refer again Figure 1 Sensor 1 also includes a switch-mode boost converter 106 (in Figure 1 (The middle part is defined by a dashed line).

[0049] Converter 106 is configured to deliver a potential VHV to a single-photon avalanche diode of array 102 of pixel 104. More specifically, converter 106 is configured to deliver potential VHV from a power supply potential Vbat. Potentials Vbat and VHV are DC ("direct current") potentials. In other words, converter 106 is a DC / DC converter.

[0050] For example, the potential Vbat is smaller than the potential VHV, for example, at least 10V smaller. As an example, the potential Vbat is less than or equal to 5V, for example, approximately equal to 3.6V.

[0051] The converter 106 includes an inductor 110, a switch 112, a diode 114, and a control circuit CTRL configured to control the switching of the switch 112.

[0052] Inductor 110 is coupled to node 116, which is configured to receive potential Vbat, to intermediate node 118. In other words, one terminal of inductor 110 is coupled, for example, to node 116, and the other terminal of inductor 110 is coupled, for example, to node 118.

[0053] Switch 112 couples node 118 to a reference potential GND; that is, switch 112 couples node 118 to node 122, which is configured to receive the reference potential GND. This switch 112 is, for example, referred to as a low-side switch. For example, switch 112 includes a conductive terminal coupled, for example, to node 118, and another conductive terminal coupled, for example, to node 122. Switch 112 receives a control signal sigCTRL on a control terminal.

[0054] For example, switch 112 is implemented using an N-channel MOS transistor. For example, a first conductive terminal of transistor 112, such as drain-coupled, is preferably connected to node 118, and a second conductive terminal of transistor 112, such as source-coupled, is preferably connected to node 122. The gate of transistor 112 receives the signal sigCTRL. Preferably, when the signal sigCTRL switches to a high potential equal to the power supply voltage of chip 100, this is sufficient to switch transistor 112 to the on state. Therefore, switch 112 is controlled by a signal, here a voltage, the maximum value of which is less than or equal to the power supply voltage of chip 100.

[0055] Diode 114 couples intermediate node 118 to output node 124 of converter 106. Node 124 is configured to supply potential VHV. In other words, converter 106 supplies potential VHV at its output node 124. The first electrode of diode 114, here its anode coupled, is preferably connected to node 118, and the second electrode, here its cathode coupled, is preferably connected to node 124. In effect, diode 114 performs a switching function. In other words, diode 114 is a switch (uncontrollable), referred to as a high-side switch. As an example, diode 114 is a Schottky diode.

[0056] The circuit CTRL is used to control switch 112, that is, to control the on / off state of switch 112, so that the potential VHV is maintained at the target value Vtarget. The target value Vtarget is, for example, greater than 15V, preferably greater than or equal to 20V, and for example, substantially equal to 25V.

[0057] For this purpose, the circuit CTRL is configured to receive a signal representing a potential VHV, such as the actual potential VHV. Furthermore, the circuit CTRL is configured to supply a control signal sigCTRL to the switch 112. As an example, the circuit CTRL is configured to control the switch 112 in pulse width modulation (PWM).

[0058] The circuit CTRL forms part of chip 100. In contrast, the inductor 110, switch 112, and diode 114 are arranged outside chip 100, meaning they do not form part of chip 100. In particular, node 118 is outside chip 100.

[0059] Therefore, the circuit CTRL includes terminals, or nodes, or inputs 126, which are configured to receive a signal representing a potential VHV, more specifically, Figure 1 The example shows the potential VHV. Terminal 126 of the circuit CTRL is coupled, preferably connected to the input terminal 128 of the chip 100. Terminal 128 is configured to receive the potential VHV.

[0060] Although this is in Figure 1 While not described in detail, preferably, terminal 126 of circuit CTRL corresponds, for example, to one end of a voltage divider bridge, such as a resistive voltage divider bridge, configured to divide the value of potential VHV to obtain a potential representing potential VHV but having a value compatible with the maximum voltage that the transistors of chip 100 can withstand. For example, this potential representing potential VHV has a value less than the maximum value of the power supply potential AVDD of chip 100. For example, the voltage divider bridge forms part of circuit CTRL and thus part of chip 100.

[0061] More generally, instead of a voltage divider bridge, the circuit CTRL can include any ordinary circuit configured to supply a potential that represents a potential VHV, and has a maximum value less than the maximum value that is absorbed by the MOS transistors of chip 100.

[0062] Terminal 128 is further coupled, preferably connected, to an array 102 of pixels 104 of chip 100, such that a potential VHV on terminal 128 is supplied to array 102, more specifically to each pixel 104 of array 102, and more specifically to each single-photon avalanche diode of array 102. Therefore, each single-photon avalanche diode of array 102 (e.g., as shown in the image) Figure 2As in the example, the potential VH is received on its cathode. For example, for a potential VHV, that is, a target value Vtarget of approximately 25V, the current drawn by array 102 on node 124 is approximately 30mA in steady-state operation and may reach, for example, at least 45mA during instantaneous current inrush.

[0063] Furthermore, the circuit CTRL includes a terminal, node, or output 130 configured to supply a control signal sigCTRL. Terminal 130 is coupled to, and preferably connected to, an output terminal 132 of chip 100. Output terminal 132 is configured to supply the signal sigCTRL to a switch 112 disposed outside chip 100. Terminal 132 is connected to a control terminal of switch 112.

[0064] As an example, chip 100 is powered by a potential AVDD, and chip 100 thus includes a terminal 120 configured to receive the potential AVDD and a terminal 121 configured to receive a reference potential GND. As an example, the power supply potential AVDD of chip 100 has a value substantially equal to 3.6V.

[0065] As an example, the circuit CTRL is also powered by the potential AVDD, and then includes a terminal or node 134 configured to receive a reference potential GND and a terminal 135 configured to receive the potential AVDD. As an example, terminal 134 is coupled, preferably connected to an input terminal 121 of chip 100. As an example, terminal 135 is coupled, preferably connected to an input terminal 120 of the chip.

[0066] Typically, for a switch-mode boost converter, converter 1 includes a capacitor element Cout that couples nodes 124 and 122 together. For example, capacitor element Cout includes a first electrode coupled to, preferably, node 124 and a second electrode coupled to, preferably, node 122.

[0067] As an example, converter 1 also includes a capacitor element Cin that couples node 116 to node 122. For example, capacitor element Cin includes a first electrode coupled to, preferably, node 124 and a second electrode coupled to, preferably, node 122. For example, capacitor element Cin can be omitted when the impedance between the voltage source at the supply potential Vbat and node 116 is low enough that the voltage drop at node 116 during the current draw by converter 106 at node 116 can be neglected.

[0068] According to one embodiment, at least the inductor 110, switch 112 and diode 114 of the converter 306 are arranged outside the chip 100, and at least the control circuit CTRL of the converter 106 is formed as part of the chip 100.

[0069] Although not shown, chip 100 includes a number of MOS transistors, such as in the control and readout circuitry of pixel 104 in array 102. These transistors are not intended for power applications and therefore cannot withstand high voltages, such as the voltage applied across each single-photon avalanche diode in array 102 to put that diode into Geiger mode. For example, most of the MOS transistors in chip 100 are configured to withstand voltages less than Vbat. As an example, some transistors in chip 100 are configured to withstand a maximum voltage greater than Vbat, while others are standard low-voltage transistors, such as those configured to withstand voltages less than or equal to AVDD between their terminals.

[0070] According to one embodiment, components of the chip 100 and converter 106 outside the chip 100, namely the inductor 110, switch 112, diode 114, and (if present) capacitors Cin and Cout, are assembled on a support or substrate 140. The support 140 forms part of the sensor 1. According to an alternative embodiment, the capacitors Cin and / or Cout may be arranged outside the sensor 1.

[0071] As an example, sensor 1, and more specifically its support 140, includes an input terminal 108 configured to receive a potential Vbat. For example, the potential Vbat is supplied to sensor 1 by circuitry outside of sensor 1.

[0072] As an example, sensor 1, and more specifically its support 140, includes an input terminal 109 configured to receive a potential AVDD. For example, the potential AVDD is supplied to sensor 1 by circuitry outside of sensor 1.

[0073] As an alternative example, the potentials AVDD and Vbat are the same, and terminal 108 is connected directly to terminal 109, for example.

[0074] As another alternative example, sensor 1 receives only one of potentials AVDD and Vbat from the outside, such as potential Vbat, and includes circuitry configured to supply the other of potentials AVDD and Vbat, such as potential AVDD, based on the potential received by sensor 1.

[0075] Although this is in Figure 1 The details are not specified, but the support 140 includes conductive tracks to enable the previously described coupling or connection between the chips 100, and more specifically, the coupling or connection between the input and output terminals of the chips 100 and the components of the converter 106 arranged outside the chips 100.

[0076] Although this is in Figure 1Not shown, but when sensor 1 is a time-of-flight sensor, sensor 1 may further include one or more light sources, such as one or more vertical-cavity surface-emitting laser (VCSEL) diodes, and circuitry (“drivers”) driving these light sources. The light sources and driving circuitry are configured to emit light signals toward the scene, and array 102 is configured to receive corresponding signals reflected by the scene. The light sources and driving circuitry are preferably discrete components mounted on support 140. Other discrete components of sensor 1 may also be mounted on support 140. Furthermore, sensor 1 includes, for example, a protective package mounted on or assembled with support 140. The package includes an opening opposite the array 102 of pixels 104 and an opening opposite the light source. All components of the chip of sensor 1 mounted on support 140 are then encapsulated in this package. In other words, sensor 1 thus forms a plug-and-play module that only requires power supply, for example, by supplying potentials Vbat and AVDD to terminals 108 and 109 of support 140, to enable sensor 1 to operate. As an example, the support 140 is then configured to be assembled onto the motherboard of a complex electronic system, such as a smartphone, for example, onto a printed circuit board (PCB) or a flexible printed circuit board (“FlexPCB”).

[0077] The components of the converter 106, which are arranged outside the chip 100, are common components and readily available.

[0078] Instead of integrating the circuitry CTRL into the chip 100 of sensor 1, that is, into the chip 100 that includes the pixel 104 of sensor 1, a switch-mode boost converter that is entirely located outside the chip can be designed as a discrete component to be assembled on support 140. However, this would increase the size of support 140 and thus the volume of sensor 1, for example, when sensor 1 is a plug-and-play module.

[0079] Alternatively, the converter 106 can be designed to supply the potential VHV directly to the sensor 1 by placing it entirely outside the sensor 1; that is, the converter 106 is not mounted on the same support 140 as the chip 100. However, this increases the distance between the converter supplying the potential VHV and the sensor 1, which will lead to increased losses and / or increased converter response time, and / or reduced control accuracy of the potential VHV value.

[0080] Furthermore, a charge pump fully integrated into chip 100 could be designed instead of partially arranging the converter 106 of sensor 1 within and partially outside chip 100. However, such a charge pump would be significantly less efficient than that of converter 106, and would occupy a much larger surface area than the circuit CTRL. For example, considering a charge pump with approximately 25% efficiency, supplying a maximum current of approximately 45mA at the output terminal of the charge pump for a potential VHV essentially equal to 25V, i.e., supplying approximately 1W at the output terminal, would require a supply voltage of Vbat capable of delivering more than 4W of power. This power consumption is excessive compared to the power consumption of a switch-mode DC / DC converter that would have to supply the same output power. For example, the high power consumption associated with using a charge pump could adversely affect the autonomy of battery-powered moving objects.

[0081] It would have been possible to design and integrate switch 112 into chip 100. However, switch 112 experiences voltages ranging up to a potential of VHV between its terminals, and chip 100, and in particular its MOS transistors that could be conceived to implement switch 112, is not provided to withstand such voltages.

[0082] Furthermore, providing a circuit CTRL integrated with chip 100 allows for finer control over the value of the potential VHV, i.e., the target value Vtarget, even if this circuit CTRL is located externally to chip 100. This is essential for the proper operation of the single-photon avalanche diodes in array 102. For example, the circuit CTRL can be configured to modify the value Vtarget based on the operating conditions of chip 100, such as the temperature of chip 100, and therefore the single-photon avalanche diode.

[0083] More generally, if converter 106 were replaced by a charge pump integrated into chip 100 or by a switch-mode boost converter that is entirely external to the chip, compared to this, such as regarding Figure 1 The implementation of the converter 106 of the described sensor 1 allows for better conversion efficiency and better regulation efficiency of the potential VHV with a smaller size.

[0084] In an alternative embodiment (not shown), the high-side switch of converter 106 is implemented by a controllable switch instead of a diode 114 corresponding to an uncontrollable switch. The controllable switch, replacing diode 14, is then controlled by a circuit CTRL. This high-side controllable switch is, for example, a P-channel MOS transistor. In this case, the control signal for the high-side PMOS transistor, typically the control voltage, has a value much larger than the value that the circuitry of chip 100 can deliver and / or withstand. A level shifter circuit is then provided for the high-side transistor, which is capable of supplying a control voltage suitable for the high-side transistor based on the control signal provided by the circuit CTRL. The level shifter circuit and the high-side transistor are then assembled on support 140 as one or more discrete components.

[0085] The advantage of using a diode 114 instead of a MOS transistor to implement the high-voltage side switch of converter 106 is that it is simpler and smaller in size.

[0086] Figure 3 Partially illustrated in block form Figure 1 A more detailed example of the CTRL circuitry for the sensor is provided. In this example, the CTRL circuitry implements PWM control of the on / off state of switch 112. Figure 3 Terminal 135 of the CTRL circuit is not shown in the diagram.

[0087] exist Figure 3 In the example, the circuit CTRL includes a resistive voltage divider bridge 300 connected between inputs (or terminals) 126 and 134 of the circuit CTRL. The voltage divider bridge 300 is configured to divide the value of potential VHV and supply the divided value Vfb at node 302. In other words, the voltage divider bridge 300 receives potential VHV and provides potential Vfb from potential VHV, where potential Vfb represents potential VHV and is less than potential VHV. Preferably, voltage Vfb is less than the maximum voltage that components of chip 100, particularly transistors, can withstand. For example, voltage Vfb is less than voltage Vbat, and preferably less than voltage AVDD.

[0088] As an example, the voltage divider bridge 300 includes a resistor R1 connected between nodes 126 and 302, and a resistor R2 connected between nodes 302 and 134.

[0089] The circuit CTRL also includes circuit 306. Circuit 306 is configured to provide a signal err representing the difference, or error, between voltage Vfb and voltage Vref. The voltage value Vref is determined by the value Vtarget. Therefore, the signal err represents the difference, or error, between the potential VHV and its target value. Circuit 306 is configured to receive signals Vfb and Vref, and supply signal err. As an example, circuit 306 implements a proportional-integral-derivative (PID) filter function. As an example, circuit 306 includes an operational amplifier assembled as an error amplifier, the common passive components of which are not present in... Figure 3 The diagram is shown to avoid drawing overload. As an example, signal Vref is received by an input of circuit 306, such as the non-inverting input (+) of an operational amplifier, signal Vfb is received by another input of circuit 306, such as the inverting input (-) of an operational amplifier, and signal err is available at the output of circuit 206, such as the output of an operational amplifier.

[0090] The circuit CTRL also includes circuit 308. Circuit 308 is configured to provide a periodic sawtooth signal sig1. In this example, the frequency of signal sig1 corresponds to the switching frequency of switch 112 (see [link to relevant documentation]). Figure 1 For example, approximately 10MHz.

[0091] The circuit CTRL also includes circuit 310, which is configured to compare signal sig1 with signal err and provide a binary signal cmp, the binary state of which indicates the result of the comparison. For example, when signal err is less than signal sig1, signal cmp is in a first binary state, and when signal err is greater than signal sig1, signal cmp is in a second binary state. Therefore, the width of each pulse of signal cmp is modulated according to the value of potential VHV.

[0092] like Figure 3 As shown, the circuit CTRL may include circuit 312, which is configured to supply signal sigCTRL based on signal cmp. Circuit 312 is configured to shape signal cmp to generate signal sigCTRL. As an example, circuit 312 is a buffer circuit. As an example, each switching of signal cmp causes a corresponding switching of signal sigCTRL, and each switching of signal sigCTRL is caused by a corresponding switching of signal cmp.

[0093] According to another example not shown, circuit 312 can be omitted.

[0094] Although the above, especially regarding Figure 3 The circuit CTRL has been described as being configured to control switch 112 with PWM. Figure 1This description is not limited to this control example. In practice, as an alternative example, the circuit CTRL can implement pulse frequency modulation (PFM) control or hysteresis control. In yet another example, the circuit CTRL can be configured to switch between at least two control modes of switch 112, for example, switching between PWM control and PFM control, the switching between these different control modes being determined, for example, by the power drawn by chip 100 at node 124 (see...). Figure 1 ).

[0095] For example, in an embodiment, the circuit CTRL may need to know the current in the inductor, such as whether the current is equal to zero, in order to generate the signal sigCTRL.

[0096] In this case, converter 106 may include circuitry configured to determine the current in inductor 110, for example, circuitry configured to detect when the current in inductor 110 becomes zero.

[0097] Figure 4 At least partially illustrated in block form Figure 1 Alternative embodiments of sensor 1 are shown here. Only those highlighted are shown. Figure 1 Converter 1 and Figure 4 The difference between converter 1 and converter 2.

[0098] In this variant, the circuit CTRL is configured to generate a signal sigCTRL that is not based solely on the value of the potential VHV, i.e., the difference between the available potential VHV on node 124 and the target value Vtarget of potential VHV, but also on the value of the current IL in the inductor 110, for example, based on detecting that the current IL in the inductor has become zero.

[0099] Therefore, with Figure 1 Compared to converter 106, Figure 4 The converter 106 includes a resistor Rs, for example, called a shunt resistor.

[0100] Between nodes 118 and 116, the resistor Rs and the inductor 110 are connected in series.

[0101] For example in Figure 4 In this configuration, one end or terminal of resistor Rs is connected to node 116, and the other end or terminal is connected to one electrode of inductor 110, with the other electrode of inductor 110 connected to node 118. As an alternative example (not shown), one end or terminal of resistor Rs is connected to node 118, and the other end or terminal is connected to one electrode of inductor 110, with the other electrode of inductor 110 connected to node 116.

[0102] Preferably, resistor Rs is connected to one side of node 116 such that the voltage across resistor Rs is less than or equal to the maximum voltage that the transistor of chip 100 can withstand.

[0103] Electrical components Rs, along with components 110, 112, and 114, and (if present) capacitor components Cin and Cout, are arranged outside chip 100.

[0104] The circuit CTRL includes two terminals (or nodes or inputs) 402 and 406, each configured to receive a voltage across one of the terminals of the resistor Rs. Therefore, the chip 100 includes two terminals (or inputs) 400 and 408, each connected to a different end (or terminal) of the resistor Rs and connected to the control circuitry.

[0105] exist Figure 4 In the example, terminal 408 of chip 100 is connected to the first end of resistor Rs, i.e., node 116 in this example, and terminal 400 of chip 100 is connected to the second end of resistor Rs, i.e., node 404 connecting inductor 110 and resistor Rs in this example. Furthermore, terminal 408 of chip 100 is connected to terminal 406 of circuit CTRL, and terminal 400 of chip 100 is connected to terminal 402 of circuit CTRL.

[0106] Those skilled in the art can make the above regarding Figure 4 The description applies to cases where potentials AVDD and Vbat are the same and / or to cases where resistor Rs has a terminal connected to node 118.

[0107] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will occur to them. In particular, those skilled in the art can provide other embodiments of a switch-mode boost converter having its low-side switch, its high-side switch, preferably a diode, and an inductive element disposed outside an integrated circuit chip containing a pixel array, each pixel comprising a single-photon avalanche diode, and the converter having control circuitry integrated with the chip for the low-side switch, or in other words, a voltage and / or current feedback loop for the converter. In this case, according to one embodiment, for example when the sensor forms a plug-and-play module, the high-side and low-side switches of the converter, i.e., the converter's chopper switch, inductive element, and measuring resistor (if present), are assembled on the same support as the chip.

[0108] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. A light sensor, comprising: An integrated circuit chip includes a pixel array comprising a plurality of pixels, each of the plurality of pixels including a single-photon avalanche diode; and A boost DC / DC converter is configured to deliver a bias potential to the single-photon avalanche diode of each pixel, wherein the bias potential is configured to place each single-photon avalanche diode in Geiger mode. The boost DC / DC converter mentioned above includes: The inductor element will be coupled to the intermediate node at the node configured to receive the first power supply potential; The first switch couples the intermediate node to a reference potential; A second switch couples the intermediate node to the output node, the output node being configured to deliver the bias potential; and The control circuit is configured to control the switching of the first switch; The inductor, the first switch, and the second switch of the boost DC / DC converter are all arranged outside the integrated circuit chip, and The control circuit described therein forms part of the integrated circuit chip.

2. The optical sensor according to claim 1, wherein the second switch is a diode.

3. The optical sensor according to claim 1, wherein the boost DC / DC converter further comprises a first capacitor element, the first capacitor element coupling the output node to the reference potential, the first capacitor element being disposed outside the integrated circuit chip.

4. The optical sensor according to claim 1, wherein the output node is connected to the input terminal of the integrated circuit chip.

5. The optical sensor according to claim 4, wherein the input terminal of the integrated circuit chip is coupled to the input of the control circuit.

6. The optical sensor of claim 4, wherein the input terminal of the integrated circuit chip is coupled to the pixel array such that a potential of the input terminal is supplied to each single-photon avalanche diode of the pixel array of the integrated circuit chip.

7. The optical sensor according to claim 1, wherein the bias potential has a target value greater than 15V.

8. The optical sensor according to claim 1, wherein the bias potential has a target value greater than or equal to 20V.

9. The optical sensor of claim 1, configured to perform time-of-flight capture function.

10. The optical sensor according to claim 1, wherein the control terminal of the first switch of the boost DC / DC converter is connected to the output terminal of the integrated circuit chip.

11. The optical sensor of claim 10, wherein the output of the control circuit is coupled to the output terminal of the integrated circuit chip.

12. The optical sensor of claim 1, wherein the boost DC / DC converter further comprises a second capacitor element, the second capacitor element being coupled to the reference potential at a node configured to receive the first power supply potential, the second capacitor element being disposed outside the integrated circuit chip.

13. The optical sensor of claim 1, wherein the integrated circuit chip includes a terminal configured to receive the reference potential.

14. The optical sensor of claim 1, wherein the boost DC / DC converter further comprises a resistor connected in series with the inductor between the node configured to receive the first power supply potential and the intermediate node, the resistor being disposed outside the integrated circuit chip, and wherein the integrated circuit chip comprises two terminals connected to different ends of the resistor and connected to the control circuit.

15. The optical sensor of claim 1, further comprising a substrate support having an assembly of the integrated circuit chip and the boost DC / DC converter, the assembly being disposed outside the integrated circuit chip and assembled on the integrated circuit chip, the substrate support including conductive rails configured to electrically connect the integrated circuit chip and the assembly of the boost DC / DC converter disposed outside the integrated circuit chip.

16. The optical sensor according to claim 15, further comprising: The protective package is assembled on the substrate support; and At least one light source is assembled on the substrate support; The integrated circuit chip, the inductor of the boost DC / DC converter, the first switch and the second switch of the boost DC / DC converter, and the at least one light source are encapsulated in the protective package, and the light sensor forms a plug-and-play module.

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