Electrostatic discharge protection circuit

Abstract

An electrostatic discharge protection circuit is disclosed. The electrostatic discharge protection circuit is coupled to a bond pad and includes a buffer circuit, a driver circuit, and a power clamp circuit. The buffer circuit includes first and second transistors of a first conductivity type coupled in series between a first node and a first power supply node. The bond pad is coupled to the first node. The driver circuit determines a state of at least one of the first and second transistors based on a control voltage. The driver circuit includes a third transistor of a second conductivity type coupled between a second power supply node and a gate of the first transistor and controlled by the control voltage. The power clamp circuit is coupled to the bond pad through the first node and couples a gate of the third transistor to a second node. The control voltage is generated at the second node. The power clamp circuit determines a level of the control voltage based on a voltage on the bond pad. The electrostatic discharge protection circuit of the present embodiments has high voltage tolerance.

Description

Technical Field

[0001] This invention relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection circuit with high voltage tolerance. Background Technology

[0002] With the development of semiconductor technology for integrated circuits, the size of semiconductor devices has shrunk to the sub-micron level to improve the performance and processing speed of integrated circuits. However, this reduction in device size has brought about some reliability issues, particularly affecting the protection capability of integrated circuits against electrostatic discharge (ESD). Generally, the bonding pads used for output and input can be coupled to buffer circuits with high voltage tolerance. When an ESD event occurs on the bonding pad, the ESD current can be conducted to ground through an N-type metal-oxide-semiconductor transistor connected in series in the buffer circuit, thereby preventing damage to the components coupled to the bonding pad from ESD. Therefore, the ESD capability of the buffer circuit is crucial. Summary of the Invention

[0003] In view of this, the present invention proposes an electrostatic discharge (ESD) protection circuit. The ESD protection circuit is coupled to a bonding pad and includes a buffer circuit, a drive circuit, and a power clamping circuit. The buffer circuit includes a first transistor and a second transistor, both having a first conductivity type, connected in series between a first node and a first power node. The bonding pad is coupled to the first node. The drive circuit receives a first control voltage and determines the state of at least one of the first and second transistors based on the first control voltage. The drive circuit includes a third transistor having a second conductivity type. The third transistor is coupled between a second power node and the gate of the first transistor and is controlled by the first control voltage. The power clamping circuit is coupled to the bonding pad through the first node and to the gate of the third transistor at the second node. The first control voltage is generated at the second node. The power clamping circuit determines the level of the first control voltage based on the voltage on the bonding pad.

[0004] The present invention further proposes an electrostatic discharge (ESD) protection circuit. This ESD protection circuit is coupled to a bonding pad and includes a buffer circuit, a drive circuit, and a power clamping circuit. The buffer circuit includes a first transistor and a second transistor having a first conductivity type. The first transistor is coupled between a first node and a second node. The bonding pad is coupled to the first node. The second transistor is coupled between the second node and a first power node. The drive circuit receives a first control voltage and determines the state of at least one of the first transistor and the second transistor based on the first control voltage. The power clamping circuit is coupled to the bonding pad through the first node and to the drive circuit at a third node. The first control voltage is generated at the third node, and the power clamping circuit determines the level of the first control voltage based on the voltage on the bonding pad. When an ESD event occurs on the bonding pad, the drive circuit turns off the first transistor based on the first control voltage.

[0005] The electrostatic discharge protection circuit of this invention has high voltage tolerance and can prevent components coupled to the bonding pad from being damaged by electrostatic discharge. Attached Figure Description

[0006] Figure 1 This describes an electrostatic discharge protection circuit according to an embodiment of the present invention.

[0007] Figure 2A express Figure 1 A schematic diagram of the electrostatic discharge protection circuit in input mode.

[0008] Figure 2B This indicates that according to an embodiment of the present invention, Figure 1 A schematic diagram of the main voltage or signal levels of the electrostatic discharge protection circuit in input mode.

[0009] Figure 2C According to another embodiment of the present invention, Figure 1 A schematic diagram of the main voltage or signal levels of the electrostatic discharge protection circuit in input mode.

[0010] Figure 3A express Figure 1 A schematic diagram of the electrostatic discharge protection circuit in output mode.

[0011] Figure 3B express Figure 1 A schematic diagram of the main voltage or signal levels of the electrostatic discharge protection circuit in output mode.

[0012] Figure 4A This indicates when an electrostatic discharge event occurs on the bonding pad. Figure 1 A schematic diagram of the operation of the electrostatic discharge protection circuit.

[0013] Figure 4Bexpress Figure 1 A schematic diagram of the main voltage or signal levels of an electrostatic discharge protection circuit when encountering an electrostatic discharge event.

[0014] Figure 5 This describes an electrostatic discharge protection circuit according to another embodiment of the present invention.

[0015] Figure 6 This describes an electrostatic discharge protection circuit according to another embodiment of the present invention.

[0016] Figure 7 This describes an electrostatic discharge protection circuit according to another embodiment of the present invention.

[0017] Figure Labels

[0018] 1, 5, 6, 7: Electrostatic discharge protection circuit

[0019] 10: Buffer circuit

[0020] 11: Drive circuit

[0021] 12: Power clamping circuit

[0022] 13: Joining pad

[0023] 14: Core Circuit

[0024] 15: Diode

[0025] 110: Step-down circuit

[0026] 120: Inverter

[0027] C10: Capacitor

[0028] N10, N11, N112, N13, N14, N15: NMOS transistors

[0029] ND10, ND11, ND12, ND13, ND15, ND16: Nodes

[0030] ND14: Common Node

[0031] ND17, ND18: Power nodes

[0032] P10, P11, P12, P13: PMOS transistors

[0033] R10: Resistor

[0034] SI13: Input signal

[0035] SO13: Output signal

[0036] T10, T11: Control terminals

[0037] V13, V14, V15, V17: Voltage

[0038] VCC, VSS: Operating voltage

[0039] VS10, VS11: Signal voltage Detailed Implementation

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, a preferred embodiment is described below in detail with reference to the accompanying drawings.

[0041] Figure 1 This describes an electrostatic discharge protection circuit according to an embodiment of the present invention. (See also...) Figure 1 In order to explain in detail, Figure 1 In addition to showing the electrostatic discharge protection circuit 1, the bonding pad 13 and the core circuit 14 are also shown. (Example) Figure 1 As shown, the electrostatic discharge (ESD) protection circuit 1 has two power supply nodes ND17 and ND18, and is coupled to a bonding pad 13 at node ND10. The ESD protection circuit 1 is coupled to the core circuit 14 via the bonding pad 13. In one embodiment, when the core circuit 14 is operating under normal conditions, power supply node ND17 receives one operating voltage and power supply node ND18 receives another operating voltage; when an ESD event occurs on the bonding pad 13, power supply nodes ND17 and ND18 do not receive any operating voltage. In another embodiment, power supply node ND18 is coupled to ground; therefore, the operating voltage received by power supply node ND18 is the ground voltage, for example, 0 volts (V). The operation of the ESD protection circuit 1 will be described below with reference to the figures.

[0042] The electrostatic discharge protection circuit 1 includes a buffer circuit 10, a drive circuit 11, and a power clamping circuit 12. The buffer circuit 10 includes a metal-oxide-semiconductor (MOS) transistor N10, a MOS transistor N11, and a MOS transistor P10. In this embodiment, the MOS transistors N10 and N11 are N-type (first conductivity type), while the MOS transistor P10 is P-type (second conductivity type). In this specification, the N-type MOS transistor (i.e., the MOS transistor with the first conductivity type) is simply referred to as an NMOS transistor, and the P-type MOS transistor (i.e., the MOS transistor with the second conductivity type) is simply referred to as a PMOS transistor. See also... Figure 1The source of PMOS transistor P10 is coupled to power node ND17, its drain is coupled to node ND10, and its gate is coupled to control terminal T10. The drain of NMOS transistor N10 is coupled to node ND10, its source is coupled to node ND16, and its gate is coupled to node ND12. The drain of NMOS transistor N11 is coupled to node ND16, its source is coupled to power node ND18, and its gate is coupled to control terminal T11. When the core circuit 14 operates in normal operating condition, the gate of PMOS transistor P10 receives a signal voltage through control terminal T10, and the gate of NMOS transistor N11 receives another signal voltage through control terminal T11.

[0043] like Figure 1 As shown, the driving circuit 11 includes a buck circuit 110, PMOS transistors P11 and P12, and NMOS transistors N12 and NMOS transistors N13. The buck circuit 110 is coupled between the bonding pad 13 and the node ND13. The buck circuit 110 provides an regulated voltage, thereby reducing the voltage on the bonding pad 13 so that the voltage on the node ND13 is less than the voltage on the bonding pad 13. The buck circuit 110 includes a plurality of buck elements cascaded between the bonding pad 13 and the node ND13. In this embodiment, the buck circuit 110 includes a plurality of diodes 15 cascaded between the bonding pad 13 and the node ND13. The actual number of diodes 15 can be adjusted according to actual needs, and the invention is not limited thereto. In the series of diodes 15 connected in sequence from the junction pad 13 to the node ND13, the anode of the first diode 15 is coupled to the junction pad 13, the anode of each of the remaining diodes 15 is coupled to the cathode of the preceding diode 15, and the cathode of the last diode 15 is coupled to the node ND13. The magnitude of the regulated voltage depends on the number of diodes 15.

[0044] The source of PMOS transistor P12 is coupled to node ND13, its drain is coupled to power clamp circuit 12 at node ND15, and its gate is coupled to power clamp circuit 12 at the common node ND14. The source of PMOS transistor P11 is coupled to power node ND17, its drain is coupled to the gate of NMOS transistor N10 at node ND12, and its gate is coupled to power clamp circuit 12 at node ND15. The drain of NMOS transistor N13 is coupled to the gate of NMOS transistor N10 at node ND12, its source is coupled to power node ND18, and its gate is coupled to power clamp circuit 12 at node ND15. The drain of NMOS transistor N12 is coupled to the gate of NMOS transistor N11 and the control terminal T11 at node ND11, its source is coupled to power node ND18, and its gate is coupled to power clamp circuit 12 at node ND15.

[0045] See Figure 1 The power supply clamping circuit 12 includes a resistor R10, a capacitor C10, a PMOS transistor P13 as a pull-up transistor, an NMOS transistor N14 as a pull-down transistor, and an NMOS transistor N15. Resistor R10 is coupled between power node ND17 and common node ND14, and capacitor C10 is coupled between common node ND14 and power node ND18. The source of PMOS transistor P13 is coupled to power node ND17, its drain is coupled to node ND15, and its gate is coupled to common node ND14. The drain of NMOS transistor N14 is coupled to node ND15, its source is coupled to power node ND18, and its gate is coupled to common node ND14. Based on the connection architecture of PMOS transistor P13 and NMOS transistor N14, PMOS transistor P13 and NMOS transistor N14 form an inverter 120. The drain of NMOS transistor N15 is coupled to power node ND17, its source is coupled to power node ND18, and its gate is coupled to node ND15.

[0046] According to an embodiment of this application, the power clamping circuit 12 is coupled to the PMOS transistor P10 via power node ND17 and connected to the bonding pad 13. The power clamping circuit 12 generates at least one control voltage based on the voltage on the bonding pad 13, and the drive circuit 11 determines the on or off state of at least one of the NMOS transistors N10 and NMOS transistor N11 based on this at least one control voltage. Specifically, during periods when the core circuit 14 is not operating under normal conditions, when an electrostatic discharge event occurs on the bonding pad 13, the drive circuit 11 turns off at least one of the NMOS transistors N10 and NMOS transistor N11 based on this at least one control voltage. For detailed operation of the electrostatic discharge protection circuit 1, please refer to the following and related figures.

[0047] When the core circuit 14 operates in normal operating condition, power node ND17 receives the operating voltage VCC, and power node ND18 receives the operating voltage VSS or is coupled to ground. In this embodiment, the level of the operating voltage VSS is lower than the level of the operating voltage VCC. For example, the operating voltage VCC is 3.3V, while the operating voltage VSS is 0V, or power node ND18 is coupled to ground. When power node ND18 is coupled to ground, the operating voltage VSS is considered to be the ground voltage (0V). In normal operating condition, the core circuit 14 can be in input mode or output mode. Figure 2AThis is a schematic diagram illustrating the operation of the electrostatic discharge protection circuit 1 in input mode. In input mode, the contact pad 13 receives the input signal SI13, the signal voltage VS10 is provided to the control terminal T10, and the signal voltage VS11, which is equal to 0V, is also provided to the control terminal T11. For example, the signal voltages VS10 and VS11 are provided by the core circuit 14; however, the invention is not limited thereto. In one embodiment, the signal voltages VS10 and VS11 can be provided by different circuits. Assuming that the core circuit 14 is composed of components with a withstand voltage of 5V, during input mode, the level of the input signal SI13 is in the range of 0V to 3.3V or in the range of 0V to 5V, and the signal voltage VS10 is 3.3V or 5V. Specifically, in input mode, the level of the input signal SI13 is in the range of 0V to 3.3V and the signal voltage VS10 is 3.3V, or the level of the input signal SI13 is in the range of 0V to 5V and the signal voltage VS10 is 5V. In the following description, the operation of the electrostatic discharge protection circuit 1 in input mode will be illustrated using the example of the input signal SI13 level being in the range of 0V to 3.3V and the signal voltage VS10 being 3.3V.

[0048] See Figure 2A In input mode, since signal voltage VS10 is 3.3V and signal voltage VS11 is 0V, PMOS transistor P10 and NMOS transistor N11 are turned off. The operating voltage VCC on power node ND17 charges capacitor C10 through resistor R10, causing the control voltage V14 on node ND14 to approach or equal to the operating voltage VCC, thus having a high level. Inverter 120 generates a low-level control voltage V15 on node ND15 based on the high-level control voltage V14 on the common node ND14. Specifically, based on the high-level voltage V14 on the common node ND14, NMOS transistor N14 is turned on while PMOS transistor P13 is turned off. Therefore, the control voltage V15 on node ND15 approaches or equal to the operating voltage VSS, thus having a low level. NMOS transistor N15 is then turned off based on the low-level control voltage V15. See also Figure 2B By performing signal simulation on the electrostatic discharge protection circuit 1 of this application, when the voltage level of the input signal SI13 (represented by the X-axis) is in the range of 0V to 3.3V, the control voltage V14 is close to or equal to 3.3V (operating voltage VCC), while the control voltage V15 is close to or equal to 0V (operating voltage VSS).

[0049] like Figure 2AAs shown, the buck converter 110 provides a regulating voltage via a series diode 15, ensuring that the voltage at node ND13 is less than the voltage at the bonding pad 13 (i.e., the voltage level of the input signal SI13). Since the gate of PMOS transistor P12 is coupled to node ND14, PMOS transistor P12 is turned off according to the high-level control voltage V14. According to the low-level control voltage V15 at node ND15, NMOS transistors N12 and N13 are turned off, while PMOS transistor P11 is turned on. Because PMOS transistor P11 is turned on, the voltage at node ND12 is close to or equal to the operating voltage VCC (3.3V) and has a high level, turning on NMOS transistor N10. Furthermore, because NMOS transistor N12 is turned off, NMOS transistor N11 can reliably be turned off according to the signal voltage VS11.

[0050] According to the operation of the electrostatic discharge protection circuit 1 in input mode, since the PMOS transistor P10 and NMOS transistor N11 of the buffer circuit 10 are turned off, the input signal SI13 input to the bonding pad 13 can be transmitted to the core circuit 14 without being affected by the components in the electrostatic discharge protection circuit 1. Furthermore, even if the level of the input signal SI13 is the maximum of 0V to 3.3V (3.3V), since the gate-drain voltage of the PMOS transistor P10 (the voltage difference between the signal voltage VS10 and the voltage at node ND10) and the gate-source voltage of the NMOS transistor N10 (the voltage difference between node ND12 and node ND10) are both close to or equal to 0V, oxide breakdown of the PMOS transistor P10 and NMOS transistor N10 will not occur.

[0051] The above describes the operation of the electrostatic discharge protection circuit 1 in input mode when the level of the input signal SI13 is within the range of 0V to 3.3V and the signal voltage VS10 is 3.3V. When the level of the input signal SI13 is within the range of 0V to 5V and the signal voltage VS10 is 5V, the components in the electrostatic discharge protection circuit 1 of this application operate in the same manner as described above. For example, the on or off states of each transistor in the electrostatic discharge protection circuit 1 are the same as those described above. For example, see [link to relevant documentation]. Figure 2C When the level of input signal SI13 is the highest value (5V) within the range of 0V to 5V, the voltage V13 at node ND13 is approximately 3.3V. Therefore, PMOS transistor P12 can still be turned off according to the high-level control voltage V14.

[0052] Figure 3AThis is a schematic diagram illustrating the operation of the electrostatic discharge protection circuit 1 in output mode. During the output mode, power node ND17 receives the operating voltage VCC (3.3V), and power node ND18 receives the operating voltage VSS (0V) or is coupled to ground. In output mode, the core circuit 14 provides signal voltages VS10 and VS11 with the same level according to its operation. The operating voltage VCC on power node ND17 charges capacitor C10 through resistor R10, causing the control voltage V14 on node ND14 to approach or equal to the operating voltage VCC, thus having a high level. Based on the high voltage V14, NMOS transistor N14 is turned on while PMOS transistor P13 is turned off. Therefore, the control voltage V15 on node ND15 approaches or equal to the operating voltage VSS, thus having a low level. NMOS transistor N15 is then turned off based on the low control voltage V15. By performing signal simulation on the electrostatic discharge protection circuit 1 of this application, the levels of control voltages V14 and V15 in output mode are the same as the levels of control voltages V14 and V15 in input mode (e.g., Figure 2B (As shown).

[0053] like Figure 3A As shown, the buck converter 110 uses the regulating voltage provided by the series diode 15 to make the voltage at node ND13 less than the voltage at the junction pad 13 (i.e., the voltage level of the output signal SO13 (0V~3.3V)). PMOS transistor P12 is turned off according to the high-level control voltage V14. According to the low-level control voltage V15 at node ND15, NMOS transistors N12 and NMOS transistor N13 are turned off, while PMOS transistor P11 is turned on. Because PMOS transistor P11 is turned on, the voltage at node ND12 is close to or equal to the operating voltage VCC (3.3V) and has a high level, thus turning on NMOS transistor N10. Furthermore, because NMOS transistor N12 is turned off, NMOS transistor N11 can reliably be turned on or off according to the signal voltage VS11.

[0054] In output mode, core circuit 14 provides signal voltages VS10 and VS11 with the same level according to its operation. (See also...) Figure 3BWhen both signal voltages VS10 and VS11 are high (e.g., VS10 and VS11 are 3.3V), NMOS transistor N11 is turned on while PMOS transistor P10 is turned off. At this time, node ND10 is pulled down to near or equal to voltage VSS (0V) through the turned-on NMOS transistors N10 and N11, therefore the voltage level of the output signal SO13 output through pad 13 is 0V. When both signal voltages VS10 and VS11 are low (e.g., VS10 and VS11 are 0V), PMOS transistor P10 is turned on while NMOS transistor N11 is turned off. At this time, node ND10 is pulled up to near or equal to voltage VCC (3.3V) through the turned-on PMOS transistor P10, therefore the voltage level of the output signal SO13 output through pad 13 is 3.3V.

[0055] According to the operation of the electrostatic discharge protection circuit 1 in output mode, the drive circuit 11 controls the NMOS transistor N10 to turn on. The PMOS transistor P10 and the NMOS transistor N11 are in different on or off states depending on the signal voltages VS10 and VS11, so that the voltage level of the output signal SO13 is opposite to the levels of the signal voltages VS10 and VS11.

[0056] Figure 4A This diagram illustrates the operation of the electrostatic discharge protection circuit 1 when an electrostatic discharge event occurs on the bonding pad 13. When the core circuit 14 is not operating under normal conditions, power node ND17 is not receiving the operating voltage VDD and is at a low level, and power node ND18 is not receiving the operating voltage VSS or is maintained coupled to ground and is at a low level. Therefore, the voltage on power nodes ND17 and ND18 is 0V. Furthermore, the core circuit 14 does not provide signal voltages VS10 and VS11 to control terminals T10 and T11, and the bonding pad 13 does not output or receive any signals.

[0057] See Figure 4A and Figure 4BWhen an electrostatic discharge (ESD) event occurs on pad 13, the voltage V10 at node 10 instantaneously increases with the change in voltage on pad 13 (or, at this time, the voltage V10 at node 10 is equal to the voltage on pad 13). PMOS transistor P10 is in a floating state at this time. Through the parasitic path formed by the parasitic elements of PMOS transistor P10, the voltage V17 at power node ND17 instantaneously increases with voltage V10. Based on the element characteristics of capacitor C10, the control voltage V14 at common node ND14 is low. According to the low voltage V14, PMOS transistor P13 turns on while NMOS transistor N14 turns off. Therefore, the control voltage V15 at node ND15 instantaneously increases with voltage V17 to turn on NMOS transistor N15. Due to the conduction of N-type transistor N15, a discharge path is formed between power nodes ND17 and ND18, allowing the electrostatic charge on pad 13 to be conducted to ground GND via PMOS transistor P10 and along this discharge path.

[0058] like Figure 4A and Figure 4B As shown, the buck circuit 110 reduces the voltage on the bonding pad 13 by means of the regulating voltage provided by the series diode 15. At this time, the voltage V13 on node ND13 is less than the voltage on the bonding pad 13 but still greater than the control voltage V14, therefore, PMOS transistor P12 is turned on. Since both PMOS transistors P12 and PMOS transistor P13 are turned on, it is ensured that the control voltage V15 on node ND15 can change with voltage V17. According to the high level control voltage V15 on node ND15, NMOS transistors N12 and NMOS transistor N13 are turned on, while PMOS transistor P11 is turned off. Since PMOS transistor P11 is turned off and NMOS transistor N13 is turned on, the voltage on node ND12 is close to or equal to the voltage (0V) on power node ND18 and has a low level, so that NMOS transistor N10 is turned off. In addition, since NMOS transistor N12 is turned on, the voltage on node ND11 is close to or equal to the voltage (0V) on power node ND18 and has a low level (e.g., Figure 4B (As shown), to turn off NMOS transistor N11.

[0059] As described above, when an electrostatic discharge event occurs on the bonding pad 13, the drive circuit 11 forcibly turns off NMOS transistors N10 and NMOS transistor N11 according to control voltages V14 and V15. Therefore, the electrostatic discharge current from the bonding pad 13 is conducted to the power node ND18 through the parasitic bipolar transistors formed between NMOS transistors N10 and NMOS transistor N11 and their bases, thereby improving the electrostatic discharge capability of the buffer circuit 10.

[0060] Figure 5 This illustrates an electrostatic discharge protection circuit according to another embodiment of the present invention. (See also...) Figure 5 The circuit architecture of electrostatic discharge protection circuit 5 is similar to... Figure 1 The circuit architecture of the electrostatic discharge protection circuit 1 is roughly the same. The difference between the electrostatic discharge protection circuit 5 and the electrostatic discharge protection circuit 1 is that the drive circuit 11 of the electrostatic discharge protection circuit 5 does not include the PMOS transistor P12 of the electrostatic discharge protection circuit 1. Even though the drive circuit 11 of the electrostatic discharge protection circuit 5 does not include the PMOS transistor P12, the operation of the buffer circuit 10, the other components of the drive circuit 11, and the power supply clamping circuit 12 is as described above. Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 4A , Figure 4B The operation is omitted here. According to this embodiment, since the drive circuit 11 of the electrostatic discharge protection circuit 5 does not include the PMOS transistor P12, when the core circuit 14 is not operating in the normal operating state and an electrostatic discharge event occurs on the bonding pad 13, the drive circuit 11 receives the control voltage V15 and operates according to the control voltage V15 to forcibly turn off the NMOS transistors N10 and NMOS transistor N11.

[0061] Figure 6 This illustrates an electrostatic discharge protection circuit according to another embodiment of the present invention. (See also...) Figure 6 The circuit architecture of electrostatic discharge protection circuit 6 is similar to... Figure 1 The circuit architecture of the electrostatic discharge protection circuit 1 is roughly the same. The difference between the electrostatic discharge protection circuit 6 and the electrostatic discharge protection circuit 1 is that the drive circuit 11 of the electrostatic discharge protection circuit 6 does not include the NMOS transistor N13 of the electrostatic discharge protection circuit 1. Since the drive circuit 11 of the electrostatic discharge protection circuit 5 does not include the NMOS transistor N13, when the core circuit 14 is not operating under normal conditions and an electrostatic discharge event occurs on the bonding pad 13, the NMOS transistor N10 is in a floating state because the PMOS transistor P11 is turned off. When an electrostatic discharge event occurs on the bonding pad 13, only the NMOS transistor N11 is in the floating state. Figure 4A and Figure 4B This is the off state. The operation of the other components of the buffer circuit 10, the drive circuit 11, and the power clamping circuit 12 is as described above. Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 4A , Figure 4BThe operation is omitted here.

[0062] Figure 7 This illustrates an electrostatic discharge protection circuit according to another embodiment of the present invention. (See also...) Figure 7 The circuit architecture of electrostatic discharge protection circuit 7 is similar to... Figure 1 The circuit architecture of the electrostatic discharge protection circuit 1 is roughly the same. The difference between the electrostatic discharge protection circuit 7 and the electrostatic discharge protection circuit 1 is that the drive circuit 11 of the electrostatic discharge protection circuit 7 does not include the NMOS transistor N12 of the electrostatic discharge protection circuit 1. Since the drive circuit 11 of the electrostatic discharge protection circuit 7 does not include the NMOS transistor N12, the NMOS transistor N11 is in a floating state when the core circuit 14 is not operating under normal conditions. When an electrostatic discharge event occurs on the bonding pad 13, only the NMOS transistor N10 is in the floating state. Figure 4A and Figure 4B This is the off state. The operation of the other components of the buffer circuit 10, the drive circuit 11, and the power clamping circuit 12 is as described above. Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 4A , Figure 4B The operation is omitted here.

[0063] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by reference to the appended claims.

Claims

1. An electrostatic discharge protection circuit, characterized in that, Coupled to a bonding pad, comprising: A buffer circuit includes a first transistor and a second transistor connected in series between a first node and a first power node and having a first conductivity type, wherein the bonding pad is coupled to the first node. A driving circuit receives a first control voltage and determines the state of at least one of a first transistor and a second transistor based on the first control voltage, wherein the driving circuit includes: A third transistor having a second conductivity type, wherein the third transistor is coupled between a second power node and the gate of the first transistor and is controlled by the first control voltage; A fourth transistor having the second conductivity type, wherein the fourth transistor is coupled between a third node and a second node and is controlled by a second control voltage; and A power clamping circuit is coupled to the bonding pad through the first node and to the gate of the third transistor at the second node; The first control voltage is generated at the second node, and the power clamping circuit determines the level of the first control voltage based on the voltage on the bonding pad. The buffer circuit further includes: A pull-up transistor having the second conductivity type, wherein the pull-up transistor is coupled between the second power node and the second node and is controlled by the second control voltage.

2. The electrostatic discharge protection circuit as described in claim 1, characterized in that, When an electrostatic discharge event occurs on the bonding pad, the drive circuit shuts off at least one of the first transistor and the second transistor according to the first control voltage.

3. The electrostatic discharge protection circuit as described in claim 1, characterized in that, The buffer circuit further includes: A fifth transistor, having the second conductivity type, and coupled between the second power node and the first node; and The driving circuit further includes: A step-down circuit is coupled between the bonding pad and the third node; A sixth transistor having the first conductivity type, wherein the sixth transistor is coupled between the gate of the first transistor and the first power supply node and is controlled by the first control voltage; and A seventh transistor having the first conductivity type, wherein the seventh transistor is coupled between the gate of the second transistor and the first power supply node and is controlled by the first control voltage; The power clamping circuit generates the second control voltage in response to the voltage on the bonding pad and determines the level of the first control voltage based on the second control voltage.

4. The electrostatic discharge protection circuit as described in claim 1, characterized in that, The buffer circuit further includes: A fifth transistor, having the second conductivity type, and coupled between the second power node and the first node; and The driving circuit further includes: A step-down circuit is coupled between the bonding pad and the third node; and A sixth transistor having the first conductivity type, wherein the sixth transistor is coupled between the gate of the second transistor and the first power supply node and is controlled by the first control voltage; The power clamping circuit generates the second control voltage in response to the voltage on the bonding pad and determines the level of the first control voltage based on the second control voltage.

5. The electrostatic discharge protection circuit as described in claim 1, characterized in that, The buffer circuit further includes: A fifth transistor, having the second conductivity type, and coupled between the second power node and the first node; and The driving circuit further includes: A step-down circuit is coupled between the bonding pad and the third node; and A sixth transistor having the first conductivity type, wherein the sixth transistor is coupled between the gate of the first transistor and the first power supply node and is controlled by the first control voltage; The power clamping circuit generates the second control voltage in response to the voltage on the bonding pad and determines the level of the first control voltage based on the second control voltage.

6. The electrostatic discharge protection circuit as described in any one of claims 3 to 5, characterized in that, The power clamping circuit includes: A resistor and a capacitor are connected in series between the second power node and the first power node, wherein the second control voltage is generated at a common node between the resistor and the capacitor; and A pull-down transistor having the first conductivity type, wherein the pull-down transistor is coupled between the second node and the first power node and is controlled by the second control voltage.

7. The electrostatic discharge protection circuit as described in claim 6, characterized in that, In an input mode, the first power node has a first operating voltage, the second power node receives a second operating voltage higher than the first operating voltage, the gate of the second transistor receives a first signal voltage, and the gate of the fifth transistor receives a second signal voltage. as well as In the input mode, the level of the second signal voltage is higher than that of the first signal voltage.

8. The electrostatic discharge protection circuit as described in claim 6, characterized in that, In an output mode, the first power node has a first operating voltage, the second power node receives a second operating voltage higher than the first operating voltage, the gate of the second transistor receives a first signal voltage, and the gate of the fifth transistor receives a second signal voltage. as well as In the output mode, the level of the second signal voltage is equal to that of the first signal voltage.

9. The electrostatic discharge protection circuit as described in claim 6, characterized in that, When the second power node does not receive any operating voltage and an electrostatic discharge event occurs on the bonding pad, the drive circuit turns off at least one of the first transistor and the second transistor according to at least one of the first control voltage and the second control voltage.

10. An electrostatic discharge protection circuit, characterized in that, Coupled to a bonding pad, comprising: A buffer circuit, comprising: A first transistor having a first conductivity type and coupled between a first node and a second node, wherein the bonding pad is coupled to the first node; and A second transistor having the first conductivity type and coupled between the second node and a first power node; A driving circuit receives a first control voltage and determines the state of at least one of the first transistor and the second transistor based on the first control voltage, wherein the driving circuit further includes: A third transistor having a second conductivity type, wherein the third transistor is coupled between a fourth node and a third node and is controlled by a second control voltage; and A fourth transistor having the second conductivity type, wherein the fourth transistor is coupled between a second power node and the gate of the first transistor and is controlled by the first control voltage; and A power clamping circuit is coupled to the bonding pad through the first node and to the drive circuit at the third node; Wherein, the first control voltage is generated at the third node, and the power clamping circuit determines the level of the first control voltage based on the voltage on the bonding pad; and When an electrostatic discharge event occurs on the bonding pad, the drive circuit turns off the first transistor according to the first control voltage.

11. The electrostatic discharge protection circuit as described in claim 10, characterized in that, When the electrostatic discharge event occurs on the bonding pad, the drive circuit further shuts off the second transistor according to the first control voltage.

12. The electrostatic discharge protection circuit as described in claim 10, characterized in that, The buffer circuit further includes: A fifth transistor, having the second conductivity type, and coupled between the second power node and the first node; and The driving circuit further includes: A step-down circuit is coupled between the bonding pad and the fourth node; A sixth transistor having the first conductivity type, wherein the sixth transistor is coupled between the gate of the first transistor and the first power supply node and is controlled by the first control voltage; and A seventh transistor having the first conductivity type, wherein the seventh transistor is coupled between the gate of the second transistor and the first power supply node and is controlled by the first control voltage; The power clamping circuit generates the second control voltage in response to the voltage on the bonding pad and determines the level of the first control voltage based on the second control voltage.

13. The electrostatic discharge protection circuit as described in claim 10, characterized in that, The buffer circuit further includes: A fifth transistor, having the second conductivity type, and coupled between the second power node and the first node; and The driving circuit further includes: A step-down circuit is coupled between the bonding pad and the fourth node; and A sixth transistor having the first conductivity type, wherein the sixth transistor is coupled between the gate of the first transistor and the first power supply node and is controlled by the first control voltage; The power clamping circuit generates the second control voltage in response to the voltage on the bonding pad and determines the level of the first control voltage based on the second control voltage.

Images