System-on-chip including pvt sensors and corresponding pvt sensing methods

Abstract

The present disclosure relates to a system-on-chip including a PVT sensor and a corresponding PVT sensing method. A system-on-chip includes a process voltage temperature (PVT) sensor having a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to changes in a semiconductor material of the system-on-chip, an operating power supply voltage, and an operating temperature. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. In response to detecting a comparison of a difference between the initiated patterned digital signal and the propagated patterned digital signal, a warning signal is generated.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to French patent application No. 2200018, filed on January 3, 2022, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] The embodiments relate to integrated circuits, such as systems-on-a-chip, including process voltage-temperature (PVT) methods.

[0004] Sensors and corresponding PVT sensing methods. Background Technology

[0005] It is well known that electronic devices containing systems-on-a-chip, such as smartphones or devices used in industrial or automotive applications, may be vulnerable to external attacks by unauthorized users with the aim of tampering with the electronic device and / or gaining access to the data stored in the electronic device.

[0006] For example, to tamper with the on-chip system, an unauthorized user could change the operating power supply voltage or alter the chip's operating temperature, thereby introducing the on-chip system into an error state. Other errors...

[0007] The introduced technology can act on clock signals by adjusting their frequency, or on the physical behavior of silicon or other semiconductors by electromagnetic or laser stimulation. Unauthorized users can then exploit this fault to gain access to the on-chip system.

[0008] In fact, if operating conditions such as power supply voltage, temperature, frequency, or semiconductor physics change outside the nominal operating range, the on-chip system may enter a fault state and operate unexpectedly.

[0009] This leads to security issues related to the voluntary alteration of operating conditions of systems used to tamper with chips.

[0010] This also leads to safety issues related to involuntary changes in operating conditions, such as those implied by critical environments in the automotive sector, where extreme temperatures can be reached and electrical failures (such as power supply voltage drops) may occur due to the high energy required by electric motors used at high performance.

[0011] Traditional techniques for detecting changes in operating conditions outside the nominal operating range are typically based on direct power supply voltage measurements and direct temperature measurements, and mean additional silicon and power consumption to accommodate such sensors in an on-chip system.

[0012] Furthermore, traditional techniques for detecting changes in operating conditions are typically not linked to technical parameters. Technical parameters are those related to the physical characteristics of a semiconductor, also known as process variations. Therefore, these techniques cannot detect clock frequency tweaking or changes in semiconductor behavior through electromagnetic or laser stimulation.

[0013] Furthermore, traditional sensors that operate under varying conditions are typically hardware-based and static, meaning the detection trigger is fixed at the manufacturing stage. Therefore, customers cannot configure detection triggers with varying degrees of sensitivity to suit their specific applications.

[0014] Therefore, there is a need to provide an apparatus and method to prevent the aforementioned security and safety issues, and to overcome the shortcomings of conventional technologies. Summary of the Invention

[0015] According to embodiments provided below, a configurable hardware tool is proposed that can detect out-of-range operating conditions by using components that make all circuitry within an on-chip system identical and based on physical process voltage and temperature conditions. In other words, in the proposed embodiments, this technique informs the user that the system is about to fail and is therefore able to detect any nature of tampering conditions for assurance and security purposes.

[0016] According to one aspect, a system-on-a-chip (SoC) is proposed, comprising a process voltage-temperature (PVT) sensor, the PVT sensor including a filter circuit and a digital comparator circuit. The filter circuit is configured to initiate a patterned digital signal and propagate the patterned digital signal in response to changes in the semiconductor material, operating supply voltage, and operating temperature of the SoC. The digital comparator circuit is configured to compare the initiated patterned digital signal and the propagated patterned digital signal, and generate a warning signal upon detecting a difference between the compared patterned digital signals.

[0017] The term "responding to" means "dependent on" or "affected by," for example, in such a way that a filter circuit is configured to propagate a patterned digital signal according to nominal behavior without modifying the patterned digital signal when the operating conditions are within the nominal range, and to propagate a patterned digital signal according to tampering behavior that modifies the patterned digital signal when the operating conditions are outside the nominal range.

[0018] Therefore, by observing the differences introduced by the filter circuit in forming patterned digital signals, this aspect allows for modifications to the characteristics of the circuit materials and components in the actual performance of the detection circuit (more specifically, the filter circuit), providing better information about the risk of failure than detection isolation measurements (such as traditional detection based on power supply voltage measurements or temperature measurements).

[0019] According to one embodiment, the filter circuit includes: a first trigger circuit configured to propagate a patterned digital signal; and a first delay circuit configured to delay the patterned digital signal at the data input of the first trigger circuit and configured to respond to changes in the semiconductor material of the system-on-chip, the operating power supply voltage, and the operating temperature.

[0020] The first delay circuit located at the data input of the first trigger circuit allows for an increase in the duration of the detection delay, which advantageously corresponds to a decrease in system speed below the nominal range, and is also known as a detection of setting violations.

[0021] For example, the first delay circuit can be any digital unit where the inherent delay increases with temperature. A digital delay unit is preferred because this type of digital unit is usually the most sensitive.

[0022] According to one embodiment, the filter circuit includes: a second flip-flop configured to propagate a patterned digital signal and controlled by a clock signal; a second delay circuit configured to delay the patterned digital signal at the data input of the second flip-flop circuit, and the second delay circuit is responsive to changes in the semiconductor material, operating power supply voltage, and operating temperature of the on-chip system; and a third delay circuit configured to delay the clock signal at the clock input of the second flip-flop circuit, and the third delay circuit is less responsive to changes in the semiconductor material, operating power supply voltage, and operating temperature of the on-chip system compared to the second delay circuit.

[0023] The combination of the second and third delay circuits, located at the data input and clock input of the second trigger circuit respectively, detects a reduction in the duration of the delay, which advantageously corresponds to an increase in system speed above the nominal range. This is also known as the detection of a violation, such as when the temperature becomes below the minimum nominal limit and / or when the supply voltage increases above the maximum nominal limit.

[0024] A timing violation occurs in the configuration defined by this embodiment when the difference between two delays is not within the nominal range.

[0025] According to one embodiment, the PVT sensor includes a register configured to store internal parameters that determine the responsiveness of the filter circuitry to changes in the semiconductor material, operating supply voltage, and operating temperature of the system on chip.

[0026] According to one embodiment, the internal parameters include the delay duration of (multiple) corresponding delay circuits, such as the first delay circuit in the embodiment first defined above, the second delay circuit and the third delay circuit in the embodiment second defined above, or the first delay circuit, the second delay circuit and the third delay circuit in a combination of the two embodiments.

[0027] The ability to configure internal parameters allows users to set and modify a nominal range of operating conditions. Therefore, according to this embodiment, the protection of the system-on-chip can be adapted to specific usage conditions and to the degree of criticality of the operations performed by the system-on-chip (such as critical operations requiring high security and protection).

[0028] According to one embodiment, the system-on-chip additionally includes peripheral circuitry and at least one internal bus linking the peripheral circuitry together in a respective bus domain. The PVT sensor is incorporated into the bus domain in physical proximity to the peripheral circuitry and is provided with the same power supply voltage and the same clock signal as the peripheral circuitry in the bus domain.

[0029] According to one embodiment, the PVT sensor includes the same components as those in the peripheral circuitry that are physically close to the PVT sensor.

[0030] Therefore, in these embodiments, the PVT sensor operates in the same manner and under the same operating conditions as the peripheral circuitry in the corresponding bus domain, and provides effective and practical detection of potential faults or failure risks.

[0031] According to one embodiment, the PVT sensor includes a bus interface configured to receive and transmit communications on an internal bus.

[0032] According to one embodiment, the system-on-a-chip includes a main unit configured to perform software operations, including transmitting configuration commands to a PVT sensor via an internal bus, the configuration commands being configured to set internal parameters of the PVT sensor.

[0033] According to one embodiment, the PVT sensor is configured to transmit a warning signal to the decision unit via an internal bus.

[0034] In other words, in these embodiments, the PVT sensor (advantageously included within the bus domain of the peripheral circuitry) is controlled and operates on the internal bus like the peripheral circuitry. This provides a variety of communication and configuration capabilities for the use of the PVT sensor.

[0035] According to another aspect, a method for sensing process voltage-temperature (PVT) changes in a system-on-a-chip is proposed, comprising: activating a patterned digital signal; propagating the patterned digital signal through a filter circuit in response to changes in the semiconductor material, operating power supply voltage, and operating temperature of the system-on-a-chip; digitally comparing the activated patterned digital signal and the propagated patterned digital signal; and generating a warning signal if there is a difference between the compared patterned digital signals.

[0036] According to one embodiment, propagating a patterned digital signal includes passing it through a first trigger circuit and applying a first delay to the patterned digital signal at the data input of the first trigger circuit, the first delay being responsive to changes in the semiconductor material of the system-on-chip, the operating power supply voltage, and the operating temperature.

[0037] According to one embodiment, propagating a patterned digital signal includes: applying a second delay to the patterned digital signal at the data input of a second flip-flop circuit controlled by a clock signal, and applying a third delay to the clock signal at the clock input of the second flip-flop circuit, wherein the second delay is responsive to changes in the semiconductor material, operating power supply voltage, and operating temperature of the system on chip, and the third delay is less responsive to changes in the semiconductor material, operating power supply voltage, and operating temperature of the system on chip than the second delay.

[0038] According to one embodiment, the method further includes storing internal parameters in a register that determine the responsiveness of the on-chip filter circuit to changes in semiconductor material, operating supply voltage, and operating temperature; these internal parameters are configurable.

[0039] According to one embodiment, the internal parameters include the duration of(a) corresponding delays.

[0040] According to one embodiment, sensing process voltage-temperature (PVT) changes is performed in proximity to peripheral circuitry linked together via at least one internal bus in a corresponding bus domain of the system-on-chip, and is performed with the same power supply voltage and the same clock signal as the peripheral circuitry of the bus domain.

[0041] According to one embodiment, sensing process voltage-temperature (PVT) changes is performed using the same components as those in the peripheral circuitry that are physically close to the sensing location.

[0042] According to one embodiment, the method includes receiving and transmitting communications on an internal bus via a bus interface, including communications of configuration commands for setting internal parameters transmitted from a master unit of a system-on-a-chip configured to perform software operations.

[0043] According to one embodiment, the method includes transmitting a warning signal to a decision unit of the system-on-chip via an internal bus. Attached Figure Description

[0044] Other advantages and descriptions of the invention will become apparent in a review of the detailed description of the embodiments, which are by no means limiting, and are associated with the accompanying drawings, in which:

[0045] Figure 1 A block diagram of a method for sensing process voltage-temperature (PVT) changes in an on-chip system is shown.

[0046] Figure 2A An example embodiment of a system-on-a-chip (SoC) including a process voltage-temperature (PVT) sensor is shown;

[0047] Figure 2B , 2C 2D and 2E show the relationship with Figure 2A The timing diagram of the signals related to the filter circuit and comparator is shown below;

[0048] Figure 3A Another example embodiment of a system-on-a-chip (SoC) including a process voltage-temperature (PVT) sensor is shown;

[0049] Figure 3B , 3C 3D and 3E demonstrate the relationship with Figure 3A The timing diagram of the signals related to the filter circuit and comparator is shown below;

[0050] Figure 4 An example embodiment is shown from a more advanced perspective of a system-on-a-chip (SoC) including a process voltage-temperature (PVT) sensor; and

[0051] Figure 5 A schematic general example of a system-on-a-chip (SoC) including a process voltage-temperature (PVT) sensor is shown. Detailed Implementation

[0052] Figure 1 A block diagram of a method 100 for sensing process voltage-temperature (PVT) variations in a system-on-chip (SoC) is shown. Method 100 includes initiating a patterned digital signal 101, propagating the patterned digital signal 103 through a filter circuit FLT, and performing a digital comparison 105 between the initiated patterned digital signal PDSi and the propagated patterned digital signal PDSo. The filter circuit is configured such that the propagation of the patterned digital signal PDSo responds to (i.e., "depends on" or "is affected by") variations in the semiconductor material Smc, operating supply voltage Vdd, and operating temperature Tmp of the SoC. The digital comparison 105 includes generating a warning signal 107 if a difference exists between the compared patterned digital signals.

[0053] Figure 2A An example embodiment of a system-on-chip (SoC) including a process voltage and temperature (PVT) sensor SNS is shown, which is configured to perform operations related to... Figure 1 The method described.

[0054] The PVT sensor SNS includes a filter circuit FLT configured to initiate a patterned digital signal PDS and propagate the patterned digital signal in response to changes in the semiconductor material Smc, operating supply voltage Vdd, and operating temperature Tmp of the system-on-chip (SOC). The PVT sensor SNS also includes a digital comparator circuit CMP configured to compare the initiated patterned digital signal PDSi and the propagated patterned digital signal PDSo via the filter circuit FLT, and generate warning signals SV and HV if a difference exists between the compared patterned digital signals.

[0055] In this exemplary embodiment, to initiate the patterned digital signal PDS, the PVT sensor SNS includes a pattern generator PGN configured to generate the patterned digital signal PDS. In this example, the pattern generator includes a feedback inverter circuit coupled from the output Q1 to the input D1 of a first D-type flip-flop DF1. The first D-type flip-flop DF1 is controlled by a clock signal clk and thus generates a series of alternating zeros "0" and one "1", which triggers in each clock cycle and forms a digital pattern.

[0056] Traditionally, a D-type flip-flop is a synchronous latch that is configured to capture the value of the "D" (data) input at a certain part of the clock cycle (such as the rising edge of the clock), and the captured value becomes the "Q" output.

[0057] In alternative example embodiments (in) Figure 4 As shown in the diagram, in order to initiate the patterned digital signal PDS, the PVT sensor SNS may include a dedicated input configured to receive the patterned digital signal PDS, which is generated by an external device and transmitted on the dedicated input.

[0058] A first D-type flip-flop DF1 is also included in a first flip-flop circuit FFC1, which is configured to detect a setting violation SV. The first flip-flop circuit includes a second D-type flip-flop DF2 controlled by a clock signal clk, and has an input D2 connected to the output Q1 of the first flip-flop DF1, and an output Q1 of a patterned digital signal PDSo that propagates outwards.

[0059] In addition, the first trigger circuit FFC1 includes a first delay circuit DEL1, which is connected in the feedback loop of the pattern generator PGN and is configured to delay the patterned digital signal at the data input D1 of the D-type trigger DF1.

[0060] The first delay circuit DEL1 is illustrated upstream (before) the inverter in the feedback loop of the pattern generator PGN, but it can also be placed downstream (after) the inverter in the feedback loop of the pattern generator PGN.

[0061] The first delay circuit DEL1, connected in the data paths D1, Q1, D2, Q2 of the filter circuit FLT, is configured to respond to changes in the semiconductor material Smc, the operating supply voltage Vdd, and the operating temperature Tmp of the system-on-chip (SOC).

[0062] The digital comparator circuit CMP includes, for example, an XOR gate that receives an activated patterned digital signal PDSi (on D2) and a propagated patterned digital signal PDSo (on Q2) to output a signal SV corresponding to their comparison (equal or different). By convention, the output of the XOR gate can be inverted to provide a high-level signal "at 1" when a warning signal is triggered and a low-level signal "at 0" when it is not triggered.

[0063] Figure 2B , 2C 2D and 2E show the relationship with Figure 2A The timing diagram of the signals related to the filter circuit FLT and comparator CMP shown is in... Figure 2B The diagram shows the nominal conditional behavior as "error-free". Figure 2C This illustrates a scenario where the "setting error" behavior is violated. Figure 2D The following are examples of situations where the violation is "held in error": Figure 2E This illustrates the scenarios of setting and maintaining the violation behavior "Setting and Maintaining Error". Figure 2A The signals associated with the corresponding nodes of the circuit SNS shown are named using the same reference numerals as the corresponding nodes.

[0064] We now refer to Figure 2B "No error".

[0065] The clock signal clk has a constant period T, and at each rising edge of the clock signal clk, the D flip-flop DF1 outputs a signal Q1, which is at the digital level that the data input D1 has at the rising edge.

[0066] The output signal Q1 is delayed for a duration of DEL1 and inverted (considered to be an inverted signal without delay) to provide the data input signal D1.

[0067] Under nominal operating conditions, output Q2 essentially corresponds to output Q1 shifted by one clock cycle. Therefore, output Q1 (input D2) and output Q2 are always opposite, such as the warning signal SV, which is always 0.

[0068] We now refer to Figure 2C "Setting error".

[0069] Figure 2C The scenario depicts a situation where the System-on-Chip (SOC) is tampered with or its speed is reduced under operating conditions. In this case, because the first delay circuit DEL1 is configured to be sensitive to such modifications to operating conditions, an additional non-nominal delay +Δ is positively added to the duration of the first delay DEL1.

[0070] Therefore, if the additional delay +Δ places the next edge of the data input signal D1 after the next rising edge of the clock signal clk, then at the rising edge of that next clock signal, the level of the data input D1 remains at its previous level. Consequently, the output Q1 does not switch at the rising edge of that clock signal and maintains its previous level for one additional clock cycle.

[0071] However, the second D-type flip-flop circuit DF2 is controlled by the clock signal clk, and therefore switches its state to the level provided by Q1.

[0072] As a result, the Q1 and Q2 signals have the same level during one complete clock cycle, and alternatively, have opposite levels during another complete clock cycle.

[0073] Therefore, during the alternating full clock cycle, that is, during the time period when the Q1 signal and the Q2 signal have the same level, the output SV of the XOR comparator circuit is periodically triggered to "1".

[0074] This allows the communication system to be slowed down to the extent that the settings of the system-on-chip (SoC) have been violated.

[0075] The duration of the first delay DEL1 can be advantageously configured to provide a margin for generating the warning signal SV. For example, since the warning signal SV is generated once the total duration of the delay DEL1+Δ is greater than the clock cycle period T, the nominal duration of the first delay DEL1 can be set to be an amount (T-DEL1) lower than the period T, which provides tolerance for the additional non-nominal delay +Δ before the warning signal SV is generated.

[0076] Now for reference Figure 2A .

[0077] The filter circuit FLT also includes a second flip-flop circuit FFC2, which includes a third D-type flip-flop DF3, which is configured to be controlled by a delayed clock signal clkd.

[0078] The filter circuit FLT includes a second delay circuit DEL2 and a third delay circuit DEL3. The second delay circuit DEL2 is configured to introduce a second delay on the patterned digital signal PDS propagating at the output Q2 of the second flip-flop DF2, and the third delay circuit DEL3 is configured to introduce a third delay on the clock signal clk to generate a delayed clock signal clkd.

[0079] The second delay circuit DEL2 is configured to respond to changes in the semiconductor material Smc, operating power supply voltage Vdd, and operating temperature Tmp of the system-on-chip (SoC), while the third delay circuit DEL3 is configured to respond less to changes in the semiconductor material Smc, operating power supply voltage Vdd, and operating temperature Tmp of the SoC than the second delay circuit DEL2.

[0080] For example, the second delay circuit DEL2 may include digital delay units, while the third delay circuit DEL3 may include digital buffers, which are generally less sensitive to PVT variations than the digital delay units. For example, delay units (by construction) are based on internal slopes (a characteristic of the unit) that make them more sensitive to PVT variations.

[0081] The second comparator circuit CMP2 (e.g., including an inverting XOR gate) is configured to receive the input D3 of the third flip-flop DF3 (i.e., the delayed patterned digital signal propagated by the second flip-flop DF2 at its output Q2) and the output Q3 of the third flip-flop circuit DF3.

[0082] Advantageously, the duration of the second delay DEL2 is greater than the duration of the third delay DEL3.

[0083] We now refer to Figure 2B "No error".

[0084] In the example described, the duration of the second delay DEL2 is set to be approximately equal to the duration of the third delay DEL3, but in general, the second delay DEL2 is greater than the third delay DEL3.

[0085] Therefore, after the next clock cycle of the delayed clock clkd, the edge in the output Q2 of the second flip-flop DF2 is delayed at the input D3 of the third flip-flop DF3.

[0086] Under nominal conditions, the output Q3 of the third flip-flop DF3 therefore takes the previous value of the output Q2 of the second flip-flop DF2 (i.e., the value before the edge).

[0087] When the duration of the second delay DEL2 is approximately equal to the duration of the third delay DEL3, signals D3 and Q3 are always at opposite levels. Therefore, the warning signal HV remains constant at level "0", indicating that there is no holding error.

[0088] When the duration of the second delay DEL2 is slightly longer than the duration of the third delay DEL3, signals D3 and Q3 are mainly at opposite levels, except during the short duration of these signals, which is equal to the time difference between the edge of the delayed clock cycle (delayed by the third delay) and the edge of the data signal (delayed by the second delay).

[0089] Therefore, the warning signal HV is mainly at level "0", the short pulse is at level "1", and there is no transmission and holding error.

[0090] We now refer to Figure 2D "Maintain error".

[0091] Figure 2D The scenario depicts a situation where the system-on-chip (SoC) is tampered with or its speed is increased under operating conditions. An additional non-nominal delay – Δ – is negatively added to the duration of the second delay, DEL2, while the third delay is considered unchanged because the second delay circuit, DEL2, is configured to be more sensitive to such modifications to operating conditions than the third delay circuit, DEL3.

[0092] Therefore, if the additional negative delay -Δ is large enough to advance the considered edge of the delayed data signal D3 before the next rising edge of the delayed clock signal clkd (at the input of the third flip-flop DF3).

[0093] Therefore, before the next clock cycle of the delayed clock clkd, the edge in the output Q2 of the second flip-flop DF2 is delayed at the input D3 of the third flip-flop DF3.

[0094] Under these conditions of increased speed alteration, the output Q3 of the third flip-flop DF3 takes the next value of the output Q2 of the second flip-flop DF2 (i.e., the value after the edge).

[0095] Therefore, in these tampered cases, signals D3 and Q3 are at the same level for the entire clock cycle clkd after the considered rising edge, except for a short duration of opposite durations during the time difference between the edge of the delayed clock cycle (delayed by the third delay) and the edge of the data signal (delayed by the second delay and the additional negative delay -Δ).

[0096] Therefore, the warning signal HV is mainly at level "1", with short pulses at level "0" periodically at clkd in each delayed clock cycle, conveying the "holding error".

[0097] Furthermore, the difference in duration between the second delay DEL2 and the third delay DEL3 can be advantageously configured to provide a margin for generating the warning signal HV. In practice, since the warning signal HV is generated once the total duration of delay DEL2 – Δ is less than the duration of the third delay DEL3, the nominal duration of the second delay DEL2 can be set to be an amount (DEL2 – DEL3) larger than the third delay DEL3 before generating the warning signal HV. This amount provides tolerance for a negative additional non-nominal delay – Δ.

[0098] Recall that in this example, we have already considered that the third delay DEL3 remains constant in absolute value. However, in practice, the third delay DEL3 should actually vary and be less than the second delay DEL2, and this variation should be accounted for to establish a margin of safety.

[0099] Figure 2E Additionally, it describes how the complexity of the system-on-chip (SoC) allows setup errors to be introduced in the data path and hold errors to be introduced in the clock path when the SoC is tampered with.

[0100] The generated warning signals SV and HV are combined from the previous ones. Figure 2C and Figure 2D The combination of the two described situations produces a manner that is easily derived from these descriptions and combinations. Figure 2A The structure is derived from the described circuit.

[0101] In summary, under these conditions, during the alternating full clock cycles, the violation warning signal SV is periodically triggered to "1", while the violation warning signal HV remains primarily at level "1", with short pulses periodically at level "0" at clkd every two consecutive delayed clock cycles.

[0102] Figure 3A Another example embodiment of a system-on-chip (SoC) including a process voltage and temperature (PVT) sensor SNS is shown, which is configured to perform operations related to... Figure 1 The method described.

[0103] To initiate the patterned digital signal, the PVT sensor SNS includes a pattern generator PGN configured to generate the patterned digital signal PDS. Similarly, the pattern generator PGN includes a feedback inverter circuit coupled from its output Qg to the input Dg of the pattern generator trigger circuit FFCg. The pattern generator trigger circuit FFCg is controlled by a clock signal clk and thus generates a series of alternating zeros "0" and one "1", triggering in each clock cycle and forming the digital pattern.

[0104] The PVT sensor SNS includes a filter circuit FLT, which includes a reference trigger circuit FFCr. The reference trigger circuit FFCr receives a patterned digital signal at its input Dr and propagates a patterned digital signal triggered by a clock signal clk at its output Qr.

[0105] The reference flip-flop circuit FFCr acts as a synchronizer for a mode that is delayed by one clock cycle, allowing it to have the same behavior as the outputs of FFC1 and FFC2 without error.

[0106] The filter circuit FLT includes a first delay circuit DEL1, which is configured to introduce a first delay DEL1 onto the patterned digital signal in response to changes in the semiconductor material Smc of the system-on-chip (SOC), the operating supply voltage Vdd, and the operating temperature Tmp.

[0107] The first flip-flop circuit FFC1 receives a delayed patterned digital signal at its input D1 and propagates a patterned digital signal triggered by the clock signal clk at its output Q1.

[0108] The filter circuit FLT includes a second delay circuit DEL2, which is configured to introduce a second delay DEL2 onto the patterned digital signal in response to changes in the semiconductor material Smc of the system-on-chip (SOC), the operating supply voltage Vdd, and the operating temperature Tmp.

[0109] The filter circuit FLT includes a third delay circuit DEL3, which is configured to introduce a third delay DEL3 on the clock signal clk in a manner that is less sensitive to changes in the semiconductor material Smc, operating supply voltage Vdd, and operating temperature Tmp of the system on-chip (SOC) than the second delay circuit DEL2.

[0110] The second flip-flop circuit FFC2 receives a delayed patterned digital signal at its input D2 and propagates a patterned digital signal triggered by a delayed clock signal at its output Q2.

[0111] The comparator circuit CMP includes a first comparator, which includes at least an XOR gate and is configured to compare the output signal Qr of the reference flip-flop circuit FFCr with the output signal Q1 of the first flip-flop circuit FFC1.

[0112] The comparator circuit CMP includes a second comparator, which includes at least an XOR gate, configured to compare the output signal Qr of the reference flip-flop circuit FFCr with the output signal Q2 of the second flip-flop circuit FFC1.

[0113] The comparator circuit CMP is accordingly related to... Figure 2B , 2C The methods described in 2D and 2E operate in a similar manner to provide a first warning signal SV, in which a first comparator communicates a setting violation, and provide a second warning signal HV, in which a second comparator communicates a holding violation.

[0114] In summary, for reference Figure 3B , 3C 3D and 3E correspond to the nominal condition "no error", the slowed tampering condition "set error", the tight tampering condition "hold error", and the combination of "set and hold error", respectively.

[0115] In any of these conditions, the reference flip-flop circuit FFCr acts like a shift register on the patterned digital signal PDS provided on the output Qg of the pattern generator flip-flop circuit FFCg. In other words, the reference flip-flop circuit FFCr outputs Qr at each rising edge of the clock cycle clk, with the previous value of its input Qg.

[0116] Under nominal conditions Figure 3B "Error-free" means that before the next rising edge of the clock signal clk, the first delay DEL1 shifts the edge of the digitally patterned signal Qg backward. Therefore, the first flip-flop circuit FFC1 outputs the previous value of the Qr-patterned digital signal Qg at each rising edge of the clock signal clk. Thus, the first flip-flop circuit FFC1 functions the same as the reference flip-flop circuit FFCr, and the output SV of the first comparator is always "0".

[0117] Under nominal conditions, the second delay DEL2 is greater than the third delay DEL3, and therefore the second delay DEL2 shifts the edge of the digitally patterned signal Qg backward after the next rising edge of the delayed clock signal clkd. Therefore, the second flip-flop circuit FFC2 outputs the previous value of the Qr-patterned digital signal Qg at each rising edge of the delayed clock signal clkd. Thus, the second flip-flop circuit FFC2 functions the same as the reference flip-flop circuit FFCr, but is controlled by the delayed clock period clkd, and during the duration of the third delay DEL3, the output HV of the second comparator is primarily "0" with short pulses of "1" periodically in each clock cycle.

[0118] Under conditions that slow down the tampering of the system's SOC, Figure 3CThe "setting error" is addressed by the first delay DEL1 experiencing an additional positive delay +Δ, shifting the edge of the digitally patterned signal Qg backward after the next rising edge of the clock signal clk. Therefore, the first flip-flop circuit FFC1 outputs the next value of the Qr-patterned digital signal Qg at each rising edge of the clock signal clk. Thus, the first flip-flop circuit FFC1 functions in the opposite way to the reference flip-flop circuit FFCr, and the output SV of the first comparator is always "1".

[0119] Under the condition of tampering that increases the speed of the system's SOC, Figure 3D "Maintaining the error," the second delay DEL2 undergoes an additional negative delay –Δ, making it shorter than the third delay DEL3. Therefore, the second delay DEL2 –Δ shifts the edge of the digitally patterned signal Qg backward before the next rising edge of the delayed clock signal clkd. Thus, the second flip-flop circuit FFC2 outputs the next value of the Qr-patterned digital signal Qg at each rising edge of the delayed clock signal clkd. Therefore, the second flip-flop circuit FFC2 acts in opposite directions to the reference flip-flop circuit FFCr, but is controlled by the delayed clock period clkd, and during the duration of the difference between the third delay DEL3 and the second delay DEL2 –Δ, the output HV of the second comparator is primarily "1" with short pulses periodically at "0" in each clock cycle.

[0120] In the combination of the two tampering conditions Figure 3E "Setting and holding error" combines the two results HV and SV, namely, the output SV of the first comparator is always "1", and the output HV of the second comparator is mainly "1", and there are short pulses of "0" periodically at each clock cycle during the duration of the difference between the third delay DEL3 and the second delay DEL2-Δ.

[0121] For this record, the digital delay units of the first and second delay circuits DEL1 and DEL2 mentioned above and below can, for example, include a series of odd-numbered inverter circuits to accumulate their inherent propagation delays. All or several outputs of the inverters can be input to a multiplexer to control the duration of the delay by selecting the corresponding input of the multiplexer.

[0122] Figure 4 An exemplary embodiment is shown from a more advanced viewpoint of a system-on-a-chip (SoC), which includes a process voltage-temperature (PVT) sensor (SNS), such as combined with... Figure 2A -2B-2C-2D-2E and Figure 3A As described in -3B-3C-3D-3E.

[0123] The PVT sensor SNS therefore includes a filter circuit FLT and a digital comparator circuit CMP. The filter circuit FLT is configured to propagate a patterned digital signal in response to changes in the semiconductor material Smc of the system on-chip SOC, the operating supply voltage Vdd, and the operating temperature Tmp. The digital comparator circuit CMP is configured to generate a warning signal WS in the event of a difference between the initiated patterned digital signal and the propagated patterned digital signal.

[0124] The PVT sensor includes a startup stage for initiating a patterned digital signal, which includes an internal pattern signal generator (PGN), such as those previously mentioned. Figures 2A to 3E The external input EXT_PGN is configured to receive an externally generated patterned digital signal, and the multiplexer MUX is configured to select the patterned digital signal from an internal or external source. A gate circuit GT may be provided at the output of the multiplexer MUX to enable or disable the transmission of the patterned digital signal to a filter.

[0125] In addition, the PVT sensor SNS includes a control logic unit, such as a finite state machine (FSM), and a register REG configured to store the internal parameters PVT_config and CMP_config of the filter circuit FLT.

[0126] The internal parameters PVT_config and CMP_config can be configured (i.e., modified) and determine the response of the filter circuit SNS to changes in the on-chip semiconductor material Smc, operating supply voltage Vdd, and operating temperature Tmp.

[0127] For example, internal parameters include the parameter CMP_config, which configures the trigger response of the comparator circuit CMP; and include, for example, parameters related to... Figures 2A to 3E The delay duration of the corresponding delay circuit PVT_config is the duration of the delay introduced by the first delay circuit DEL1, the second delay circuit DEL2, and the third delay circuit DEL3.

[0128] A control logic unit (e.g., a finite state machine) is provided to control different elements of the PVT sensor according to control signals received, for example, from the user or the master device of the chip system.

[0129] For example, the control logic unit (e.g., finite state machine) FSM controls the multiplexer MUX with the selection signal sel; controls the pattern generator circuit PGN with the configuration signal Patt_gen_config; controls the gate circuit GT with the start and stop enable and disable signals; sends the internal parameters PVT_config and CMP_config to the filter circuit FLT and the comparator circuit CMP respectively, and receives the warning signal WS.

[0130] In addition, the PVT sensor SNS includes a bus interface INTFC, which is configured to receive and transmit communication on the internal bus of the system-on-chip (SoC). The internal bus may be, for example, an AHB ("Advanced High Performance Bus") internal bus, an APB ("Advanced Peripheral Bus") internal bus, or other types of internal bus.

[0131] For example, the PVT sensor SNS is configured to transmit warning signals WS (set violation SV or hold violation HV) to decision unit cores #1 and #N via the internal bus BUS. Figure 5 ).

[0132] Figure 5 A schematic general example of a System-on-a-Chip (SoC) is shown, which includes features such as... Figure 2A -2B-2C-2D-2E, Figure 3A -3B-3C-3D-3E and Figure 4 The process voltage and temperature (PVT) sensor SNS is mentioned above.

[0133] The system-on-a-chip specifically includes at least one main unit Core#1, Core#N, at least one AHB type internal bus AHB1 and some peripheral devices CRYPTO, GPIO, ..., CRC linked to the AHB type internal bus AHB1, as well as at least one APB type internal bus APB_bus and some peripheral devices IP#2, ..., IP#6 linked to the APB type internal bus APB_bus.

[0134] The internal buses AHB1 and APB_bus link the corresponding peripheral circuits together in their respective bus domains AHB1, APB_1, and (APB_n). Each bus domain AHB1, APB_1, and (APB_n) can correspond to a region of the logic section of the integrated system-on-a-chip (SoC).

[0135] Included Figure 5 Other components in the system of the chip SOC shown, such as “bus matrix #1”, “flash memory”, “flash memory interface”, “AHB2APB bridge”, “GPDMA1”, “I-cache (8KB)”, “mailbox”, etc., are conventional example components known to those skilled in the art based on the accompanying drawings, and are not described in detail here, as they do not contribute particularly to aspects related to the PVT sensor SNS.

[0136] The PVT sensor SNS is integrated within the bus domains AHB1 and APB_1, and is physically close to the corresponding peripheral circuits CRYPTO, GPIO, ..., CRC and IP#2, ..., IP#6.

[0137] Therefore, the PVT sensors SNS are provided with the same power supply voltage and the same clock signal as the peripheral circuits of their corresponding bus domains AHB1 and APB_1.

[0138] For example, the PVT sensor SNS includes the same components as the peripheral circuitry CRYPTO, GPIO, ..., CRC and IP#2, ..., IP#6, which are physically close to the corresponding PVT sensor, such as the same electronic components, like transistors and logic gates.

[0139] This firstly allows PVT sensors to be sensitive to tampering with the operating conditions of semiconductor materials affecting peripheral circuits, as well as localized modifications to the operating conditions affecting the power supply voltage and / or temperature of peripheral circuits. Secondly, by utilizing an architecture that uses the same components, PVT sensors accurately represent the actual impact of operating conditions on peripheral circuits.

[0140] On the other hand, this includes PVT sensor SNS configured to receive and transmit communication bus interface INTFC on the internal bus BUS, such as in combination with Figure 4 As described, it is advantageously capable of operating like a general-purpose peripheral circuit linked on a bus.

[0141] Therefore, for example, master unit cores #1 and #N, configured to perform software operations, can transmit configuration commands to the PVT sensor SNS via the internal buses AHB1 and APB_. These configuration commands are, for example, configured to set (i.e., "change") the internal parameters PVT_config and CMP_config of the PVT sensor SNS.

[0142] As previously mentioned Figure 4 The aforementioned PVT sensor SNS can be configured to transmit a warning signal WS back to the decision unit via an internal bus BUS. The decision unit can perform countermeasures, such as shutting down the on-chip system SoC if the SV violation warning signal is set or the HV violation warning signal is maintained. The decision unit can typically be included in main unit core #1 or core #N.

[0143] Embodiments of a system-on-chip (SoC) including one or more PVT sensors (SNS) have now been described. The PVT sensors (SNS) are configured to detect anomalous changes in the temperature and / or supply voltage and / or semiconductor behavior of the SoC using a reference signal (a patterned digital signal) compared to a delayed version of a reference signal or a version propagated with a delayed clock. Elements introducing delays are sensitive to variations in process, supply voltage, and temperature (PVT).

[0144] By appropriately comparing the reference signal with its delayed version, it is possible to determine whether the change in operating conditions pertains to normal or abnormal operating conditions, and thus indicate unauthorized intrusion attempts or insecure external usage conditions.

[0145] If the PVT sensor detects an abnormal change in operating conditions, the system-on-chip (SoC) can be configured to activate one or more protection mechanisms for the SoC based on the specific application.

[0146] As a result, it is clear that this disclosure improves the security level and security of the system-on-a-chip (SoC).

Claims

1. A system-on-a-chip, comprising: Process voltage and temperature (PVT) sensors, including: A filter circuit configured to receive an input patterned digital signal, propagate the input patterned digital signal in a manner responsive to variations in semiconductor material processing, variations in the operating power supply voltage of the on-chip system, and variations in the operating temperature of the on-chip system, and generate an output patterned digital signal; and A digital comparator circuit is configured to compare the input patterned digital signal and the output patterned digital signal, and generate a warning signal when the comparison finds a difference between the input patterned digital signal and the output patterned digital signal.

2. The system-on-a-chip according to claim 1, wherein the filter circuit comprises: A first trigger circuit, configured to propagate the input patterned digital signal; as well as A first delay circuit is configured to delay the input patterned digital signal at the data input of the first trigger circuit by a first delay, the first delay depending on the process variation of the semiconductor material, the variation of the operating power supply voltage of the system-on-chip, and the variation of the operating temperature of the system-on-chip.

3. The system-on-a-chip according to claim 2, wherein the filter circuit further comprises: A second flip-flop circuit is configured to propagate the input patterned digital signal and is regulated by a clock signal; A second delay circuit is configured to delay the input patterned digital signal at the data input of the second trigger circuit by a second delay, the second delay depending on variations in the semiconductor material process, variations in the operating power supply voltage of the system-on-chip, and variations in the operating temperature of the system-on-chip. as well as A third delay circuit is configured to delay the clock signal at the clock input of the second flip-flop circuit by a third delay, the third delay depending on variations in the semiconductor material process, variations in the operating power supply voltage of the system-on-chip, and variations in the operating temperature of the system-on-chip. Compared to the second delay of the second delay circuit, the third delay of the third delay circuit is less dependent on variations in semiconductor material processing, variations in the operating power supply voltage of the on-chip system, and variations in the operating temperature of the on-chip system.

4. The system-on-a-chip according to claim 1, wherein the PVT sensor further includes a register configured to store internal parameters that determine the response of the filter circuit to changes in the semiconductor material process, changes in the operating power supply voltage of the system-on-a-chip, and changes in the operating temperature of the system-on-a-chip, wherein the internal parameters are configurable.

5. The system-on-a-chip according to claim 4, wherein the filter circuit comprises: A first trigger circuit, configured to propagate the patterned digital signal; as well as A first delay circuit is configured to delay the patterned digital signal at the data input of the first trigger circuit by a first delay, the first delay depending on variations in the semiconductor material's process, variations in the operating power supply voltage of the system-on-chip, and variations in the operating temperature of the system-on-chip; and The internal parameter includes the duration of the first delay.

6. The system-on-a-chip according to claim 5, wherein the filter circuit further comprises: A second flip-flop circuit, configured to propagate the patterned digital signal and regulated by a clock signal; A second delay circuit is configured to delay the patterned digital signal at the data input of the second trigger circuit by a second delay, the second delay depending on variations in the semiconductor material process, variations in the operating power supply voltage of the system-on-chip, and variations in the operating temperature of the system-on-chip. as well as A third delay circuit is configured to delay the clock signal at the clock input of the second flip-flop circuit by a third delay, the third delay depending on variations in the semiconductor material's process, variations in the operating power supply voltage of the on-chip system, and variations in the operating temperature of the on-chip system, wherein the third delay of the third delay circuit is less than the second delay of the second delay circuit; and The internal parameters include the durations of the first delay, the second delay, and the third delay.

7. The system-on-a-chip according to claim 1, wherein the system-on-a-chip comprises: Peripheral circuits; as well as An internal bus that links the peripheral circuits together in a corresponding bus domain; The PVT sensor is integrated into the bus domain in a manner that is physically close to the peripheral circuitry, and is provided with the same power supply voltage and the same clock signal as the peripheral circuitry of the bus domain.

8. The system-on-a-chip of claim 7, wherein the PVT sensor includes the same components as the components of the peripheral circuitry that are physically close to the PVT sensor.

9. The system-on-a-chip of claim 7, wherein the PVT sensor includes a bus interface configured to receive and transmit communications on the internal bus.

10. The system-on-a-chip according to claim 9, The PVT sensor includes a register configured to store internal parameters that determine the response of the filter circuit based on variations in the semiconductor material's process technology, variations in the operating power supply voltage of the on-chip system, and variations in the operating temperature of the on-chip system. These internal parameters are configurable. The system-on-a-chip includes a main unit configured to perform software operations, the software operations including transmitting configuration commands to the PVT sensor via the internal bus, the configuration commands being configured to set the internal parameters.

11. The system-on-a-chip of claim 9, wherein the PVT sensor is configured to transmit the warning signal to the decision unit via the internal bus.

12. A method for sensing process voltage-temperature (PVT) changes in an on-chip system, comprising: Generate input patterned digital signals; The input patterned digital signal is propagated by a filter circuit in response to changes in the semiconductor material process, changes in the operating power supply voltage of the on-chip system, and changes in the operating temperature of the on-chip system, so as to generate an output patterned digital signal. The input patterned digital signal is digitally compared with the output patterned digital signal; as well as A warning signal is generated in response to the detection of a difference between the input patterned digital signal and the output patterned digital signal.

13. The method of claim 12, wherein propagating the input patterned digital signal comprises: The input patterned digital signal is passed through the first trigger circuit; as well as A first delay is applied to the input patterned digital signal at the data input of the first trigger circuit; The first delay depends on variations in the semiconductor material manufacturing process, variations in the operating power supply voltage of the system-on-chip, and variations in the operating temperature of the system-on-chip.

14. The method of claim 13, wherein propagating the input patterned digital signal comprises: The input patterned digital signal is passed through a second trigger circuit that is adjusted by a clock signal; A second delay is applied to the input patterned digital signal at the data input of the second trigger circuit; as well as A third delay is applied to the clock signal at the clock input of the second flip-flop circuit; The second delay depends on variations in the semiconductor material's manufacturing process, variations in the operating power supply voltage of the system-on-chip, and variations in the operating temperature of the system-on-chip. Compared to the second delay, the third delay is less dependent on variations in semiconductor material processing, variations in the operating power supply voltage of the system-on-chip, and variations in the operating temperature of the system-on-chip.

15. The method of claim 12, further comprising storing internal parameters that determine the response of the filter circuit to changes in the semiconductor material process, changes in the operating power supply voltage of the system-on-chip, and changes in the operating temperature of the system-on-chip, wherein the internal parameters are configurable.

16. The method of claim 15, wherein propagating the input patterned digital signal comprises: The input patterned digital signal is passed through the first trigger circuit; as well as A first delay is applied to the input patterned digital signal at the data input of the first trigger circuit; The first delay depends on variations in the semiconductor material's manufacturing process, variations in the operating power supply voltage of the on-chip system, and variations in the operating temperature of the on-chip system; and The internal parameter includes the duration of the first delay.

17. The method of claim 16, wherein propagating the input patterned digital signal comprises: The input patterned digital signal is passed through a second trigger circuit controlled by a clock signal; A second delay is applied to the input patterned digital signal at the data input of the second trigger circuit; as well as A third delay is applied to the clock signal at the clock input of the second flip-flop circuit; The second delay depends on variations in the semiconductor material's manufacturing process, variations in the operating power supply voltage of the system-on-chip, and variations in the operating temperature of the system-on-chip. The third delay is less dependent on variations in semiconductor material processing, variations in the operating power supply voltage of the on-chip system, and variations in the operating temperature of the on-chip system; and The internal parameters include the durations of the first delay, the second delay, and the third delay.

18. The method of claim 12, wherein sensing the process voltage temperature (PVT) change is performed in physical proximity to the peripheral circuitry and is performed using the same power supply voltage and the same clock signal as the peripheral circuitry in the corresponding bus domain of the system-on-chip, the peripheral circuitry being linked together by internal buses in the bus domain.

19. The method of claim 18, wherein sensing the process voltage-temperature (PVT) change is performed using the same components as those physically close to the sensed peripheral circuitry.

20. The method of claim 18, further comprising storing internal parameters that determine the response of the filter circuit to variations in semiconductor material processing, variations in the operating supply voltage of the on-chip system, and variations in the operating temperature of the on-chip system, wherein the internal parameters are configurable; and Communication is received and transmitted on the internal bus via a bus interface, including communication of configuration commands for configuring the internal parameters transmitted from the master unit of the system-on-chip configured to perform software operations.

21. The method of claim 20, further comprising transmitting the warning signal to the decision unit of the system-on-chip via the internal bus.

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