Projection device and control method of projection device

Abstract

The projection device and its control method ensure sufficient timing for writing data signals without causing display discrepancies at shifted positions. In the pixel circuit with a first and a second capacitor element, during the write subframe (W_f1), the voltage corresponding to the grayscale is held in the first capacitor element. During the vertical scan retrace (Vblnk) following the write subframe (W_f1), multiple OLEDs are turned off. During the emission subframe (L_f1) following the vertical scan retrace (Vblnk), the current corresponding to the voltage held in the first capacitor element is supplied to the OLED, and the voltage corresponding to the grayscale is held in the second capacitor element. In the optical path shifting element, the optical path shifts during the vertical scan retrace (Vblnk) and stabilizes in the emission subframe (L_f1).

Description

Technical Field

[0001] The present invention relates to, for example, a projection device and a method for controlling a projection device. Background Technology

[0002] In projection devices that magnify the displayed image on a display panel and project it onto a screen or similar surface, there is a known technique that uses a light path shifting element to shift the light path emitted from the display panel (see, for example, Patent Documents 1 and 2). According to this technique, a user can see an image whose resolution is virtually enhanced.

[0003] Patent Document 1: Japanese Patent Publication No. 2007-500868

[0004] Patent Document 2: Japanese Patent Application Publication No. 2011-158589

[0005] In display panels, sequential line driving is the mainstream method, switching the display content with each scan line write. On the other hand, the image as a whole is shifted due to the shifting of the optical path by optical path shifting elements. Therefore, if a write operation is performed near the center of the screen, and the optical path is shifted, the upper half of the screen will show the content after the switch, while the lower half will show the content before the switch, resulting in a mixed view of the image before and after the switch.

[0006] In addition, in the structure that shifts the optical path after horizontal scanning, in order to ensure that the switched image is seen, all scan lines need to be written in a short time, resulting in insufficient writing. Summary of the Invention

[0007] This disclosure discloses a projection device comprising: a display panel including a plurality of pixel circuits; and a light path shifting element, the plurality of pixel circuits each having: a first capacitor element and a second capacitor element; and a light-emitting element that emits light with brightness corresponding to current in a predetermined direction. The light path shifting element is capable of shifting the light path emitted from the light-emitting element to the first light path and the second light path. In the plurality of pixel circuits, during a first period, a voltage corresponding to the current supplied to the light-emitting element is maintained at the first capacitor element; during an off-state period following the first period, the light-emitting element is off; during a second period following the off-state period, a current corresponding to the voltage maintained at the first capacitor element is supplied to the light-emitting element, and a voltage corresponding to the current supplied to the light-emitting element is maintained at the second capacitor element. In the light path shifting element, during the off-state period, the light path shifts from the first light path to the second light path, and during the second period, the second light path is maintained. Attached Figure Description

[0008] Figure 1This is a diagram showing the structure of the projection device according to the first embodiment.

[0009] Figure 2 It is a three-dimensional diagram showing the structure of the display panel used in a projection device.

[0010] Figure 3 These are examples of panel pixels and sub-panel pixels in a projection device.

[0011] Figure 4 It is a block diagram representing the electrical structure of the projection device.

[0012] Figure 5 It is a diagram showing the structure of a frame in a projection device.

[0013] Figure 6 It is a diagram showing the correspondence between input pixels and panel pixels.

[0014] Figure 7 It is a diagram showing the relationship between each subframe and the optical path shift.

[0015] Figure 8 It is a diagram representing the projected pixels as seen through a projection device.

[0016] Figure 9 It is a block diagram showing the electrical structure of the display panel.

[0017] Figure 10 This is a diagram showing the pixel circuitry in a display panel.

[0018] Figure 11 It is a timing diagram representing control signals for optical path shifting elements, etc.

[0019] Figure 12 It is a timing diagram that represents the operation of the display panel, etc.

[0020] Figure 13 It is a timing diagram that represents the operation of the display panel, etc.

[0021] Figure 14 This is a diagram showing the equivalent circuit of the pixel circuit in the first embodiment.

[0022] Figure 15 It is a diagram used to illustrate the projected image.

[0023] Figure 16 This is a diagram used to illustrate the improvement in display quality of the implementation method.

[0024] Figure 17 This is a diagram showing the pixel circuit of the display panel in the second embodiment.

[0025] Figure 18 It is a timing diagram that represents the operation of the display panel, etc.

[0026] Figure 19 It is a timing diagram that represents the operation of the display panel, etc.

[0027] Figure 20 This is a diagram showing the equivalent circuit of the pixel circuit in the second embodiment.

[0028] Figure 21 It is a timing diagram showing the control signals, etc., of the optical path shifting element for the modified example.

[0029] Figure 22 This is a timing diagram showing the operation of the display panel of the first comparative example.

[0030] Figure 23 This is a timing diagram showing the operation of the display panel in the second comparative example.

[0031] Label Explanation

[0032] 1: Projection device; 10: Display panel; 12: Scan line; 14: Data line; 100: Display area; 110R, 110G, 110B: Pixel circuit; 116: Power supply wiring (high-order power supply wiring); 118: Power supply wiring (low-order power supply wiring); 121: Transistor (driving transistor); 122a: Transistor (first switching element); 122b: Transistor (second switching element); 123a: Transistor (third switching element); 123b: Transistor (fourth switching element); 124: Transistor (fifth switching element); 126: Transistor (sixth switching element); C1a: Capacitor (first capacitor); C1b: Capacitor (second capacitor); C2: Capacitor (third capacitor). Detailed Implementation

[0033] Hereinafter, the display panel of an embodiment of the present invention will be described with reference to the accompanying drawings.

[0034] Furthermore, in each drawing, the size and scale of each part are appropriately different from the actual dimensions. Additionally, the embodiments described below are preferred examples, and therefore various technically preferred limitations are included. However, unless otherwise specified in the following description, the scope of the invention is not limited to these methods.

[0035] <First Implementation>

[0036] Figure 1 This is a diagram showing the structure of the projection device 1 according to the first embodiment. Figure 2This is a perspective view showing the structure of the display panel 10 applied to the projection device 1. The projection device 1 magnifies the color image generated by the display panel 10 and projects it onto the screen Scr. The display panel 10 has a light-emitting element, so the projection device 1 does not require an additional light source, enabling miniaturization. Furthermore, the projection device 1 can display high-resolution color images through the optical path shifting element 20.

[0037] Display panel 10 is a miniature display that generates color images. In this embodiment, display panel 10 is used, which employs a single board to apply an OLED to the light-emitting element. OLED is an abbreviation for Organic Light Emitting Diode.

[0038] In the display panel 10, multiple pixel circuits and driving circuits for driving the pixel circuits are formed on a semiconductor substrate. A silicon substrate is typical as the semiconductor substrate, but other semiconductor substrates may also be used.

[0039] like Figure 1 As shown, emitted light from display panel 10 is incident on light path shifting element 20. Projection lens 34 magnifies the projected image Img transmitted through light path shifting element 20 and projects it onto screen Scr.

[0040] The optical path shifting element 20 shifts the emitted light from the display panel 10. Specifically, the optical path shifting element 20 can, according to the control described later, shift the projected image Img projected onto the screen Scr in the left-right and up-down directions when observing the screen Scr, which is the projection surface.

[0041] For ease of explanation, it is necessary to distinguish between the pixels of the projected image Img projected onto the screen Scr and the pixels of the display panel 10. Therefore, in this description, the pixels of the projected image Img projected onto the screen Scr will be labeled as projected pixels, and the pixels displayed by the display panel 10 will be labeled as panel pixels.

[0042] like Figure 2 As shown, the display panel 10 is housed in a frame-shaped housing 192 with an opening 191. An FPC substrate 194 is connected to one end of the display panel 10. FPC stands for Flexible Printed Circuits. Multiple terminals 196 are provided at the other end of the FPC substrate 194. These terminals 196 are connected to the image processing circuitry described below.

[0043] Furthermore, in the figure, the X direction is the extension direction of the scan lines in the display panel 10, representing the horizontal direction of the displayed pixels, and the Y direction is the extension direction of the data lines, representing the vertical direction of the displayed image. Additionally, the two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction represents the emission direction of light emitted from the OLED, which is perpendicular to both the X and Y directions.

[0044] Figure 3 This is a diagram showing the structure of panel pixels 11 in display panel 10. As shown in the diagram, one panel pixel 11 is composed of a red sub-panel pixel 11R, a green sub-panel pixel 11G, and a blue sub-panel pixel 11B.

[0045] Furthermore, in the display panel 10, the panel pixels 11 are approximately square in shape when viewed from above, and are arranged with a spacing p in both the X direction (horizontal) and Y direction (vertical). Additionally, the reference numeral 11b indicates the center of gravity of the panel pixels 11.

[0046] In addition, the panel pixels 11 in the display panel 10 are arranged in a matrix with m rows and n columns, which will be described in detail later. m and n are both integers greater than 2.

[0047] Figure 4 This is a block diagram showing the electrical structure of the projection device 1. As shown in the figure, in addition to the aforementioned display panel 10 and optical path shifting element 20, the projection device 1 also includes an image processing circuit 40.

[0048] Image data Vde-in is supplied synchronously from the host device 5 to the image processing circuit 40 along with the synchronization signal Sync. Image data Vde-in represents the image displayed by the projection device 1; specifically, for example, it specifies the grayscale level of a color image in one frame of the image using 8 bits for each of red (R), green (G), and blue (B). For ease of explanation, the pixels of the color image represented by image data Vde-in are labeled as input pixels.

[0049] The synchronization signal Sync includes a vertical synchronization signal indicating the start of vertical scanning in the image data Vid-in, a horizontal synchronization signal indicating the start of horizontal scanning, and a clock signal indicating the timing of one pixel in the image data Vid-in.

[0050] In this embodiment, the arrangement of display pixels specified by the image data Vde-in is, for example, twice as large in the vertical direction and twice as large in the horizontal direction compared to the arrangement of panel pixels in the display panel 10. Specifically, the input pixels are arranged in vertical (2m) rows × horizontal (2n) columns.

[0051] In this embodiment, the four input pixels specified by the image data Vde-in are represented by one panel pixel in the display panel 10. Therefore, the specific method used here will be described first.

[0052] In this embodiment, in order to view the projected image at a resolution higher than that of the panel pixels, the emitted light path (the position of the projected pixel) from the display panel 10 is shifted by the optical path shifting element 20. Specifically, when displaying an image of one frame via image data Vde-in, the period for displaying that one frame is divided into four subframes, and the position of the projected pixel is shifted for each subframe. Through this shifting, one panel pixel is perceived as being displayed as four input pixels within one frame (four subframes).

[0053] Figure 5 This is a diagram used to illustrate the relationship between frames and subframes in this embodiment. As shown in the diagram, in this embodiment, one frame F is divided into four subframes, and these four subframes are assigned the symbols f1, f2, f3, and f4 in chronological order.

[0054] Furthermore, when the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60Hz, the duration of frame F is 16.7 milliseconds, which is one cycle. In this case, the durations of subframes f1 to f4 are 4.17 milliseconds each.

[0055] The relationship between the positions of the input pixels whose grayscale level is specified by the image data Vde-in, the panel pixels of the display panel 10, and the projected pixels shifted by the optical path shifting element 20 will be explained. Furthermore, the optical path shifting element 20 shifts the projected image Img projected onto the screen Scr in the left-right and up-down directions as described above; however, for convenience, the amount of this shift will be explained in terms of the size of the projected pixels or panel pixels in the screen Scr.

[0056] Figure 6 The left column shows a map extracted from only a portion of the image data represented by Vde-in. Additionally, Figure 6 The right column is a graph representing the arrangement of the extracted panel pixels that corresponds to the arrangement of the input pixels in the left column.

[0057] exist Figure 6 For convenience, the input pixels of the image data Vde-in are labeled as follows: A1 to A6 for the first row, B1 to B6 for the second row, C1 to C6 for the third row, D1 to D6 for the fourth row, E1 to E6 for the fifth row, and F1 to F6 for the sixth row.

[0058] exist Figure 6In the arrangement of the panel pixels 11, for convenience, the first row is assigned a1 to a3, the second row is assigned b1 to b3, and the third row is assigned c1 to c3 as labels.

[0059] exist Figure 6 The image shows a case where four input pixels, arranged in a 2×2 grid (represented by thick outlines), are represented by a single panel pixel 11, in an arrangement of input pixels represented by image data Vde-in.

[0060] Figure 7 This is a diagram showing which input pixel 11 of the display panel 10 in the projection device 1 will be shifted to which position and displayed, as indicated by the image data Vde-in.

[0061] In detail, Figure 7 It means Figure 6 The 9 panels in the right column will be 11 pixels. Figure 6 The image is displayed by showing which input pixel in the left column is shifted to which position in subframes f1 to f4. The optical path shifting element 20 is controlled to shift the optical path to the 1st to 4th optical paths in subframes f1 to f4. Figure 7 This indicates that the optical path is shifted to the first to fourth optical paths, and the image is projected to positions (1) to (4).

[0062] Figure 7 The first paragraph indicates that in subframe f1, panel pixel 11 at position (1) represents the odd-numbered rows and odd-numbered columns of the 2×2 input pixels corresponding to that panel pixel 11, which are shaded. For example, panel pixel 11 at position a1 projects input pixel A1 onto the screen Scr to represent it at position (1). The optical path is the first optical path. Furthermore, panel pixel 11 representing input pixel A1 means that the RGB OLED contained in panel pixel 11 emits light with brightness corresponding to the grayscale level of input pixel A1 specified by image data Vde-in.

[0063] Figure 7 The second segment indicates that in subframe f2, panel pixel 11 at position (2) represents the even-numbered row and odd-numbered column of the 2×2 input pixels corresponding to panel pixel 11, which is shaded. For example, panel pixel 11 at position a1 projects input pixel B1 onto position (2) to represent it. Position (2) is the position after shifting position (1) by half the distance p (p / 2) in the Y direction. The optical path is the second optical path.

[0064] Figure 7The third segment indicates that in subframe f3, panel pixel 11 at position (3) represents the even-numbered row and even-numbered column of the 2×2 input pixels corresponding to panel pixel 11, which is shaded. For example, panel pixel 11 at position a1 projects input pixel B2 onto position (3) to represent it. Position (3) is the position after shifting position (2) by half the distance p (p / 2) in the X direction. The optical path is the third optical path.

[0065] Figure 7 The fourth segment indicates that in subframe f4, panel pixel 11 at position (4) represents the odd-row, even-column input pixel in the 2×2 input pixels corresponding to that panel pixel 11, which is shaded. For example, panel pixel 11 at position a1 projects input pixel A2 onto position (4) to represent it. Position (4) is the position after shifting position (3) in the opposite direction of the Y direction by half a distance p (p / 2). The optical path is the fourth optical path.

[0066] Additionally, when transitioning from subframe f4 to the next subframe f1, the projected pixel moves from position (4) in the opposite direction of the X direction by half the distance p, returning to position (1). The optical path returns to the first optical path via the optical path shifting element 20.

[0067] If we focus on the centroid 11g of panel pixel 11, then the centroid 11g shifts by half the distance p in positions (1) to (4). Therefore, from subframes f1 to f4, as Figure 8 As shown, the centers of gravity 11g are arranged at a spacing of p / 2 in the Y and X directions, respectively.

[0068] Therefore, although the panel pixels 11 are arranged in m rows × n columns in the display panel 10, the projection pixels can be regarded as being arranged in (2m) rows × (2n) columns through the shifting of the optical path shifting element 20. In other words, in this embodiment, the resolution of the display panel 10 is virtually increased to twice the vertical and twice the horizontal, totaling four times.

[0069] Return to Figure 4 To explain, the image processing circuit 40 separates the image data Vde-in supplied from the host device 5 into each subframe f1 to f4 and supplies it to the display panel 10 as image data Vid. Specifically, the image processing circuit 40 temporarily stores the image data Vde-in, and for each subframe f1 to f4 in the stored image data Vde-in, reads the image data Vde-in corresponding to the input pixel of the corresponding subframe, and supplies it to the display panel 10 as image data Vid.

[0070] The image processing circuit 40 outputs control signals Ctr for controlling the drive of the display panel 10 according to each subframe f1 to f4.

[0071] In addition, the image processing circuit 40 outputs control signals Psh_X and Psh_Y for controlling the optical path shifting element 20 for each subframe f1 to f4.

[0072] Figure 9 This diagram illustrates the electrical structure of the display panel 10. As shown in the diagram, the display panel 10 is roughly divided into a control circuit 50, a data signal output circuit 60, and a scan line drive circuit 120.

[0073] In the display panel 10, the m rows of scan lines 12 are arranged along the X direction in the figure, and the (3n) columns of data lines 14 are arranged along the Y direction and in a manner that keeps them electrically insulated from each scan line 12.

[0074] To distinguish the rows in scan line 12, they are sequentially referred to as rows 1, 2, 3, ..., (m-1), and m from top to bottom in the diagram. Additionally, regarding scan line 12, for general reference when rows are not explicitly defined, an integer i, greater than 1 and less than m, is sometimes used to represent the i-th row.

[0075] Furthermore, to distinguish the columns in data line 14, they are sequentially named 1, 2, 3, ..., (3n-2), (3n-1), and (3n) from left to right in the diagram. Additionally, data line 14 is grouped into groups of three. To generalize the explanation of the groups, when using an integer j greater than 1 and less than n, data line 14 with three columns—column (3j-2), column (3j-1), and column (3j)—belongs to the j-th group from the left.

[0076] Pixel circuits 110R, 110G, and 110B are configured corresponding to the scan lines 12 arranged in m rows and the data lines 14 arranged in (3n) columns. Specifically, pixel circuit 110R is configured corresponding to the intersection of the scan line 12 in the i-th row and the data line 14 in the (3j-2)-th column. Pixel circuit 110G is configured corresponding to the intersection of the scan line 12 in the i-th row and the data line 14 in the (3j-1)-th column. Pixel circuit 110B is configured corresponding to the intersection of the scan line 12 in the i-th row and the data line 14 in the (3j)-th column.

[0077] The area where the pixel circuits 110R, 110G, and 110B are arranged in m rows × (3n) columns is the display area 100.

[0078] Pixel circuit 110R includes an OLED that emits red light, pixel circuit 110G includes an OLED that emits green light, and pixel circuit 110B includes an OLED that emits blue light. Therefore, sub-panel pixel 11R is represented by the emission of light from the OLED included in pixel circuit 110R, sub-panel pixel 11G is represented by the emission of light from the OLED included in pixel circuit 110G, and sub-panel pixel 11B is represented by the emission of light from the OLED included in pixel circuit 110B.

[0079] Furthermore, the pixel circuits 110R, 110B, and 110G are used to sequentially represent the sub-panel pixels 11R, 11G, and 11B, so strictly speaking they should be called sub-pixel circuits, but for convenience, they are referred to as pixel circuits in this description.

[0080] The control circuit 50 controls each component based on the image data Vid supplied from the image processing circuit 40 and the control signal Ctr. The control circuit 50 generates various control signals, the details of which will be described later.

[0081] The image data Vde-in specifies the grayscale level of each input pixel using 8 bits for each RGB, as described above. However, the brightness characteristics specified by the grayscale level may not be consistent with the brightness characteristics of the OLED contained in the panel pixel 11.

[0082] Therefore, for the grayscale level specified by the image data Vde-in, in order to enable the OLED to emit light at a brightness corresponding to that grayscale level, the control circuit 50 upconverts each of the 8 bits of RGB in the image data Vde-in to 10 bits, for example, in this embodiment, and outputs it as image data Vdata specifying the brightness of the OLED for that RGB level. In this upconversion, a lookup table is used that pre-stores the correspondence between the 8 bits of the input image data Vde-in and the 10 bits of the output image data Vdata for each RGB level.

[0083] In addition, although Figure 9 Although not shown, the control circuit 50 supplies the control signal Enb to all pixel circuits 110R, 110G, and 110B in a common manner.

[0084] The scan line driving circuit 120 is used to drive the pixel circuits 110R, 110G, and 110B arranged in m rows (3n columns) according to the control of the control circuit 50. Specifically, the scan line driving circuit 120 supplies scan signals Scan(1), Scan(2), ..., Scan(m-1), Scan(m) sequentially to the scan lines 12 in rows 1, 2, 3, ..., (m-1), and m. Typically, the scan signal supplied to the scan line 12 in row i is denoted as Scan(i).

[0085] In addition, Figure 9 In order to avoid complicating the attached diagram, the number of scan lines 12 in row 1 is set to 1. However, in reality, the number of scan lines for row 1 is "2". That is, in fact, scan signals Scan_a(i) and Scan_b(i) are supplied to the two scan lines 12 corresponding to row i.

[0086] The data signal output circuit 60 is a circuit that outputs a data signal with a voltage corresponding to the grayscale level to the pixel circuits 110R, 110G, and 110B located in the row selected by the scan line drive circuit 120. Specifically, the data signal output circuit 60 latches one row of image data Vdata supplied from the control circuit 50, converts the latched row of image data Vdata into an analog data signal, and outputs it as a data signal to the corresponding data line 14.

[0087] In addition, the potentials of data lines 14 in columns 1, 2, 3, ..., (3n-2), (3n-1), and 3n are described in sequence as Vd(1), Vd(2), Vd(3), ..., Vd(3n-2), Vd(3n-1), and Vd(3n).

[0088] Furthermore, in this specification, the reference for zero voltage is the logic level L (ground potential), but apart from the voltage between two points (threshold voltage), this specification does not strictly distinguish between potential and voltage. Additionally, in this specification, power supply refers to a voltage or potential that remains approximately constant over time.

[0089] The electrical structures of pixel circuits 110R, 110G, and 110B are identical. Therefore, the electrical structures of pixel circuits 110R, 110G, and 110B will be described using pixel circuit 110R, located in row i (3j-2) as an example.

[0090] Figure 10 This is a circuit diagram showing the electrical structure of the pixel circuit 110R located in row i (3j-2). As shown, the pixel circuit 110R includes an OLED 130, P-channel MOS transistors 121, 122a, 122b, 123a, 123b, and 124, and capacitors C1a and C1b. Furthermore, MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor.

[0091] In the pixel circuits 110R, 110G, and 110B of the i-th row, a scan signal Scan_a(i) is supplied via one of the two scan lines 12a corresponding to the i-th row, and a scan signal Scan_b(i) is supplied via the other scan line 12b.

[0092] OLED 130 is a light-emitting element formed by sandwiching a light-emitting functional layer 132 between pixel electrodes 131 and a common electrode 133. The pixel electrodes 131 function as the anode, and the common electrode 133 functions as the cathode. Furthermore, the common electrode 133 exhibits both light reflectivity and light transmittance. In OLED 130, when current flows from the anode towards the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, producing white light.

[0093] Furthermore, when pixel circuits 110R, 110G, and 110B are observed individually, the generated white light resonates in an optical resonator (not shown) composed of a reflective layer and a semi-reflective / semi-transmissive layer, and is emitted at resonant wavelengths corresponding to the colors red, green, and blue, respectively. A color filter corresponding to this color is provided in the Z direction, which is the emission direction of the light from the optical resonator. Therefore, the emitted light from OLED 130 is seen after being colored based on the optical resonator and the color filter. (Illustration of the optical resonator is omitted.)

[0094] In the pixel circuit 110R of row i (3j-2) columns, the source node of transistor 122a is connected to the data line 14 of column (3j-2), its drain node is connected to one end of capacitor element C1a and the source node of transistor 123a, and its gate node is connected to scan line 12a. The source node of transistor 122b is connected to the data line 14 of column j, its drain node is connected to one end of capacitor element C1b and the source node of transistor 123b, and its gate node is connected to scan line 12b. The other ends of capacitor element C1a and capacitor element C1b are connected to the power supply wiring 116 supplied with the high-order power supply potential ELvdd.

[0095] In transistor 123a, the gate node is connected to control line 13a, which is supplied with the selection signal Sel_a. In transistor 123b, the gate node is connected to control line 13b, which is supplied with the selection signal Sel_b. The drain nodes of transistors 123a and 123b are connected to the gate node g of transistor 121.

[0096] The source node s of transistor 121 is connected to power supply wiring 116, and the drain node d is connected to the source node of transistor 124. The gate node of transistor 124 is supplied with a control signal Enb, and the drain node is connected to the pixel electrode 131 of OLED 130. Furthermore, in OLED 130, a low-level power supply potential ELvss is supplied to the common electrode 133 via power supply wiring 118.

[0097] In addition, in this description, "electrical connection" or simply "connection" refers to a direct or indirect connection or combination between two or more elements, and also includes, for example, in a semiconductor substrate, the connection between two or more elements is not direct but is achieved through different wiring layers and contact holes.

[0098] Figure 11 This is a timing diagram used to illustrate the operation of the optical path shifting element 20. The image processing circuit 40 supplies control signals Psh_Y and Psh_X to the optical path shifting element 20, causing the projected image Img on the screen Scr to shift in the Y and X directions, respectively.

[0099] In detail, the control signal Psh_Y shifts the position of the projected image Img relative to the screen Scr in the Y direction, and the control signal Psh_X shifts the position of the projected image Img in the X direction. The control signals Psh_Y and Psh_X are respectively set to voltages of -A or +A. The optical path changes to optical path 1 through 4 depending on the voltage of the control signals Psh_Y or Psh_X. When the voltages of the control signals Psh_Y and Psh_X do not change, the optical path is maintained.

[0100] Here, if the voltage of the control signal Psh_Y is -A and the voltage of the control signal Psh_X is -A, then the projected image Img in the screen Scr is at position (1). For convenience, let the coordinates Pps_Y and Pps_X of a certain projected pixel of the projected image Img at position (1) (e.g., the projected pixel at the upper left end of the display area 100) be reference zero. The optical path in this case is the first optical path.

[0101] When the voltage change of the control signal Psh_Y is +A, the position of the projected pixel shifts by half the distance p in the Y direction, and the coordinate position Pps_Y becomes p / 2. When the voltage change of the control signal Psh_X is +A, the position of the projected pixel shifts by half the distance p in the X direction, and the coordinate position Pps_X becomes p / 2.

[0102] Therefore, if the voltage of the control signal Psh_Y is -A and the voltage of the control signal Psh_X is -A, the projected pixel is located at position (1); if the voltage of the control signal Psh_Y is +A and the voltage of the control signal Psh_X is -A, the projected pixel is located at position (2). Additionally, if the voltage of the control signal Psh_Y is +A and the voltage of the control signal Psh_X is +A, it becomes position (3); if the voltage of the control signal Psh_Y is -A and the voltage of the control signal Psh_X is +A, it becomes position (4).

[0103] Furthermore, even if the control signals Psh_Y and Psh_X change to voltages -A or +A, the position of the projected pixel (projected image Img) shifted by the optical path shifting element 20 is not immediately determined, but is accompanied by a delay of t1. That is, the position of the projected pixel stabilizes only after a period t1 has elapsed since the voltage change of the control signals Psh_Y or Psh_X.

[0104] Furthermore, the control circuit 50 outputs a control signal Enb corresponding to the output changes of the control signals Psh_Y and Psh_X based on the image processing circuit 40. That is, the control circuit 50 outputs a control signal Enb that is at level H during period t2, which includes the aforementioned period t1, and at level L during other periods.

[0105] Figure 12 and Figure 13 This is a timing diagram used to illustrate the operation of projection device 1.

[0106] As described above, one frame F consists of four subframes f1 to f4, corresponding to the first to fourth periods, respectively. In this embodiment, from the viewpoint of data writing, the subframe consists of write subframes W_f1 to W_f4 for writing data signals to pixel circuits 110R, 110G, and 110B, and the vertical scan retrace period Vblnk. Furthermore, in this embodiment, from the viewpoint of light emission, the subframe consists of light emission subframes L_f1 to L_f4 for allowing current based on the voltage of the written data signal to flow through the OLED 130, and the vertical scan retrace period Vblnk.

[0107] In detail, the writing subframes W_f1 to W_f4 are used to sequentially write the data signals corresponding to the subframes f1 to f4 into the pixel circuits 110R, 110G, and 110B, and the emitting subframes L_f1 to L_f4 are used to sequentially cause the OLED 130 to emit light by allowing current based on the voltage of the data signals written in the writing subframes W_f1 to W_f4 to flow through it.

[0108] In this embodiment, periods 1 to 4 correspond to writing subframes W_f1 to Wf4 or emitting subframes L_f4, L_f1 to L_f3, respectively. The vertical scan retrace period Vblnk corresponds to the extinguishing period.

[0109] Furthermore, in this embodiment, the periods for writing subframes W_f1 to W_f4 are sequentially aligned with the periods for emitting subframes L_f4 and Lf1 to L_f3, respectively. Additionally, writing refers to the operation of maintaining the voltage of the data signal at capacitor elements C1a or C1b.

[0110] In write subframes W_f1 and W_f3, the scan signals Scan_a(1), Scan_a(2), ..., Scan_a(m-1), Scan_a(m) are sequentially and exclusively at the L level during each horizontal scan period. Additionally, in write subframes W_f2 and W_f4, the scan signals Scan_b(1), Scan_b(2), ..., Scan_b(m-1), Scan_b(m) are sequentially and exclusively at the L level during each horizontal scan period.

[0111] In this embodiment, the period from when the scan signal Scan_a(1) changes to L level to when the scan signal Scan_a(m) changes to H level in the write subframe W_f1 (or W_f3), and the period from when the scan signal Scan_b(1) changes to L level to when the scan signal Scan_b(m) changes to H level in the write subframe W_f2 (or W_f4) are called the vertical effective scan period.

[0112] In addition, the period other than the effective vertical scan period, specifically, the period from when the scan signal Scan_a(m) changes to H level in the write subframe W_f1 (or W_f3) until the scan signal Scan_b(1) changes to L level in the write subframe W_f2 (or W_f4), and the period from when the scan signal Scan_b(m) changes to H level in the write subframe W_f2 (or W_f4) until the scan signal Scan_a(1) changes to L level in the write subframe W_f3 (or W_f1) is the vertical scan retrace period Vblnk.

[0113] In this embodiment, the control signal Enb is at level L during the luminous subframes L_f2, L_f3, L_f4, and L_f1, which are the active vertical scan periods, and at level H during the vertical scan retrace periods, which are other periods. Furthermore, the vertical scan retrace period corresponds to the aforementioned period t2.

[0114] Furthermore, the control signal Psh_Y for the optical path shifting element 20 becomes voltage -A at the end of writing subframe W_f4 and voltage +A at the end of writing subframe W_f2. The control signal Psh_X becomes voltage -A at the end of writing subframe W_f1 and voltage +A at the end of writing subframe W_f3.

[0115] Although Figure 12 and Figure 13 The process is omitted, but at the beginning of the vertical scan retrace period, after the voltage change of the control signal Psh_Y or Psh_X, until the beginning of the next effective vertical scan period, the optical path shifting element 20 completes the shifting of the optical path, and this state is maintained based on the stable position of the projected pixel.

[0116] In the first embodiment, in the writing subframes W_f1 and W_f3 (light-emitting subframes L_f4 and L_f2), the selection signal Sel_a is at level H and the selection signal Sel_b is at level L. In the writing subframes W_f2 and W_f4 (light-emitting subframes L_f1 and L_f3), the selection signal Sel_a is at level L and the selection signal Sel_b is at level H.

[0117] Additionally, during the vertical scan retrace after writing subframes W_f1 and W_f3, the selection signal Sel_b changes from L to H level in time first, while the selection signal Sel_a changes from H to L level later in time. During the vertical scan retrace after writing subframes W_f2 and W_f4, the selection signal Sel_a changes from L to H level in time first, while the selection signal Sel_b changes from H to L level later in time.

[0118] The operation of the projection device 1, which is written into subframe W_f1, is explained.

[0119] The following three actions are mainly performed when writing subframe W_f1.

[0120] In detail, in writing subframe W_f1, firstly, the operation is performed to make the capacitor element C1a of the pixel circuits 110R, 110G, and 110B hold the odd-numbered rows and odd-numbered columns of the input pixels arranged in vertical (2m) rows × horizontal (2n) columns in the image data Vde-in as image data Vdata.

[0121] In the subframe W_f1, secondly, the action of shifting the projected pixel to position (4) via the optical path shifting element 20 is performed. The optical path is shifted to the fourth optical path.

[0122] In writing subframe W_f1, i.e., light-emitting subframe L_f4, the third step is to supply the current corresponding to the voltage of the capacitor element C1b held in the pixel circuits 110R, 110G, and 110B to the OLED 130.

[0123] If we describe the first action in detail, in writing subframe W_f1, the image processing circuit 40 outputs the odd-numbered rows and odd-numbered columns of the input pixels arranged in vertical (2m) rows × horizontal (2n) columns from the image data Vde-in supplied from the host device 5 as image data Vid. Furthermore, the odd-numbered rows and odd-numbered columns of the input pixels arranged in vertical (2m) rows × horizontal (2n) columns are... Figure 7 The first segment (subframe f1) includes input pixels with added shadow lines.

[0124] In the subframe W_f1, the control circuit 50 is timed to match the scanning signals Scan_a(1)~Scan_a(m) sequentially to L level, and converts the image data Vde-in line by line into image data Vdata and outputs it.

[0125] In addition, when writing to subframe W_f1, for example during the period when the scan signal Scan_a(i) becomes L level, the data signal output circuit 60 converts the gray levels of subpanel pixels 11R, 11G, 11B in the i-th row and 1-th row (3n) columns represented by image data Vdata into analog potentials Vd(1) to Vd(3n), and outputs them as data signals to the data lines 14 of the 1st to (3n) columns.

[0126] For column (3j-2), the data signal output circuit 60 converts the gray level in the image data Vdata corresponding to the sub-panel pixel 11R in row (3j-2) into the potential Vd(3j-2) of the analog signal, and outputs it as a data signal to the data line 14 in column (3j-2).

[0127] Furthermore, the gray level corresponding to sub-panel pixel 11R in row i (3j-2) refers to converting the 8-bit gray level corresponding to the R component in the input pixel in row (2i-1) and column j of the input pixels arranged in vertical (2m) × horizontal (2n) columns into a 10-bit gray level.

[0128] When the scan signal Scan_a(i) becomes low level, transistor 122a is turned on in pixel circuit 110 in row i (3j-2) column. During the period when the scan signal Scan_a(i) is low level, the scan signal Scan_b(i) is high level, therefore transistor 122b is turned off in pixel circuit 110 in row i (3j-2) column.

[0129] Therefore, the data signal at potential Vd(3j-2) is held by capacitor element C1a sequentially via data line 14 in column (3j-2) and transistor 122a in pixel circuit 110R in row (3j-2).

[0130] Here, the pixel circuit 110R in row i and column (3j-2) is described, but the same applies to the pixel circuits 110R, 110G, and 110B in columns other than column (3j-2) in row i. In addition, the data signal is held in capacitor element C1a.

[0131] In addition, in this description, the "on / conducting state" of a switching element or transistor refers to a low-impedance state where the two ends of the switching element or the source / drain node in the transistor are electrically closed. Conversely, the "off / turn-off state" of a switching element or transistor refers to a high-impedance state where the two ends of the switching element or the source / drain node are electrically disconnected.

[0132] In the subframe W_f1, even for rows other than the i-th row, the scan signals Scan_a(1) to Scan(m) are sequentially and exclusively at the L level, thus the data signals are held in the capacitor element C1a in all pixel circuits 110R, 110G, and 110B.

[0133] If we were to describe the second action in detail, after writing subframe W_f4, the image processing circuit 40 sets the control signal Psh_Y to voltage -A and the control signal Psh_X to voltage +A. Therefore, in the luminous subframe L_f4, the projected pixel is shifted to position (4) and stabilized. The optical path is shifted to the fourth optical path, maintaining this state.

[0134] If we were to describe the third action in detail, in the written subframe W_f1, the selection signal Sel_a is at level H and the selection signal Sel_b is at level L. Therefore, in all pixel circuits 110R, 110G, and 110B, transistor 123a is in the off state and transistor 123b is in the on state.

[0135] Therefore, in all pixel circuits 110R, 110G, and 110B, one end of capacitor element C1b is electrically connected to the gate node g of transistor 121 via transistor 123b, thus applying a voltage maintained in capacitor element C1b between the gate node and source node in transistor 121.

[0136] Additionally, in the write subframe W_f1 (light-emitting subframe L_f4), the control signal Enb is at level L, so transistor 124 becomes on.

[0137] Therefore, in the light-emitting subframe L_f4, in all pixel circuits 110R, 110G, and 110B, transistor 121 causes the voltage between the gate node and the source node, i.e., the current corresponding to the gray level of the pixel, to flow through OLED 130.

[0138] The voltage maintained at capacitor C1b is based on the data signal supplied via data line 14 in the write subframe W_f4 of the previous frame. Therefore, in the light-emitting subframe L_f4, each OLED 130 in all pixel circuits 110R, 110G, and 110B emits light with a brightness corresponding to the sub-panel pixels 11R, 11G, and 11B of subframe f4. Furthermore, the projected pixel based on this light emission is seen at position (4) on the screen Scr.

[0139] The operation of the projection device 1 written into subframe W_f2 is the same as the operation of writing into subframe W_f1, except in the following aspects.

[0140] That is, the operation of writing to subframe W_f2 differs from the operation of writing to subframe W_f1 in the following aspects: First, in writing to subframe W_f2, the image processing circuit 40 outputs the even-numbered rows and odd-numbered columns of the input pixels arranged in vertical (2m) rows × horizontal (2n) columns in the image data Vde-in as image data Vdata; Second, the image processing circuit 40 sets the control signal Psh_Y to voltage -A and the control signal Psh_X to voltage -A, so that the projection pixel of the optical path shifting element 20 is located at position (1); and Third, the control circuit 50 sets the selection signal Sel_a to L level and the selection signal Sel_b to H level. The optical path is shifted to the first optical path, and this state is maintained.

[0141] In the subframe W_f2, in all pixel circuits 110R, 110G, and 110B, the voltage of the data signal corresponding to the input pixel in the even-numbered rows and odd-numbered columns of the input pixels arranged in vertical (2m) rows × horizontal (2n) columns in the image data Vde-in is maintained in the capacitor element C1b. On the other hand, the current corresponding to the voltage maintained in the capacitor element C1a (the voltage written in the subframe Wf_1) is supplied to the OLED 130.

[0142] Therefore, in the writing subframe W_f2 (light-emitting subframe L_f1), each OLED 130 in all pixel circuits 110R, 110G, 110B emits light with a brightness corresponding to the subpanel pixels 11R, 11G, 11B of subframe f1, and the projected pixel based on this light emission is seen at position (1) on the screen Scr.

[0143] The operation of the projection device 1 written into subframe W_f3 is the same as the operation of writing into subframe W_f1, except in the following aspects.

[0144] That is, the operation of writing to subframe W_f3 differs from the operation of writing to subframe W_f1 in the following aspects: First, in writing to subframe W_f2, the image processing circuit 40 outputs the even-numbered rows and even-numbered columns of the input pixels arranged in vertical (2m) rows × horizontal (2n) columns in the image data Vde-in as image data Vdata; and second, the image processing circuit 40 sets the control signal Psh_Y to voltage +A, sets the control signal Psh_X to voltage -A, and sets the projected pixel based on the optical path shifting element 20 to position (2). The optical path is shifted to the second optical path, and this state is maintained.

[0145] In the subframe W_f3, in all pixel circuits 110R, 110G, and 110B, the voltage of the data signal corresponding to the even-numbered row and even-numbered column input pixel in the input pixels arranged in vertical (2m) rows × horizontal (2n) columns in the image data Vde-in is maintained in the capacitor element C1a. On the other hand, the current corresponding to the voltage maintained in the capacitor element C1b (the voltage written in the subframe Wf_2) is supplied to the OLED 130.

[0146] Therefore, in the writing subframe W_f3 (light-emitting subframe L_f2), each OLED 130 in all pixel circuits 110R, 110G, 110B emits light with a brightness corresponding to the sub-panel pixels 11R, 11G, 11B of subframe f2, and the projected pixel based on this light emission is seen at position (2) on the screen Scr.

[0147] The operation of the projection device 1 written into subframe W_f4 is the same as the operation of writing into subframe W_f1, except in the following aspects.

[0148] That is, the operation of writing to subframe W_f4 differs from the operation of writing to subframe W_f1 in the following aspects: First, in writing to subframe W_f4, the image processing circuit 40 outputs the input pixels in the image data Vde-in, which are arranged in vertical (2m) rows × horizontal (2n) columns, as image data Vdata; Second, the image processing circuit 40 sets the control signal Psh_Y to voltage +A and the control signal Psh_X to voltage +A, so that the projection pixel of the optical path shifting element 20 is located at position (3); and Third, the control circuit 50 sets the selection signal Sel_a to L level and the selection signal Sel_b to H level. The optical path is shifted to the third optical path, and this state is maintained.

[0149] In the subframe W_f4, in all pixel circuits 110R, 110G, and 110B, the voltage of the data signal corresponding to the input pixel in the odd row and even column of the input pixels arranged in vertical (2m) rows × horizontal (2n) columns in the image data Vde-in is maintained in the capacitor element C1b. On the other hand, the current corresponding to the voltage maintained in the capacitor element C1a (the voltage written in the subframe Wf_3) is supplied to the OLED 130.

[0150] Therefore, in the writing subframe W_f4 (light-emitting subframe L_f3), each OLED 130 in all pixel circuits 110R, 110G, 110B emits light with a brightness corresponding to the sub-panel pixels 11R, 11G, 11B of subframe f3, and the projected pixel based on this light emission is seen at position (3) on the screen Scr.

[0151] Regarding the pixel circuits 110R, 110G, and 110B of the display panel 10 in the projection device 1 of the first embodiment, taking pixel circuit 110R as an example, it can be understood as follows: Figure 14 The structure shown.

[0152] like Figure 14 As shown, Figure 10 Transistors 122a and 122b in the diagram can be understood as the first selector 122. Specifically, in the write subframes W_f1 and W_f3, if scan line 12a is selected and the scan signal Scan_a(i) becomes low level, the first selector 122 electrically connects one end of capacitor element C1a to the data line 14 of column (3j-2). In the write subframes W_f2 and W_f4, if scan line 12b is selected and the scan signal Scan_b(i) becomes low level, the first selector 122 electrically connects one end of capacitor element C1b to the data line 14 of column (3j-2).

[0153] In addition, such as Figure 14 As shown, Figure 10 Transistors 123a and 123b in the text can be understood as the second selector 123. Specifically, in the write subframes W_f1 and W_f3, if the selection signal Sel_a is at level H and the selection signal Sel_b is at level L, then one end of capacitor element C1b is electrically connected to the gate node g of transistor 121. In the write subframes W_f2 and W_f4, if the selection signal Sel_a is at level L and the selection signal Sel_b is at level H, then one end of capacitor element C1a is electrically connected to the gate node g of transistor 121.

[0154] That is, transistor 121 is an example of a driving transistor, transistor 122a is an example of a first switching element, transistor 122b is an example of a second switching element, transistor 123a is an example of a third switching element, and transistor 123b is an example of a fourth switching element. Additionally, capacitor C1a is an example of a first capacitor, and capacitor C1b is an example of a second capacitor.

[0155] Next, we will explain how to suppress the degradation of display quality in the image projected by the projection device 1 of this embodiment.

[0156] Figure 15 This represents the diagram of display area 100. Top indicates the top of display area 100, i.e., the first row; Mid indicates the middle of display area 100, i.e., the (m / 2)th row; and Btm indicates the bottom of display area 100, i.e., the mth row.

[0157] Figure 22 This is a graph used to illustrate the degradation of display quality in the first comparative example. In the first comparative example, it is shown that during each horizontal scan, H selects a scan line, writes a data signal, and sequentially drives the line to become the brightness corresponding to the written data signal.

[0158] Additionally, Wr represents the timing of writing the data signal, and L represents the brightness state corresponding to the data signal being written.

[0159] In the first comparative example, if the optical path shifting element is a structure that shifts the optical path during the write timing of the middle Mid of the display area 100, then the panel pixels of the middle Mid are seen at the position after being shifted by the shifting element with the brightness of the sub-frame, while the panel pixels of the upper Top and lower Btm are seen at the position after being shifted by the optical path shifting element with the brightness spanning the preceding and following sub-frames.

[0160] Therefore, in the first comparative example, the panel pixels located at the top (Top) and bottom (Btm) cannot be seen correctly at their positions after being shifted by the optical path shifting element. As a result, the display quality is reduced due to the inconsistency in the display at the shifted position.

[0161] Figure 23 This is a graph used to illustrate the decline in display quality in the second comparative example. The second comparative example has the following structure: the horizontal scan period H is shortened, that is, the time used to write the data signal is shortened, and the vertical scan retrace period is correspondingly extended, so that the extended vertical scan retrace period is consistent with the period during which the position is stabilized after being shifted by the optical path shifting element.

[0162] In the second comparative example, as in the first comparative example, the panel pixels at the top, middle, and bottom are seen at approximately equal positions after being shifted by the optical path shifting element. Therefore, it is believed that the decline in display quality caused by the inconsistency in the display at the shifted position can be suppressed.

[0163] However, in the second comparative example, because the time for writing the data signal was shortened, the voltage that generates the data signal was not sufficiently written to the capacitor element, which easily leads to a decrease in display quality due to insufficient writing.

[0164] Figure 16 This is a diagram used to illustrate the suppression of the decline in display quality in the first embodiment.

[0165] As described above, in the first embodiment, for example, in the write subframe W_f1, the data signal is sequentially written to the capacitor element C1a at each horizontal scan period H, and on the other hand, the current corresponding to the voltage written to the capacitor element C1b is supplied to the OLED 130. In the next write subframe W_f2, the data signal is sequentially written to the capacitor element C1b at each horizontal scan period H, and on the other hand, the current corresponding to the voltage written to the capacitor element C1a is supplied to the OLED 130.

[0166] Therefore, in the first embodiment, the time for writing the data signal can be sufficiently ensured, and there is no contradiction in the display at the shift position, thus suppressing the degradation of display quality.

[0167] <Second Implementation Method>

[0168] Next, the projection device 1 according to the second embodiment will be described. In the second embodiment, the structure of the pixel circuits 110R, 110G, and 110B in the display panel 10 differs from that in the first embodiment. Therefore, regarding the second embodiment, the differences in the pixel circuits 110R, 110G, and 110B will be mainly described.

[0169] In addition, in the second embodiment, the pixel circuits 110R, 110G, and 110B are structured to compensate the threshold voltage of the transistor 121 that controls the current flowing through the OLED 130.

[0170] Furthermore, in the second embodiment, the electrical structures of pixel circuits 110R, 110G, and 110B are also the same, so the pixel circuit 110R located in row i (3j-2) column will be described as representative.

[0171] Figure 17 This is a circuit diagram showing the electrical structure of the pixel circuit 110R in the display panel 10 of the projection device 1 according to the second embodiment. Figure 17 In the pixel circuit 110R shown, with Figure 10 Compared to the pixel circuit 110R shown, a capacitor C2 and p-channel MOS transistors 125 and 126 are added.

[0172] exist Figure 17 In this configuration, the drain nodes of transistors 123a and 123b are connected to the drain node of transistor 125 and one end of capacitor C2. The other end of capacitor C2 is connected to the gate node g of transistor 121 and the drain node of transistor 126. The source node of transistor 125 is connected to power supply wiring 116, and its gate node is supplied with a control signal Yb. The source node of transistor 126 is connected to the drain node d of transistor 121, and its gate node is supplied with a control signal Ya.

[0173] In addition, control signals Ya and Yb are provided from control circuit 50 to all pixel circuits 110R, 110G and 110B.

[0174] Figure 18 and Figure 19 This is a timing diagram used to explain the operation of the projection device 1 in the second embodiment.

[0175] Control signals Ya and Yb become low (L) level after the writing of subframes W_f1 to W_f4 is completed. Specifically, after the writing of subframes W_f1 to W_f4 is completed, control signal Yb first becomes low (L) level, and then control signal Ya becomes low (L). After control signal Ya becomes low (L), control signal Yb first becomes high (H) level, and then control signal Ya becomes high (H).

[0176] Furthermore, in the second embodiment, in the write subframes W_f1 and W_f3 (light-emitting subframes L_f4 and L_f2), the selection signal Sel_a is at level H and the selection signal Sel_b is at level L. In the write subframes W_f2 and W_f4 (light-emitting subframes L_f1 and L_f3), the selection signal Sel_a is at level L and the selection signal Sel_b is at level H, which is the same as in the first embodiment. However, the timing of the selection signals Sel_a and Sel_b changing to level H is the end timing of the write subframes W_f1 to W_f4 (light-emitting subframes L_f1 to L_f4). Additionally, the timing of the selection signals Sel_a and Sel_b changing to level L is after the control signal Ya changes to level H and before the end of the vertical scan retrace period Vblnk.

[0177] When the timing control signal Yb at the end of writing subframes W_f1 to W_f4 becomes L level, transistor 125 becomes on, and therefore one end of capacitor C2 becomes the power supply potential ELvdd.

[0178] Next, when the control signal Ya becomes level L, transistor 126 becomes on, thus becoming a state in which the drain node and gate node in transistor 121 are connected, i.e., a diode connection state. Therefore, the voltage between the gate node g and the source node s in transistor 121 converges to the threshold voltage of transistor 121, which is held by capacitor element C2.

[0179] When the control signal Yb becomes H level, transistor 125 becomes off, and when the control signal Ya becomes H level, transistor 126 becomes off.

[0180] Just before Vblnk ends during the vertical scan retrace, the selection signal Sel_b becomes L level, and transistor 123b becomes on. Therefore, capacitors C1b and C2 are connected in series between power supply wiring 116 and gate node g of transistor 121.

[0181] Therefore, in the luminescent subframe L_f2 (or L_f4) after Vblnk ends during the vertical scan retrace, a threshold voltage is added to the voltage corresponding to the gray level supplied in the previous write subframe W_f2 (or W_f4), and this added voltage is applied to the gate node g of transistor 121.

[0182] Furthermore, after Vblnk ends during the vertical scan retrace, if it becomes a light-emitting subframe L_f3 (or L_f1), transistor 123a becomes on, and therefore capacitors C1a and C2 are connected in series between power supply wiring 116 and the gate node g of transistor 121. Therefore, in light-emitting subframe L_f3 (or L_f1), a threshold voltage is added to the voltage corresponding to the grayscale level supplied in the previous write subframe W_f3 (or W_f1), and this added voltage is applied to the gate node g of transistor 121.

[0183] Thus, according to the second embodiment, during each vertical scan retrace period Vblnk, the threshold voltage of transistor 121 is maintained at capacitor element C2.

[0184] In the subsequent light-emitting subframe, the following actions are performed: if transistor 123b is turned on, a threshold voltage (holding voltage of capacitor C2) is added to the voltage (holding voltage of capacitor C1b) corresponding to the gray level supplied in the previous write subframe, and this added voltage is applied to the gate node g of transistor 121. On the other hand, when transistor 122a is turned on, the voltage corresponding to the gray level is held in capacitor C1a.

[0185] On the other hand, in the light-emitting subframe after Vblnk during vertical scan retrace, the following operation is performed: if transistor 123a is turned on, a threshold voltage (holding voltage of capacitor C2) is added to the voltage (holding voltage of capacitor C1a) corresponding to the gray level supplied in the previous write subframe, and this added voltage is applied to the gate node g of transistor 121. On the other hand, when transistor 122b is turned on, the voltage corresponding to the gray level is held in capacitor C1b.

[0186] In the second embodiment, such actions are performed alternately and repeatedly.

[0187] In the second embodiment, in the light-emitting subframes L_f1 to L_f4, when the position of the projected pixel is stable, the transistors 121 of all pixel circuits 110R, 110G, and 110B simultaneously flow current in the OLED 130, which is the same as in the first embodiment.

[0188] Furthermore, according to the second embodiment, in any of the light-emitting subframes L_f1 to L_f4, with the threshold voltage compensated, transistor 121 causes a current corresponding to the grayscale level to flow through OLED 130, thereby enabling high-quality display with minimal deviation of each pixel circuit 110R, 110G, 110B.

[0189] Therefore, in the second embodiment, the time for writing the data signal can be sufficiently ensured, and there is no contradiction in the display at the shift position. Thus, the degradation of display quality can be suppressed, and a high-quality display with compensated threshold voltage can be achieved.

[0190] Regarding the pixel circuits 110R, 110G, and 110B of the display panel 10 in the projection device 1 of the second embodiment, taking pixel circuit 110R as an example, it can be understood as follows: Figure 20 The structure shown.

[0191] like Figure 18 , 19 As shown, if the control signal Ya is at level L during the vertical scan retrace, then Figure 20 Transistor 126 functions as a switching element that short-circuits the gate node g and drain node d of transistor 121, thus making transistor 121 a diode-connected state. That is, transistor 126 is an example of the sixth switching element.

[0192] Furthermore, capacitor C2 maintains the threshold voltage of transistor 121 when transistors 125 and 126 are in the ON state. In the light-emitting subframe L_f2 (or L_f4), if the selection signal Sel_a is at level H and the selection signal Sel_b is at level L, capacitor C2, maintaining the threshold voltage, is electrically inserted between one end of capacitor C1b and the gate node g of transistor 121. In the light-emitting subframe L_f1 (or L_f3), if the selection signal Sel_a is at level L and the selection signal Sel_b is at level H, one end of capacitor C1a is electrically inserted between the gate node g of transistor 121. That is, capacitor C2 is an example of a third capacitor.

[0193] Additionally, in this description, "electric insertion" refers to insertion between two or more elements when observed in a circuit.

[0194] <Application Examples and Variations>

[0195] The first and second embodiments (hereinafter referred to as embodiments, etc.) illustrated above can be modified in various ways. Specific modifications applicable to the embodiments are illustrated below. Two or more embodiments selected arbitrarily from the following examples can be combined without contradiction.

[0196] In the implementation, the control signal Enb is set to L level during the period when the scan signals Scan_a(1) to Scan_a(m) are sequentially at L level and during the period when the scan signals Scan_b(1) to Scan_b(m) are sequentially at L level (i.e., the entire period of the vertical effective scan period), which is the light emission period, so that the OLED 130 emits light.

[0197] Not limited to this structure, it can also be configured to shorten the light emission period of the OLED 130 by reducing the light emission period when the control signal Enb is at an L level. With such a structure, if the light emission period of the OLED 130 is shortened, the display characteristics in the display panel 10 approach a so-called impulse response, thus reducing the afterimage effect in dynamic image display. Furthermore, darker grayscale levels can be rendered darker through the pixel circuit 110.

[0198] Furthermore, when a portion of the effective vertical scanning period is designated as the emission period, this emission period can be moved forward in time, backward in time, or it can be made into an intermittent period.

[0199] To improve the responsiveness of optical path shifting, overdrive can also be used to drive the optical path shifting element 20. Specifically, such as... Figure 21As shown, when the voltages of the control signals Psh_Y and Psh_X change, the image processing circuit 40 sets the voltage to an excessively oscillating voltage in the direction of the change, and then immediately sets it to the voltage corresponding to the shift amount.

[0200] For example, when the image processing circuit 40 changes the projection pixel from position (1) to position (2), it sets the voltage of the control signal Psh_Y to a voltage (A+α) that has excessively oscillated α in the direction of change, and then immediately sets it to voltage +A. Similarly, when the image processing circuit 40 changes the projection pixel from position (4) to position (1), it sets the voltage of the control signal Psh_X to a voltage (-A-α) that has excessively oscillated α in the direction of change, and then immediately sets it to voltage -A.

[0201] When the optical path shifting element 20 is driven by overdrive in this way, the responsiveness of the optical path shift is improved, and therefore the period during which the projected pixel is stable at any position among positions (1) to (4) is longer. Therefore, the period of the light-emitting subframes L_f1 to L_f4 can be ensured for a longer period.

[0202] In the embodiments, the optical path shifting element 20 is a structure that shifts the projected pixel along the X and Y axes, but it can also be a structure that shifts the projected pixel along either the X or Y axis. For example, if the structure shifts the projected pixel at two different positions along the X axis, the resolution of the display panel 10 is virtually increased to twice the horizontal resolution and thus seen. Alternatively, it can be a structure that shifts the optical path in an oblique direction, not along the X or Y axis.

[0203] In the display panel 10 of the embodiment, transistor 124 is disposed between transistor 121 and OLED 130, but the position of transistor 124 is not limited to the aforementioned arrangement. The function of transistor 124 is to cut off the path of current controlled by transistor 121 flowing through OLED 130; therefore, any structure in which transistors 121 and 124 are connected in series between power lines 116 and 118 is sufficient. Furthermore, transistor 124 is an example of a fifth switching element.

[0204] Furthermore, in the display panel 10, transistors 124 are provided in the pixel circuits 110R, 110G, and 110B. Depending on the conduction state of the transistors 124, transistors 121 cause current to flow through the OLED 130. However, in the first embodiment, since all OLEDs 130 emit light during the same period, it is possible to omit the power supply circuit shown in the figure and supply the power potential ELvdd to the power wiring 116 corresponding to the emission period.

[0205] The projection device 1 of the embodiment, etc., represents a single pixel of color by additive color mixing based on sub-panel pixels 11R, 11G, 11B. Therefore, the display panel 10 is a single-panel type, but it can also be a three-panel type that uses a color separation prism to synthesize a red image display panel, a green image display panel, and a blue image display panel and then projects them.

[0206] Furthermore, while OLED 130 has been described as an example of a light-emitting element in the embodiments, other light-emitting elements may also be used. For example, LEDs (Light Emitting Diodes), mini LEDs, micro LEDs, etc., may also be used as light-emitting elements.

[0207] The channel type of transistors 121, 122a, 122b, 123a, 123b, 124, 125, and 126 is not limited to the specific implementation. Furthermore, these transistors, except for transistor 121, can be appropriately replaced with transmission gates.

[0208] <Postscript>

[0209] Based on the above description, the preferred embodiments of this disclosure can be understood, for example, as follows. Furthermore, for ease of understanding, the reference numerals in the accompanying drawings are listed in parentheses below, but this is not intended to limit the invention to the illustrated embodiments.

[0210] <Postscript 1>

[0211] A projection device (1) of one method (method 1) includes: a display panel (10) comprising a plurality of pixel circuits (110R, 110G, 110B); and a light path shifting element (20), wherein the plurality of pixel circuits (110R, 110G, 110B) each has: a first capacitor element (C1a) and a second capacitor element (C1b); and a light-emitting element (130) that emits light corresponding to brightness and current in a predetermined direction, the light path shifting element (20) being capable of shifting the light path of the light emitted from the light-emitting element (130) to the first light path and the second light path, wherein in the plurality of pixel circuits (110R, 110G, 110B), during the first period (W_f1), the light path shifting element (20) is connected to the light source. The voltage corresponding to the current supplied to the light-emitting element (130) is maintained in the first capacitor element (C1a). During the extinction period (Vblnk) after the first period (W_f1), the light-emitting element (130) is extinguished. During the second period (W_f2) after the extinction period (Vblnk), the current corresponding to the voltage maintained in the first capacitor element (C1a) is supplied to the light-emitting element (130), and the voltage corresponding to the current supplied to the light-emitting element (130) is maintained in the second capacitor element (C1b). In the optical path shifting element (20), during the extinction period (Vblnk), the optical path is shifted from the first optical path to the second optical path. During the second period (W_f2), the optical path remains in the second optical path.

[0212] According to method 1, during the first period (W_f1), sufficient time is ensured for writing the voltage corresponding to the current supplied to the light-emitting element (130), while during the second period (W_f2), the optical path is maintained and the current corresponding to the maintained voltage is supplied to the light-emitting element (130), so that no contradiction occurs in the display at the shifted position.

[0213] Additionally, writing subframe W_f1 is an example of the first period, vertical scan retrace period is an example of the extinction period (Vblnk), and writing subframe W_f2 is an example of the second period.

[0214] <Appendix 2>

[0215] In the projection device (1) of the specific method 1 (method 2), during the first period (W_f1), a current corresponding to the voltage held in the second capacitor element (C1b) is supplied to the light-emitting element (130) to maintain the first optical path. According to method 2, the voltage corresponding to the current supplied to the light-emitting element (130) is alternately held by the first capacitor element (C1a) and the second capacitor element (C1b).

[0216] <Appendix 3>

[0217] In the projection device (1) of the specific method (method 3) of method 2, one pixel circuit (e.g., 110R) of the plurality of pixel circuits (110R, 110G, 110B) is arranged correspondingly at the intersection of the data line (14) and the scan line (12). The pixel circuit (e.g., 110R) also includes a first selector (122), a second selector (123) and a driving transistor (121). The driving transistor (121) can supply current corresponding to the voltage of the gate node to the light-emitting element (130). During the first period (W_f1), when the scan line (12) is selected, the first selector (122) electrically connects one end of the first capacitor element (C1a) to the data line (14), and the second selector... (123) Connect one end of the second capacitor element (C1b) to the gate node. During the second period (W_f2), when the scan line (12) is selected, the first selector (122) connects one end of the second capacitor element (C1b) to the data line (14), and the second selector (123) connects one end of the first capacitor element (C1a) to the gate node. According to mode 3, the voltage corresponding to the current is maintained at one of the first capacitor element (C1a) and the second capacitor element (C1b) by the first selector (122), and the holding voltage of the other of the first capacitor element (C1a) and the second capacitor element is applied to the gate node and source node of the driving transistor (121) by the second selector (123).

[0218] <Appendix 4>

[0219] In the projection device (1) of the specific method of method 3 (method 4), the first selector (122) includes: a first switching element (122a) that is in an on or off state between one end of the data line (14) and one end of the first capacitor element (C1a); and a second switching element (122b) that is in an on or off state between one end of the data line (14) and one end of the second capacitor element (C1b). The second selector (123) includes: a third switching element (123a) that is in an on or off state between one end of the first capacitor element (C1a) and the gate node; and a fourth switching element (123b) that is in an on or off state between one end of the second capacitor element (C1b) and the gate node. According to method 4, the first selector (122) and the second selector (123) can be specifically configured.

[0220] <Appendix 5>

[0221] In the projection device (1) of the specific method of method 4 (method 5), a pixel circuit (110R) includes a fifth switching element (124) connected in series with a driving transistor (121) between the high-level power supply wiring (116) and the low-level power supply wiring (118). According to method 5, the driving transistor (121) can supply current corresponding to the potential of the gate node (g) to the light-emitting element (130) through the on state of the fifth switching element (124).

[0222] <Appendix 6>

[0223] In the projection device (1) of method 5 (method 6), the fifth switching element (124) is turned on during all or part of the first period (W_f1) or the second period (W_f2). According to method 6, the period during which current flows through the light-emitting element (130) can be controlled. Specifically, if this period is extended, the brightness of the displayed image can be ensured, and if this period is shortened, the blurring of the dynamic image display can be reduced.

[0224] <Appendix 7>

[0225] In the projection device (1) of a specific mode (mode 7) as mode 3, 4, 5 or 6, a pixel circuit (110R) includes a sixth switching element (126) that causes the driving transistor (121) to be in a diode-connected state. According to mode 7, the threshold voltage of the driving transistor (121) can be determined based on the diode-connected state of the driving transistor (121).

[0226] <Appendix 8>

[0227] In the projection device (1) of the specific method 7 (method 8), a pixel circuit (110R) includes a third capacitor element (C2) that holds the threshold voltage of the driving transistor (121). The third capacitor element (C2) is inserted between one end of the second capacitor element (C1b) and the gate node during the first period (W_f1), and between one end of the first capacitor element (C1a) and the gate node during the second period (W_f2). According to method 8, the threshold voltage of the driving transistor (121) can be compensated.

[0228] <Appendix 9>

[0229] The projection device (1) described in any one of methods 1 to 8 can be formed as the concept of method (9) of the control method of the projection device (1). In detail, the control method of the projection device (1) of method 9 is as follows: the projection device (1) includes: a display panel (10) which includes a plurality of pixel circuits (110R, 110G, 110B); and a light path shifting element (20), wherein the plurality of pixel circuits (110R, 110G, 110B) respectively have: a first capacitor element (C1a) and a second capacitor element (C1b); and a light-emitting element (130) which emits light corresponding to brightness and current in a predetermined direction, and the light path shifting element (20) can shift the light path of the light emitted from the light-emitting element to the first light path shifting element (20). In the first period (W_f1), the voltage corresponding to the current supplied to the light-emitting element (130) is maintained at the first capacitor element (C1a). During the extinction period (Vblnk) after the first period (W_f1), the light-emitting element (130) is extinguished, and the optical path shifts from the first optical path to the second optical path. In the second period (W_f2) after the extinction period (Vblnk), the current corresponding to the voltage maintained at the first capacitor element (C1a) is supplied to the light-emitting element (130), and the voltage corresponding to the current supplied to the light-emitting element (130) is maintained at the second capacitor element (C1b), thus maintaining the second optical path.

Claims

1. A projection device, characterized by The projection device projects an image onto a projection surface, comprising: a display panel including a pixel circuit having a first capacitor element and a second capacitor element, and a light emitting element that emits light corresponding to luminance and current to the projection surface, during a first period, a voltage corresponding to current supplied to the light emitting element is held in the first capacitor element, during an extinction period after the first period, the light emitting element is extinguished, during a second period after the extinction period, current corresponding to the voltage held in the first capacitor element is supplied to the light emitting element, and a voltage corresponding to current supplied to the light emitting element is held in the second capacitor element, and a light path shifting element that shifts a light path of light emitted from the light emitting element in any of left and right directions and up and down directions when viewing the projection surface to a first light path and a second light path corresponding to each subframe of the projection image, shifts from the first light path to the second light path during the extinction period, and maintains the second light path during the second period.

2. The projection device according to claim 1, wherein during the first period, current corresponding to the voltage held in the second capacitor element is supplied to the light emitting element, and the first light path is maintained.

3. The projection device according to claim 2, wherein the pixel circuit is provided corresponding to an intersection of a data line and a scan line, the pixel circuit further includes a first selector, a second selector, and a drive transistor, the drive transistor is capable of supplying current corresponding to a voltage of a gate node to the light emitting element, during the first period, the first selector electrically connects one end of the first capacitor element to the data line when the scan line is selected, and the second selector electrically connects one end of the second capacitor element to the gate node, during the second period, the first selector electrically connects one end of the second capacitor element to the data line when the scan line is selected, and the second selector electrically connects one end of the first capacitor element to the gate node.

4. The projection device according to claim 3, wherein the first selector includes: a first switching element that becomes an on state or an off state between the data line and one end of the first capacitor element; and a second switching element that becomes an on state or an off state between the data line and one end of the second capacitor element, the second selector includes: a third switching element that becomes an on state or an off state between one end of the first capacitor element and the gate node; and a fourth switching element that becomes an on state or an off state between one end of the second capacitor element and the gate node.

5. The projection device according to claim 4, wherein the pixel circuit includes a fifth switching element connected in series with the drive transistor between a high bit power supply line and a low bit power supply line.

6. The projection device according to claim 5, wherein ​ The fifth switching element is brought into an on state during all or a part of the first period or the second period.

7. The projection apparatus according to claim 3, 4, 5 or 6, wherein The pixel circuit includes a sixth switching element that brings the drive transistor into a diode connection state.

8. The projection apparatus according to claim 7, wherein The pixel circuit includes a third capacitor element that holds a threshold voltage of the drive transistor, The third capacitor element is interposed between one end of the first capacitor element and the gate node during the first period, The third capacitor element is interposed between one end of the second capacitor element and the gate node during the second period.

9. A control method of a projection apparatus that projects a projection image onto a projection surface, including a display panel including a pixel circuit that includes a first capacitor element and a second capacitor element, and a light emitting element that emits light corresponding to a luminance and a current toward the projection surface, and a light path shifting element that can shift a light path of light emitted from the light emitting element in any of right and left directions and up and down directions when the projection surface is observed to a first light path and a second light path corresponding to each subframe of the projection image, characterized in that, during a first period, a voltage corresponding to a current supplied to the light emitting element is held in the first capacitor element, during an extinction period after the first period, the light emitting element is extinguished, and the light path is shifted from the first light path to the second light path, during a second period after the extinction period, a current corresponding to the voltage held in the first capacitor element is supplied to the light emitting element, a voltage corresponding to the current supplied to the light emitting element is held in the second capacitor element, and the second light path is maintained.

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