Semiconductor device structure and method of fabricating the same
By first forming a sacrificial layer in the semiconductor device structure to fill the gaps between nanolayers and then removing it, the problem of residual work function layers between nanolayers is solved, ensuring threshold voltage stability and improved electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT RESEARCH & DEVELOPMENT CENTER CO LTD
- Filing Date
- 2021-12-30
- Publication Date
- 2026-07-10
Smart Images
Figure CN116435261B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device structure and its fabrication method. Background Technology
[0002] With the advancement of technology nodes, GAA (gate all around) structures are being planned for use in MOS transistors. In adjusting the threshold voltage (Vt) of HK-MG (high-k metal gate) structures in GAA structures, it is necessary to etch away the work function layer in certain areas. Because adjacent nanolayers (including nanosheets / nanowires) within the device unit are relatively close, the work function layer may remain in the gaps between the nanolayers after etching, causing the threshold voltage of the GAA structure to fail to reach the desired target value or fluctuate excessively; further etching may damage other structural layers.
[0003] Therefore, it is necessary to provide a method for fabricating semiconductor device structures to solve the problem of residual work function layers in the gaps between nanolayers. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device structure and its fabrication method to solve the problem of residual work function layers in the gaps between nanolayers.
[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device structure, comprising the following steps:
[0006] A transistor substrate and a device unit disposed on the transistor substrate are provided. The device unit includes an NMOS device unit and a PMOS device unit. The NMOS device unit is located in the NMOS region of the transistor substrate, and the PMOS device unit is located in the PMOS region of the transistor substrate. The NMOS device unit and the PMOS device unit each include a plurality of spaced nanolayers.
[0007] A sacrificial layer and a first photoresist layer are sequentially formed on the device unit, and the sacrificial layer also fills part of the gaps between the nanolayers;
[0008] Remove the first photoresist layer and sacrificial layer of the PMOS region to expose the PMOS device cell;
[0009] Remove the first photoresist layer of the NMOS region to expose the sacrificial layer of the NMOS region;
[0010] A work function layer and a second photoresist layer are sequentially formed on the sacrificial layer of the NMOS region and on the PMOS device cell, and the work function layer also fills the gaps between the nanolayers in the PMOS device cell;
[0011] Remove the second photoresist layer, work function layer, and sacrificial layer from the NMOS region.
[0012] Optionally, in the method for fabricating the semiconductor device structure, the sacrificial layer is made of Si or LaO. x .
[0013] Optionally, in the method for fabricating the semiconductor device structure, when the sacrificial layer is made of Si, the process for forming the sacrificial layer includes PECVD or PVD; when the sacrificial layer is made of LaO... x The process for forming the sacrificial layer includes ALD.
[0014] Optionally, in the method for fabricating the semiconductor device structure, the step of removing the first photoresist layer and sacrificial layer of the PMOS region to expose the PMOS device unit includes:
[0015] The first photoresist layer is exposed and developed to form a patterned first photoresist layer, wherein the patterned first photoresist layer exposes the sacrificial layer of the PMOS region;
[0016] Using the patterned first photoresist layer as a mask, the sacrificial layer of the PMOS region is etched away.
[0017] Optionally, in the method for fabricating the semiconductor device structure, the removal process of the first photoresist layer in the NMOS region includes an ashing process.
[0018] Optionally, in the method for fabricating the semiconductor device structure, the step of removing the second photoresist layer, work function layer, and sacrificial layer of the NMOS region includes:
[0019] The second photoresist layer is exposed and developed to form a patterned second photoresist layer, wherein the patterned second photoresist layer exposes the work function layer of the NMOS region;
[0020] Using the patterned second photoresist layer as a mask, the work function layer and the sacrificial layer of the NMOS region are sequentially etched away.
[0021] Optionally, in the method for fabricating the semiconductor device structure, the removal process of the sacrificial layer in the NMOS and PMOS regions includes a wet etching process. When the sacrificial layer is made of Si, the etchant used in the wet etching process includes an NH4OH solution; when the sacrificial layer is made of LaO... x In this case, the etchant used in the wet etching process includes an HCl solution.
[0022] Optionally, in the method for fabricating the semiconductor device structure, the process for removing the work function layer of the NMOS region includes a wet etching process, and the etchant includes an H2O2 solution.
[0023] Optionally, in the method for fabricating the semiconductor device structure, the nanolayer comprises: a substrate in the device unit, an interface layer, an HK dielectric layer, a barrier layer, and an etch stop layer sequentially covering the substrate in the device unit.
[0024] To achieve the above and other related objectives, the present invention also provides a semiconductor device structure, which is prepared by the semiconductor device structure preparation method described above.
[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0026] The semiconductor device structure fabrication method provided by this invention forms a sacrificial layer before forming the work function layer in the NMOS region. Since the sacrificial layer partially fills the gaps between the nanolayers and seals the gaps (or channels) between the nanolayers, the work function layer does not fill the gaps between the nanolayers. Moreover, the filling of the sacrificial layer between the nanolayers is relatively small and can be easily cleaned up later. Therefore, the final semiconductor device structure does not have a work function layer or a sacrificial layer between the nanolayers, which can solve the problem of work function layer residue in the gaps between nanolayers in traditional processes. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of a semiconductor device structure;
[0028] Figure 2 This is a flowchart of a method for fabricating a semiconductor device structure according to an embodiment of the present invention;
[0029] Figures 3 to 15 This is a schematic diagram of the steps in a method for fabricating a semiconductor device structure according to an embodiment of the present invention;
[0030] Figure 1 middle,
[0031] 01-Transistor substrate, 02-Nano layer, 0201-Substrate in device unit, 0202-HK dielectric layer, 0203-Barrier layer, 0204-Etching stop layer, 03-Work function layer, 0301-Residual work function layer;
[0032] Figures 2 to 15 middle,
[0033] 10 - Transistor substrate, 20 - Nano layer, 201 - Substrate in device unit, 202 - HK dielectric layer, 203 - Barrier layer, 204 - Etching stop layer, 30 - Work function layer, 40 - Sacrificial layer, 501 - First photoresist layer, 502 - Second photoresist layer. Detailed Implementation
[0034] The semiconductor device structure and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0035] See Figure 1 A method for fabricating a semiconductor device structure specifically includes the following steps:
[0036] Step S01: Provide a transistor substrate 01 and a device unit disposed on the transistor substrate 01. The device unit includes an NMOS device unit and a PMOS device unit. The NMOS device unit is located in the NMOS region of the transistor substrate 01, and the PMOS device unit is located in the PMOS region of the transistor substrate 01. The NMOS device unit and the PMOS device unit each include a plurality of mutually spaced nanolayers 02.
[0037] Step S02: A work function layer 03 and a photoresist layer (not shown in the figure) are sequentially formed on the device unit, wherein the work function layer 03 also fills the gaps between the nanolayers 02;
[0038] Step S03: Remove the photoresist layer and work function layer O3 of the NMOS region to expose the NMOS device unit;
[0039] Step S04: Remove the photoresist layer in the PMOS region.
[0040] The transistor substrate 01 includes an NMOS region and a PMOS region adjacent to the NMOS region, and device units are formed on the transistor substrate 01. The device units include NMOS device units located in the NMOS region and PMOS device units located in the PMOS region. The NMOS device units and PMOS device units each include a plurality of mutually spaced nanolayers 02. The nanolayers 02 include: a substrate 0201 in the device unit, an interface layer (IL, not shown in the figure) sequentially covering the substrate 0201 in the device unit, an HK (high K) dielectric layer 0202, a barrier layer 0203, and an etch stop layer 0204.
[0041] The semiconductor device structure can ultimately produce a GAA structure. However, in adjusting the threshold voltage of the high-k metal gate in the GAA structure, it is necessary to etch away the work function layer in certain regions of the semiconductor device structure. However, because adjacent nanolayers 02 in different regions of the device unit are relatively close, some work function layers tend to remain between layers after etching, i.e., residual work function layers 0301 may remain between nanolayers 02. This causes the threshold voltage of the GAA structure to fail to reach the desired target value or to fluctuate excessively. Intensifying the etching of the work function layer may damage other structural layers, such as the barrier layer 0203 and the etch stop layer 0204.
[0042] To address the issue of residual work function layers in the GAA structure platform, specifically the problem of residual work function layers in the spacing between nanolayers, this invention provides a method for fabricating a semiconductor device structure. (See [link to relevant documentation]). Figure 2 .
[0043] The method for fabricating the semiconductor device structure includes the following steps:
[0044] Step S1: Provide a transistor substrate and a device unit disposed on the transistor substrate. The device unit includes an NMOS device unit and a PMOS device unit. The NMOS device unit is located in the NMOS region of the transistor substrate, and the PMOS device unit is located in the PMOS region of the transistor substrate. The NMOS device unit and the PMOS device unit each include a plurality of mutually spaced nanolayers.
[0045] Step S2: A sacrificial layer and a first photoresist layer are sequentially formed on the device unit, wherein the sacrificial layer also fills part of the gaps between the nanolayers;
[0046] Step S3: Remove the first photoresist layer and sacrificial layer of the PMOS region to expose the PMOS device cell;
[0047] Step S4: Remove the first photoresist layer of the NMOS region to expose the sacrificial layer of the NMOS region;
[0048] Step S5: Sequentially form a work function layer and a second photoresist layer on the sacrificial layer of the NMOS region and the PMOS device cell, wherein the work function layer also fills the gaps between the nanolayers in the PMOS device cell;
[0049] Step S6: Remove the second photoresist layer, work function layer, and sacrificial layer from the NMOS region.
[0050] See Figure 3 and Figure 4 ,in Figure 4 yes Figure 3 A partially enlarged view of the device unit is shown. In step S1, the transistor substrate 10 can be silicon or other silicon-based materials, or other materials, such as a silicon substrate or a silicon-germanium substrate. The transistor substrate 10 can be doped or undoped. The transistor substrate 10 includes an NMOS region and a PMOS region adjacent to the NMOS region, and device units are formed on the transistor substrate 10, including NMOS device units located in the NMOS region and PMOS device units located in the PMOS region.
[0051] The NMOS and PMOS device units each include multiple spaced nanolayers 20. The nanolayers 20 can be nanowires, nanosheets, or other shapes. Within the same region, the thickness of multiple nanolayers 20 can be the same or different, and the spacing between adjacent nanolayers 20 can be the same or different. For example, in the NMOS region, each nanolayer 20 has the same thickness, and the spacing between adjacent nanolayers 20 is the same. Each nanolayer 20 includes: a substrate 201 in the device unit, an interface layer (not shown in the figure) sequentially covering the substrate 201, an HK dielectric layer 202, a barrier layer 203, and an etch stop layer 204.
[0052] The substrate 201 in the device unit can be silicon or other silicon-based materials, or other materials. The interface layer (IL) covering the substrate 201 in the device unit can be made of materials such as silicon nitride, or other suitable materials, such as silicon oxynitride. The HK dielectric layer 202 covering the interface layer is made of a high-k material. Examples of high-k materials used in this embodiment include tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO2), etc., preferably hafnium oxide. A barrier layer 203 covers the HK dielectric layer 202. The material of the barrier layer 203 is preferably TiN, but not limited to this. An etch stop layer 204 covers the barrier layer 203 and serves as a stop layer for subsequent wet removal of the work function layer to prevent damage to the barrier layer 203 by the wet process. The material of the etch stop layer 204 is preferably TaN, but not limited to this.
[0053] See Figure 5 In step S2, the sacrificial layer 40 is formed on the surfaces of the NMOS device cell and the PMOS device cell, and the thickness of the sacrificial layer 40 is preferably... For example, the thickness of the sacrificial layer 40 is The sacrificial layer 40 is preferably made of Si or LaO. x However, it is not limited to this. When the sacrificial layer is made of Si, the preferred process for forming the sacrificial layer 40 is PECVD (Plasma Enhanced Chemical Vapor Deposition) or PVD (Physical Vapor Deposition), but it is not limited to this. When the sacrificial layer is made of LaO x The preferred process for forming the sacrificial layer is ALD (Atomic Layer Deposition), but it is not limited to this. In the ALD process, the La precursor reacts with LaO grown from H2O. x .
[0054] Due to the use of PECVD or PVD to form Si, and the use of ALD to form LaO xThe filling ability of the nanolayers is relatively poor. Therefore, the sacrificial layer 40 can partially fill the gaps between the nanolayers 20 while sealing the inter-gate channels of the GAA (i.e., the gaps between nanolayers). This means the sacrificial layer 40 can partially fill the gaps between the nanolayers 20 and prevent the subsequently formed photoresist layer and work function layer from filling these gaps. Because the sacrificial layer 40 has poor filling ability and only partially fills the gaps between the nanolayers 20, it is easier to remove it completely afterward.
[0055] See Figure 6 A photoresist layer 501 is formed by spin-coating photoresist onto the sacrificial layer 40. The upper surface of the first photoresist layer 501 is flush with the surface. A first bottom anti-reflective layer may also be formed between the first photoresist layer 501 and the sacrificial layer 40. The first bottom anti-reflective layer has low reflectivity. The material of the first bottom anti-reflective layer can be an organic anti-reflective coating, formed by spin-coating; or it can be an inorganic anti-reflective coating, formed by plasma-enhanced chemical vapor deposition (PECVD). The material of the inorganic anti-reflective coating can be titanium nitride or silicon nitride, but is not limited thereto. In this embodiment, the first bottom anti-reflective layer is preferably an organic anti-reflective coating.
[0056] See Figure 7 and Figure 8 In step S3, the step of removing the first photoresist layer and sacrificial layer of the PMOS region to expose the PMOS device cell includes:
[0057] Step S31: Expose and develop the first photoresist layer 501 to form a patterned first photoresist layer, wherein the patterned first photoresist layer exposes the sacrificial layer 40 of the PMOS region;
[0058] Step S32: Using the patterned first photoresist layer as a mask, etch away the sacrificial layer 40 of the PMOS region.
[0059] See Figure 7 In step S31, the patterned first photoresist layer exposes the sacrificial layer 40 of the PMOS region, that is, the photoresist of the PMOS region is exposed and developed, while the photoresist of the NMOS region is retained.
[0060] When a first bottom anti-reflective layer exists between the first photoresist layer and the sacrificial layer 40, the process further includes etching the first bottom anti-reflective layer between steps S31 and S32. The first bottom anti-reflective layer is preferably an organic anti-reflective coating, and the etching of the organic anti-reflective coating is preferably dry etching. The etching gas is preferably CH2F2 or C4H8, but is not limited thereto.
[0061] See Figure 8 In step S32, the sacrificial layer 40 is etched using the patterned first photoresist layer as a mask. Since the photoresist in the PMOS region is etched away, the sacrificial layer 40 in the PMOS region is etched away using the patterned first photoresist layer as a mask.
[0062] The etching process for the sacrificial layer 40 is preferably a wet etching process. When the material of the sacrificial layer 40 is Si, the etchant used in the wet etching process includes, but is not limited to, NH4OH solution; when the material of the sacrificial layer is LaO... x In this process, the etchant used in the wet etching process includes, but is not limited to, an HCl solution. Because the sacrificial layer 40 has relatively poor filling capacity, only partially filling the spaces between the nanolayers 20, the wet etching process can easily remove the sacrificial layer 40 completely, leaving no residue in the spaces between the nanolayers 20.
[0063] See Figure 9 In step S4, the first photoresist layer 501 of the NMOS region is removed, that is, the patterned first photoresist layer is removed. The preferred method for removing the first photoresist layer of the NMOS region is an ashing method.
[0064] See Figure 10 In step S5, a work function layer 30 is formed on the sacrificial layer 40 of the NMOS region and the PMOS device cell. The work function layer 30 also fills the gaps between the nanolayers 20 in the PMOS device cell. The material of the work function layer 30 is preferably TiN, but not limited thereto. The thickness of the work function layer 30 is preferably... Furthermore, the formation process of the work function layer 30 can be any one of PVD, CVD, and ALD. Since the first photoresist layer 501 and the sacrificial layer 40 of the PMOS region are etched away, the PMOS device unit is exposed, that is, the nanolayers 20 in the PMOS device unit and the spacing between the nanolayers 20 are exposed. Therefore, the work function layer 30 also fills the spacing between the nanolayers 20, and completely fills the spacing between the nanolayers 20.
[0065] See Figure 11A second photoresist layer 502 is formed by spin-coating photoresist onto the work function layer 30. A second bottom anti-reflective layer may also be formed between the second photoresist layer 502 and the work function layer 30. The second bottom anti-reflective layer has low reflectivity. The material of the second bottom anti-reflective layer can be an organic anti-reflective coating, formed by spin-coating; or it can be an inorganic anti-reflective coating, formed using plasma-enhanced chemical vapor deposition (PECVD). The inorganic anti-reflective coating material can be titanium nitride or silicon nitride, but is not limited to these. In this embodiment, the second bottom anti-reflective layer is preferably an organic anti-reflective coating.
[0066] See Figures 12-14 In step S6, the step of removing the second photoresist layer 502, the work function layer 30, and the sacrificial layer 40 of the NMOS region includes...
[0067] Step S61: Expose and develop the second photoresist layer 502 to form a patterned second photoresist layer, wherein the patterned second photoresist layer exposes the work function layer 30 of the NMOS region;
[0068] Step S62: Using the patterned second photoresist layer as a mask, the work function layer 30 and the sacrificial layer 40 of the NMOS region are sequentially etched away.
[0069] See Figure 12 In step S61, the patterned second photoresist layer exposes the work function layer 30 of the NMOS region, that is, the photoresist of the NMOS region is exposed and developed, while the photoresist of the PMOS region is retained.
[0070] When a second bottom anti-reflective layer exists between the second photoresist layer and the work function layer 30, the process further includes etching the second bottom anti-reflective layer between steps S61 and S62. The second bottom anti-reflective layer is preferably an organic anti-reflective coating, and the etching of the organic anti-reflective coating is preferably dry etching. The etching gas is preferably CH2F2 or C4H8, but is not limited thereto.
[0071] See Figure 13 In step S62, using the patterned second photoresist layer as a mask, the work function layer 30 of the NMOS region is etched away, i.e., the work function layer is patterned. The removal method of the work function layer 30 is preferably a wet etching process, and the etchant is preferably SC2 or H2O2, but is not limited thereto.
[0072] See Figure 14Using the patterned second photoresist layer and the patterned work function layer as masks, the sacrificial layer 40 of the NMOS region is etched away. When the sacrificial layer 40 is made of Si, the etchant used in the wet etching process includes, but is not limited to, NH4OH solution; when the sacrificial layer is made of LaO... x In this process, the etchant used in the wet etching process includes, but is not limited to, an HCl solution. Because the sacrificial layer 40 has relatively poor filling capacity, only partially filling the spaces between the nanolayers 20, the wet etching process easily removes the sacrificial layer 40 completely, leaving no residue in the spaces between the nanolayers 20. That is, there is no sacrificial layer residue in the spaces between the nanolayers 20 in the NMOS region.
[0073] See Figure 15 After removing the second photoresist layer, work function layer, and sacrificial layer of the NMOS region, the process may further include: removing the second photoresist layer 502 of the PMOS region to expose the work function layer 30 of the PMOS region. The preferred method for removing the second photoresist layer 502 of the PMOS region is ashing.
[0074] In summary, in the semiconductor device fabrication method, the present invention forms a sacrificial layer before forming the work function layer of the NMOS region. Due to the poor filling ability of the sacrificial layer, it can fill less of the gaps (i.e., channels) between nanolayers while sealing them. This can prevent the work function layer of the NMOS region from filling the gaps between nanolayers. Therefore, there is no residual work function in the gaps between the nanolayers of the NMOS region, which can prevent the device's electrical performance from being difficult to meet the standards or fluctuating too much.
[0075] This invention also provides a semiconductor device structure fabricated using the same method described above. In this semiconductor device structure, there are no work function layer residues in the spacing between the nanolayers of the NMOS region, which avoids the problem of the semiconductor device's threshold voltage failing to reach the desired target value or fluctuating excessively.
[0076] A GAA structure can be fabricated by depositing a metal layer on the semiconductor device. The metal layer covers the entire semiconductor device and also fills the gaps between the nanolayers in the NMOS region. Specifically, the metal layer includes at least a TiAl layer, a TiN layer, and a tungsten metal layer. This GAA structure fabrication method can improve upon the residual work function layer in the GAA platform caused by traditional work function layer removal techniques, thereby enhancing the electrical performance of the GAA structure.
[0077] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.
[0078] Furthermore, it should be understood that the invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which can vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive”, unless the context clearly indicates otherwise. Structures described herein will be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximate should be understood in that way unless the context clearly indicates otherwise.
Claims
1. A method for fabricating a semiconductor device structure, characterized in that, Includes the following steps: A transistor substrate and a device unit disposed on the transistor substrate are provided. The device unit includes an NMOS device unit and a PMOS device unit. The NMOS device unit is located in the NMOS region of the transistor substrate, and the PMOS device unit is located in the PMOS region of the transistor substrate. The NMOS device unit and the PMOS device unit each include a plurality of spaced nanolayers. A sacrificial layer and a first photoresist layer are sequentially formed on the device unit, and the sacrificial layer also fills part of the gaps between the nanolayers; Remove the first photoresist layer and sacrificial layer of the PMOS region to expose the PMOS device cell; Remove the first photoresist layer of the NMOS region to expose the sacrificial layer of the NMOS region; A power function layer and a second photoresist layer are sequentially formed on the sacrificial layer of the NMOS region and on the PMOS device cell, and the power function layer also fills the gaps between the nanolayers in the PMOS device cell; Remove the second photoresist layer, work function layer, and sacrificial layer from the NMOS region.
2. The method for fabricating a semiconductor device structure as described in claim 1, characterized in that, The sacrificial layer is made of Si or LaO. x .
3. The method for fabricating a semiconductor device structure as described in claim 2, characterized in that, When the sacrificial layer is made of Si, the process for forming the sacrificial layer includes PECVD or PVD; when the sacrificial layer is made of LaO... x The process for forming the sacrificial layer includes ALD.
4. The method for fabricating a semiconductor device structure as described in claim 1, characterized in that, The step of removing the first photoresist layer and sacrificial layer of the PMOS region to expose the PMOS device cell includes: The first photoresist layer is exposed and developed to form a patterned first photoresist layer, wherein the patterned first photoresist layer exposes the sacrificial layer of the PMOS region; Using the patterned first photoresist layer as a mask, the sacrificial layer of the PMOS region is etched away.
5. The method for fabricating a semiconductor device structure as described in claim 1, characterized in that, The removal process of the first photoresist layer in the NMOS region includes: an ashing process.
6. The method for fabricating a semiconductor device structure as described in claim 1, characterized in that, The step of removing the second photoresist layer, work function layer, and sacrificial layer from the NMOS region includes: The second photoresist layer is exposed and developed to form a patterned second photoresist layer, wherein the patterned second photoresist layer exposes the work function layer of the NMOS region; Using the patterned second photoresist layer as a mask, the work function layer and the sacrificial layer of the NMOS region are sequentially etched away.
7. The method for fabricating a semiconductor device structure as described in claim 1, characterized in that, The removal process of the sacrificial layer in the NMOS and PMOS regions includes a wet etching process. When the sacrificial layer is made of Si, the etchant used in the wet etching process includes an NH4OH solution; when the sacrificial layer is made of LaO... x In this case, the etchant used in the wet etching process includes an HCl solution.
8. The method for fabricating a semiconductor device structure as described in claim 1, characterized in that, The removal process of the work function layer in the NMOS region includes a wet etching process, and the etchant includes an H2O2 solution.
9. The method for fabricating a semiconductor device structure as described in claim 1, characterized in that, The nanolayer comprises: a substrate in the device unit, an interface layer, an HK dielectric layer, a barrier layer, and an etch stop layer sequentially covering the substrate in the device unit.
10. A semiconductor device structure, characterized in that, The semiconductor device structure is prepared using any one of claims 1 to 9.