Computing device and testing method

Abstract

The computing device of the present invention uses a partially reconfigurable programmable logic unit to perform tests. The programmable logic unit is configured with a test object circuit as a user circuit and a non-test circuit as a user circuit other than the test object circuit. The computing device includes: a configuration control unit that forms a test separation unit in the programmable logic unit for separating the test object circuit and the non-test circuit by partial reconfiguration; and a separation control unit that controls the test separation unit for performing tests on the test object circuit.

Description

Technical Field

[0001] This invention relates to computing devices and testing methods. Background Technology

[0002] For stereo cameras and electronic control devices supporting autonomous driving and advanced driver assistance systems, high-performance data processing is required to apply sensor information to driving control. Reconfigurable logic circuits are sometimes used as the devices responsible for this data processing. Furthermore, in-vehicle electronic systems require high reliability in compliance with the functional safety standard ISO 26262. Among the technologies for ensuring high reliability of reconfigurable logic circuits while simultaneously performing logic circuit testing in a short time, patent document 1 provides an example. Patent document 1 discloses a test method for a programmable logic device that detects faults in a programmable logic device having a programmable logic module that can be set by writing program data into a memory. The method is characterized by comprising: a first step of loading program data into the memory in such a way that the test circuit is constructed using programmable logic modules other than the test module within the programmable logic device; and a second step of testing the test module using the self-test circuit.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 11-44741 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] There is room for research into shortening the testing time in the invention described in Patent Document 1.

[0008] Technical solutions for solving the problem

[0009] The first aspect of the present invention is a computing device that performs tests using a partially reconfigurable programmable logic unit, wherein the programmable logic unit comprises a test object circuit as a user circuit and a non-test circuit as a user circuit other than the test object circuit. The computing device includes: a configuration control unit that forms a test separation unit in the programmable logic unit for separating the test object circuit from the non-test circuit through partial reconfiguration; and a separation control unit that controls the test separation unit for performing tests on the test object circuit.

[0010] The second aspect of the present invention is a computer-executed test method using a partially reconfigurable programmable logic unit, comprising: forming a test separation unit for separating the test object circuit from the non-test circuit by partially reconfiguring the programmable logic unit, which constitutes a test object circuit as a user circuit and a user circuit that is not the test object circuit; and controlling the test separation unit to perform testing on the test object circuit.

[0011] Invention Effects

[0012] According to the present invention, the testing time can be shortened. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a test performed using a programmable device.

[0014] Figure 2 This is a summary diagram of the test.

[0015] Figure 3 This is a diagram illustrating an implementation example of a programmable device.

[0016] Figure 4 This is a diagram illustrating an implementation example of a programmable device.

[0017] Figure 5 This is a diagram illustrating an implementation example of a programmable device.

[0018] Figure 6 This is a diagram showing an example of the structure of the test separation section.

[0019] Figure 7 It is a flowchart representing a series of testing processes.

[0020] Figure 8 This is a diagram representing an example of a timing diagram.

[0021] Figure 9 This is a diagram showing the test separation section in Modified Example 1.

[0022] Figure 10 This is a diagram showing the test conditions in variation example 2.

[0023] Figure 11 This is a summary diagram of the test in variation example 4.

[0024] Figure 12 This is a diagram showing the test conditions in the second embodiment.

[0025] Figure 13 This is a structural diagram of the vehicle control device according to the third embodiment.

[0026] Figure 14 This is a structural diagram of the vehicle control device according to the fourth embodiment. Detailed Implementation

[0027] Hereinafter, embodiments of the electronic control device and testing method will be described with reference to the accompanying drawings. However, the embodiments shown below are merely examples and do not preclude various modifications and techniques not explicitly shown in the embodiments. That is, various modifications can be made to this embodiment without departing from its spirit. Furthermore, the figures do not represent only the components shown in the figures, but may include other functions, etc.

[0028] —First Implementation Method—

[0029] The following is for reference Figures 1 to 8 The first embodiment of the arithmetic device, i.e., the programmable device, is described.

[0030] (Summary Diagram)

[0031] Figure 1 This is a schematic diagram of a test performed using a programmable device (hereinafter referred to as "PLD") 100. The PLD 100 includes a programmable logic unit 200, a test execution control unit 300, a separation control unit 400, a data input unit 500, a configuration control unit 600, and a configuration data storage unit 700. The programmable logic unit 200 is a partially reconfigurable logic circuit. The configuration data written to the programmable logic unit 200 is provided from the configuration data storage unit 700.

[0032] Various logic circuits can be configured in the programmable logic unit 200. These logic circuits are classified into manufacturer logic circuits provided by the manufacturer of the programmable logic unit 200 and user logic circuits created by someone other than the manufacturer of the programmable logic unit 200. In this embodiment, testing of the user logic circuit will be described.

[0033] As a programmable device 100, when using a SoC (System on Chip) type, the test execution control unit 300, separation control unit 400, data input unit 500, configuration control unit 600, and configuration data storage unit 700 can be implemented using a programmable logic unit 200 or a central processing unit (CPU). Alternatively, the test execution control unit 300, separation control unit 400, data input unit 500, and configuration control unit 600 can be implemented using one or more microcomputers, and the configuration data storage unit 700 can be implemented using ROM.

[0034] Figure 1In the example shown, the programmable logic unit 200 includes a test mode generation unit 210, a test target circuit 220, a judgment unit 230, a non-test circuit 240, and a test separation unit 250. The test target circuit 220 and the non-test circuit 240 are corresponding concepts. In this embodiment, the user circuit that is the object of a certain test is called the test target circuit 220, and the user circuit that is not the object of the test is called the non-test circuit 240. That is, the test target circuit 220 and the non-test circuit 240 do not represent specific user circuits, but rather change for each test. Furthermore, the non-test circuit 240 can also be called a "test target external circuit".

[0035] The test execution control unit 300 controls the testing of the test target circuit 220. Specifically, the test execution control unit 300 outputs action commands to the test mode generation unit 210, the judgment unit 230, and the separation control unit 400, and receives responses from the test mode generation unit 210 and the judgment unit 230. The separation control unit 400 outputs action commands to the test separation unit 250 and the configuration control unit 600 based on the commands from the test execution control unit 300. Based on the action commands from the separation control unit 400, the configuration control unit 600 receives configuration data from the configuration data storage unit 700 via the data input unit 500 and writes it into the programmable logic unit 200. Specifically, the configuration control unit 600 writes data to the test mode generation unit 210, the test target circuit 220, the judgment unit 230, the non-test circuit 240, and the test separation unit 250.

[0036] Figure 2 This is a schematic diagram of the test in this embodiment. Figure 2 The diagram only shows the core parts of the test; components such as the test separation section 250, which do not affect the test itself, are omitted. Figure 2 As shown, in this embodiment, the test pattern generation unit 210 generates a test pattern and applies it to the test target circuit 220. Then, the judgment unit 230 compares the output result of the test target circuit 220 with the expected value and outputs the comparison result to the test execution control unit 300. Furthermore, this test method is a method generally used in BIST (Built-in Self Test). Figure 1 Let me continue explaining.

[0037] The configuration data storage unit 700 stores configuration information, i.e., configuration data, to be written to the programmable logic unit 200. In this embodiment, various user logic circuits are first formed in the programmable logic unit 200 through configuration, and the test execution control unit 300 determines the test target circuit 220 from these multiple user logic circuits. Then, the test execution control unit 300 partially reconstructs the test mode generation unit 210 and the judgment unit 230 in the regions of other segmented user logic circuits that have input-output relationships with the test target circuit 220, and performs the test.

[0038] In this test, the separation control unit 400 first separates the test separation unit 250. Upon completion of separation, the configuration control unit 600, via the data input unit 500, partially rewrites the configuration data of the test circuit from the configuration data storage unit 700, which includes information about the separation unit, to the required user logic circuit. Then, the test separation unit 250 is switched from a separated state to a connected state, and the test is performed.

[0039] (Implementation Example)

[0040] Figures 3-5 This is a diagram illustrating an implementation example of a programmable device 100 of the SoC type.

[0041] in, Figures 3-5 In this context, for ease of plotting, the test pattern generation unit 210 is referred to as "TPG" (Test Pattern Generator), and the judgment unit 230 is referred to as "ORA" (Output Response Analyzer).

[0042] Figure 3 In the example shown, the seven user logic circuits UL1 to UL7 are generated in the programmable logic unit 200. Figure 3 In the example shown, because all seven user logic circuits are used as test objects, test separation sections 250 are formed at all connections between the user logic circuits. Furthermore, Figure 3 For ease of illustration, only one reference numeral 250 is shown in the accompanying drawings, but all figures using the same shading represent the test separation section 250. The same applies to the following figures. (See reference) Figure 4 The function of the test separation section 250 is explained in detail.

[0043] Figure 4 In the example shown, UL4 was selected as the user logic circuit for testing. UL4 performs calculations using inputs from UL2 and UL3, and outputs the results to UL5. Therefore, when UL4 is used as the test object, TPGs are configured in UL2 and UL3, and ORAs are configured in UL5.

[0044] In order to transition from the state that was configured to UL1 to UL7 to Figure 4 The state shown requires partial reconstruction of UL2 and UL3 and writing to TPG, and partial reconstruction of UL5 and writing to ORA. However, when writing to them via partial reconstruction, the values ​​of the input / output terminals of the circuits in the partial reconstruction become uncertain. Furthermore, the initial values ​​of the partially reconstructed circuits also become uncertain. This uncertainty can adversely affect testing, so a test separation unit 250 is provided for each circuit undergoing partial reconstruction for separation and connection. Additionally, this test separation unit 250 is also provided to prevent unstable outputs from being output to user logic circuits outside the test object during the partial reconstruction process.

[0045] Figure 5 In the example shown, UL5 was selected as the user logic circuit for testing. UL5 uses inputs from UL1 and UL4 to perform calculations, outputting the results to UL6 and UL7. UL1 needs to be partially reconfigured and written to the TPG, but because UL1 operates based on outputs from the CPU, the output from UL1 to UL5 can be temporarily stopped during test execution by controlling the CPU. Therefore, Figure 5 In the example shown, the test separation part 250 is not provided at the connection between UL5 and UL1.

[0046] Figure 6 This is a diagram showing an example of the structure of the test separation section 250. (See diagram for example.) Figure 6 As shown, the test separation unit 250 can be implemented, for example, using one or more flip-flops F with enable signal terminals. The number of flip-flops F included in the test separation unit 250 is the same as the number of connected terminals. The enable signal input to the flip-flops F is output by the separation control unit 400. The separation control unit 400 uses the enable signal to control the test separation unit 250, enabling the separation and connection of the test target circuit 220 and the non-test circuit 240.

[0047] (flow chart)

[0048] Figure 7 This is a flowchart illustrating a series of testing procedures. The test execution control unit 300 is the entity responsible for executing each step described below. First, in step S701, the test execution control unit 300 instructs the configuration control unit 600 to write to the test target circuit 220. However, if the test target circuit 220 already exists in the programmable logic unit 200, step S701 can be omitted. S701 is executed when, for the purpose of testing other circuits, such as writing to the test pattern generation unit 210, it covers part or all of the test target circuit 220.

[0049] In the subsequent step S702, the test execution control unit 300 uses the separation control unit 400 to separate the test target circuit 220 and the non-test circuit 240 by the test separation unit 250. In the subsequent step S703, the test execution control unit 300 uses the configuration control unit 600 to write data to the test mode generation unit 210 and the judgment unit 230. In the subsequent step S704, the test execution control unit 300 uses the separation control unit 400 to connect the test target circuit 220 and the non-test circuit 240 by the test separation unit 250. In the subsequent step S705, the test execution control unit 300 instructs the test mode generation unit 210 to generate a test mode and execute the test.

[0050] In the subsequent step S706, the test execution control unit 300 retrieves the test results from the judgment unit 230; in other words, it receives the judgment results. In the subsequent step S707, the test execution control unit 300 determines whether the testing of all user logic circuits subject to test has been completed. If it determines that there are circuits that have not been tested, it updates the test object circuit 220 in step S708 and returns to step S701. The test execution control unit 300 terminates when it determines that the testing of all user logic circuits subject to test has been completed. Figure 7 The processing shown.

[0051] (Time series diagram)

[0052] Figure 8 This is an example of a timing diagram representing a programmable device 100. Figure 8 In the diagram, time travels from top to bottom, and the user logic circuits, UL1 to UL5, are shown horizontally. These UL1 to UL5 correspond to... Figures 3-5 In the example shown, the descriptions after UL5 have been omitted for ease of diagramming. Additionally, Figure 8 In this document, the writing of the test separation section 250 is omitted from the record and description. Figure 8 In the example shown, UL2, UL3, and UL4 are set as the test circuits in sequence.

[0053] At time t1, the entire user logic circuit is written through normal refactoring. At time t2, in order to perform testing on the circuit with UL2 as the test object, UL1 is partially refactored and written to the test mode generation unit 210, and UL3 and UL4 are written to the judgment unit 230. At time t3, the test of UL2 is performed.

[0054] At time t4, in order to perform testing on the circuit with UL3 as the test object, a partial reconstruction is performed to write the test mode generation unit 210 to UL2, the judgment unit 230 to UL4, and the user logic circuit to UL3. Since the judgment unit 230 was written to UL3 at time t2, a portion of the user logic circuit written to UL3 at time t1 is overwritten. Because this prevents the testing of UL3, the user logic circuit of UL3 is written again at time t4 through partial reconstruction. Furthermore, since the judgment unit 230 was already written to UL4 at time t2, if the judgment unit 230, which judges the output of UL2, can also judge the output of UL4, the writing of the judgment unit 230 to UL4 at time t4 can be omitted. The test of UL3 is performed at time t5.

[0055] At time t6, in order to perform testing on the circuit targeted by UL4, test pattern generation unit 210 is written to UL2 and UL3 via partial reconstruction, judgment unit 230 is written to UL5, and user logic circuit is written to UL4. Because UL4 was written to judgment unit 230 at times t2 and t4, a portion of the user logic circuit written to UL4 at time t1 is overwritten. Since the test of UL4 cannot be performed in this way, the user logic circuit of UL4 is written again via partial reconstruction at time t6. Furthermore, as mentioned above, there is a case where writing test pattern generation unit 210 to UL2 can be omitted. The test of UL4 is performed at time t7.

[0056] According to the first embodiment described above, the following effects can be obtained.

[0057] (1) The arithmetic unit, i.e., the programmable device 100, performs tests using a partially reconfigurable programmable logic unit 200. The programmable logic unit 200 comprises a user circuit (i.e., the test target circuit 220) and a user circuit (i.e., a non-test circuit 240) that is not the test target circuit 220. It includes a configuration control unit 600 that forms a test separation unit 250 within the programmable logic unit 200 through partial reconfiguration, separating the test target circuit 220 from the non-test circuit 240, and a separation control unit 400 that controls the test separation unit 250 for testing the test target circuit 220. Therefore, by separating the test target circuit 220 from the non-test circuit 240 using the test separation unit 250, the impact of partial reconfiguration writing on the non-test circuit 240 can be suppressed, such as outputting unstable signals. Thus, tests can be performed without rewriting the entire programmable logic unit 200, shortening the test time.

[0058] (2) The separation control unit 400 switches the test target circuit 220 and the non-test circuit 240 between a separated state and a connected state. Therefore, the test can be performed while the separation unit 250 is maintained.

[0059] (3) The configuration control unit 600 also partially reconfigures the programmable logic unit 200 to write a test mode generation unit 210 that generates signals for testing and outputs them to the test target circuit, and a judgment unit 230 that judges the output of the test target circuit 220. The programmable device 100 has a test execution control unit 300 that sends operation commands to the separation control unit 400 and the test mode generation unit 210 and receives judgment results from the judgment unit 230. Therefore, the test mode generation unit 210 and the judgment unit 230 required for testing can be partially reconfigured and the test can be executed.

[0060] (4) Configure control unit 600, etc. Figure 8 As shown at times t4 and t6, the test object circuit 220 is written to the programmable logic unit 200 through partial reconstruction. The test object circuit 220, which was overwritten because it was written to the test mode generation unit 210 and the judgment unit 230 for other tests, can be written again to perform the test.

[0061] (Variation Example 1)

[0062] Figure 9 This diagram illustrates the test separation unit 250 in Modified Example 1. In the first embodiment described above, the test separation unit 250 is implemented internally within the user logic circuit. However, the test separation unit 250 can also be implemented as follows: Figure 9 The implementation shown is external to the user logic circuit, i.e., in the input / output signal wiring of the user logic circuit.

[0063] (Variation Example 2)

[0064] In the first embodiment described above, a test separation section 250 is provided on both the input and output terminals of the test target circuit 220. However, the test separation section 250 may also be provided only on either the input or output terminal of the test target circuit 220. For example, if the judgment unit 230, the test target circuit 220, and the test pattern generation unit 210 are written sequentially by partial reconstruction, in other words, if the test pattern generation unit 210 is written last among the three, the test separation section 250 on the input terminal side of the test target circuit 220 may not be provided.

[0065] (Variation Example 3)

[0066] In the first embodiment described above, all signals input to the test target circuit 220 are signals generated by the test pattern generation unit 210. However, it is also possible to input the output of a non-test circuit 240 into the test target circuit 220.

[0067] Figure 10This diagram illustrates the test conditions in Modified Example 2. In this example, UL4 is the test target circuit 220, receiving inputs from the test pattern generation unit 210 configured in UL2 and UL3, which serves as the non-test circuit 240. Compared to the case where the test pattern generation unit 210 is configured in UL3, the number of test patterns generated can be reduced. Furthermore, when low-speed signals with minimal data changes, such as register setting signals and control signals, and interrupt signals such as error flags, are applied as test patterns to the test target circuit 220, the test time correspondingly increases. By providing these signals to the non-test circuit 240, test efficiency is improved.

[0068] (Variation Example 4)

[0069] At least one of the test execution control unit 300, separation control unit 400, data input unit 500, configuration control unit 600, and configuration data storage unit 700 may not be included in the programmable device 100. For example, all of the test execution control unit 300, separation control unit 400, data input unit 500, configuration control unit 600, and configuration data storage unit 700 may be included in other devices that communicate with the programmable device to perform the same processing as in the first embodiment.

[0070] Figure 11 This is a schematic diagram of the test in Modification Example 4. In this modification, the test control device 100T communicates with the programmable device 100S and performs the same processing as in the first embodiment. The test control device 100T includes a test execution control unit 300, a separation control unit 400, a data input unit 500, a configuration control unit 600, and a configuration data storage unit 700. The programmable device 100S has a programmable logic unit 200.

[0071] The test control device 100T can be implemented using a CPU to form the test execution control unit 300, separation control unit 400, data input unit 500, and configuration control unit 600, or it can be implemented using application-specific integrated circuits or rewritable logic circuits. The configuration data storage unit 700 is implemented, for example, using a ROM. Furthermore, although... Figure 11 The programmable device 100S, which is not illustrated, may also have a ROM for storing configuration data and a structure for executing configuration.

[0072] That is, the test control device 100T in this modified example is an arithmetic device that performs tests using a programmable device 100S having a partially reconfigurable programmable logic unit 200. The programmable logic unit 200 comprises a user circuit (i.e., the test target circuit 220) and a user circuit that is not the test target circuit 220 (i.e., the non-test circuit 240). It has a configuration control unit 600 that, through partial reconfiguration, forms a test separation unit 250 in the programmable logic unit 200 that separates the test target circuit 220 from the non-test circuit 240, and a separation control unit 400 that controls the test separation unit 250 for testing the test target circuit 220. Therefore, for example, it is possible to connect the test control device 100T to the programmable device 100S, which operates independently, and perform short-duration tests efficiently.

[0073] —Second Implementation Method—

[0074] refer to Figure 12 This section describes a second embodiment of the computing device, i.e., the programmable device. In the following description, the same reference numerals are used for the same components as in the first embodiment, and the main differences are explained. Aspects not specifically described are the same as in the first embodiment. The main difference in this embodiment compared to the first embodiment is the ability to test multiple user logic circuits in parallel.

[0075] In this embodiment, the test execution control unit 300 determines combinations of non-adjacent user logic circuits, in other words, those not in a data input / output relationship, from among a plurality of user logic circuits that are to be tested. Then, the test execution control unit 300 tests the determined combination of user logic circuits in parallel.

[0076] Figure 12 This is a diagram showing the test conditions in the second embodiment. Figure 12 In the circuit 220, UL4 and UL6 are tested in parallel. UL4 and UL6 are not in a data input / output relationship, so they can be tested in parallel. If a combination of UL4 and UL5 is considered, the decision unit 230 that determines the output of UL4 needs to be written into UL5, which interferes with the original operation of UL5. Therefore, UL4 and UL5 cannot be tested in parallel.

[0077] like Figure 12 As shown, the test execution control unit 300 uses the configuration control unit 600 to write UL1, UL2, UL3, and UL5 into the test mode generation unit 210, and UL5 and UL7 into the judgment unit 230. In this example, UL5 is written into both the test mode generation unit 210 and the judgment unit 230, but writing the test mode generation unit 210 and the judgment unit 230 into the same user logic circuit is not necessary in this embodiment.

[0078] According to the second embodiment described above, in addition to the effects of the first embodiment, it is also possible to reduce the number of tests and further reduce the test time through parallel processing of the tests.

[0079] —Third Implementation Method—

[0080] refer to Figure 13 This describes a third embodiment of the arithmetic device, i.e., a programmable device. In the following description, the same reference numerals are used for the same components as in the first embodiment, and the main differences are explained. Aspects not specifically described are the same as in the first embodiment. The main difference from the first embodiment is that the test target circuit 220 is tested while the non-test circuit 240 is performing calculations.

[0081] Figure 13 This is a structural diagram of the vehicle control device 900 according to the third embodiment. The vehicle 1000 has a sensor module 800 that collects information about the surroundings of the vehicle 1000 and an electronic control device 900 with a built-in programmable device 100. The information collected by the sensor module 800 is provided to the programmable device 100 of the electronic control device 900. The user logic circuits written in the programmable logic unit 200 process, for example, the information collected by the sensor module 800.

[0082] The test execution control unit 300 detects whether each user logic circuit is working, and sets one of the user logic circuits that is not working as the test target circuit 220 for testing. However, if the test execution control unit 300 needs to write to at least one of the test mode generation unit 210 and the judgment unit 230 for testing, it performs the test under the condition that the user logic circuit to be written is also not working. For example, Figure 3 In the example of the user logic circuit shown, the condition for performing the UL4 test is that the four user logic circuits UL2 to UL5 are not in operation.

[0083] According to the third embodiment described above, in addition to the effects of the first embodiment, the following effects can also be obtained.

[0084] (5) The test execution control unit detects whether the multiple user circuits configured in the programmable logic unit 200 are working, and sets one of the user logic circuits that is not working as the test target circuit for testing. Therefore, it is possible to test unused user logic circuits in accordance with the actions of the motor vehicle in use (driving, parking, etc.).

[0085] ―Fourth Implementation Method―

[0086] refer to Figure 14This describes a fourth embodiment of the computing device, i.e., the programmable device. In the following description, the same reference numerals are used for the same components as in the third embodiment, and the main differences are explained. Aspects not specifically described are the same as in the third embodiment. The main difference from the first embodiment lies in communication with the outside.

[0087] Figure 14 This is a structural diagram of the vehicle control device 900 according to the fourth embodiment. In addition to the structure of the third embodiment, the vehicle control device 900 in this embodiment also includes an external communication unit 1100. The external communication unit 1100 is a wireless communication device that communicates with the outside of the vehicle 1000. The external communication unit 1100 sends the test results from the programmable device 100 to a server 1200 located outside the vehicle 100.

[0088] According to the fourth embodiment described above, in addition to the effects of the first embodiment, the following effects can also be obtained.

[0089] (6) An external communication unit 1100 is provided to transmit test results of the test object circuit 220 via wireless communication. Therefore, the programmable device 100 can transmit test results to the outside in real time. These test results can also be considered diagnostic results of the programmable logic unit 200, and can therefore be used to monitor the operation of the programmable device 100 and evaluate system reliability. Furthermore, since the test results can be monitored by the server 1200, they can also be applied to maintenance services, etc. In addition, in the use of motor vehicles, the importance of the test object circuit can be changed, and the diagnostic cycle and number of circuits affecting safety, such as safety mechanisms (fault detection circuits) related to vehicle functional safety, can be weighted to improve the safety of the vehicle electronic system.

[0090] In the above embodiments and variations, the structure of the functional modules is only one example. Certain functional structures shown as separate functional modules can be integrally constructed, or the structure represented by one functional module diagram can be divided into two or more functions. Alternatively, the structure can be modified so that other functional modules possess a portion of the functions of each functional module.

[0091] The above-described embodiments and modifications can also be combined separately. Various embodiments and modifications have been described above, but the present invention is not limited to these. Other methods conceivable within the scope of the technical concept of the present invention are also included within the scope of the present invention.

[0092] Explanation of reference numerals in the attached figures

[0093] 100, 100S Programmable Devices

[0094] 100T Test Control Device

[0095] 200 Programmable Logic Section

[0096] 210 Test Mode Generation Department

[0097] 220 Test object circuit

[0098] 230 Judgment Department

[0099] 240 Non-test circuit

[0100] 250 Test Separation Section

[0101] 300 Test Execution Control Department

[0102] 400 Separation Control Unit

[0103] 600 Configuration Control Unit.

Claims

1. An arithmetic device that performs a test using a programmable logic section capable of partial reconfiguration, characterized by: a test target circuit as a user circuit and a non-test circuit as a user circuit other than the test target circuit being composed in the programmable logic section, the arithmetic device comprising: a configuration control section that forms a test separation section for separating the test target circuit from the non-test circuit in the programmable logic section by partial reconfiguration; and a separation control section that controls the test separation section for performing a test of the test target circuit, the test separation section separating at least the non-test circuit inputting an output of the test target circuit from the test target circuit.

2. The arithmetic device according to claim 1, characterized in that: the separation control section switches between a separation state and a connection state between the test target circuit and the non-test circuit.

3. The arithmetic device according to claim 1, characterized in that: the configuration control section further writes a test pattern generation section that generates a signal for a test and outputs it to the test target circuit and a judgment section that judges an output of the test target circuit in the programmable logic section by partial reconfiguration, the test separation section separates at least the test target circuit from the judgment section, and the arithmetic device further comprises a test execution control section that sends an action instruction to the separation control section and the test pattern generation section and receives a judgment result from the judgment section.

4. The arithmetic device according to claim 3, characterized in that: the configuration control section further writes the test target circuit in the programmable logic section by partial reconfiguration.

5. The arithmetic device according to claim 3, characterized in that: the test execution control section detects whether a plurality of user circuits composed in the programmable logic section are operating or not, and sets one of the user logic circuits that is not operating as the test target circuit to perform a test.

6. The arithmetic device according to claim 1, characterized by further comprising an external communication section that transmits a test result of the test target circuit using wireless communication. including: a step of forming a test separation section for separating a test target circuit as a user circuit from a non-test circuit as a user circuit other than the test target circuit in a programmable logic section composed of the test target circuit and the non-test circuit by partial reconfiguration; and a step of controlling the test separation section to perform a test of the test target circuit, the test separation section separating at least the non-test circuit inputting an output of the test target circuit from the test target circuit.

8. The test method according to claim 7, characterized by further comprising a step of writing a test pattern generation section that generates a signal for a test and outputs it to the test target circuit and a judgment section that judges an output of the test target circuit in the programmable logic section by partial reconfiguration, the test separation section separating at least the test target circuit from the non-test circuit. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 7. A test method, performed by a computer, using a programmable logic section capable of partial reconfiguration, characterized in that, ​ ​ ​ ​ ​ ​ ​ ​

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