High-speed high-precision voltage drop monitoring circuit

Abstract

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

Description

Technical Field

[0001] This invention belongs to the field of digital integrated circuit design and power management, and particularly relates to a high-speed, high-precision voltage descent monitoring circuit. Background Technology

[0002] The rapid development of integrated circuits has required processors to handle more complex and varied tasks, and drastic load changes pose challenges to the stability of power supply networks. Load changes directly lead to changes in supply current, resulting in voltage sags. This means insufficient timing margins or even failure to meet minimum requirements, leading to calculation errors. Voltage sags can generally be divided into three stages, with the first-order voltage sag being the most difficult to monitor. Its frequency and amplitude depend on the package inductor and on-chip capacitors, ranging from tens to hundreds of megahertz in frequency and tens to hundreds of millivolts in amplitude.

[0003] Traditional designs, unable to quickly and accurately monitor voltage sags, employ guard loop designs. These require the system to operate at higher voltages and lower frequencies, maintaining timing requirements even during voltage sags. However, a chip's dynamic power consumption is quadratic with voltage, while its static power consumption is linear. Therefore, guard loop solutions incur additional power consumption and temperature costs, violating low-power design principles. In recent years, achieving rapid and accurate voltage sag monitoring, enabling faster system adjustments, and ultimately reducing guard loops to achieve energy efficiency gains, has become a hot research topic in both academia and industry.

[0004] When faced with voltage sags, traditional analog voltage sag monitoring circuits primarily perform a threshold comparison function. While they offer the advantage of simple structure, they can only determine whether the voltage is below a preset threshold. Setting multiple thresholds for voltage judgment typically requires multiple sets of reference voltages or multiple voltage sag monitoring circuits, significantly increasing hardware costs. Furthermore, traditional analog analog-to-digital converters (ADCs) have low sampling frequencies, making it difficult to capture voltage sags. Therefore, digital voltage sag monitoring circuits offer advantages such as high resolution and fast response speed, making them more suitable for voltage sag monitoring tasks than traditional analog circuits. Current digital sensor research can be broadly divided into two technical routes: 1) Digital voltage sag monitoring circuits based on delay chains, which offer advantages such as simple structure and high sampling rate, but have limited monitoring range, poor delay chain stability, and are susceptible to noise; 2) Voltage sag monitoring circuits based on ring oscillators, which offer advantages such as high resolution and high sampling rate, enabling more accurate monitoring of voltage sags. Additionally, combining these circuits with counter designs effectively improves the monitoring range. However, their quantization logic is complex, typically requiring multiple cycles to obtain the voltage quantization result, resulting in poor real-time performance.

[0005] In summary, voltage sag phenomena, especially the first-order voltage sag phenomenon (amplitude > 100mV, time < 10ns), which poses the greatest threat to the system, remain difficult to detect accurately and quickly using existing digital voltage sag monitoring circuits. The design challenges include: 1) The resolution of voltage sag monitoring circuits is limited by the performance of the ring oscillator, but there is a lack of a ring oscillator design method that addresses high voltage sensitivity and load balancing; 2) The "ring oscillator-counter" design approach can effectively broaden the voltage detection range, but traditional counter designs disrupt the load balance of the oscillator connection nodes, leading to jitter in the final quantization result; 3) The quantization logic of traditional digital voltage sag monitoring circuits is complex and the critical path is long, limiting the maximum sampling rate or requiring multiple cycles to obtain the final quantization result, i.e., severe hysteresis. Summary of the Invention

[0006] The purpose of this invention is to provide a high-speed and high-precision voltage drop monitoring circuit, which effectively improves voltage resolution and sampling rate, reduces response delay, and solves the problem that voltage drop phenomena in large-scale integrated circuits are difficult to monitor accurately and in a timely manner.

[0007] To achieve the above-mentioned objectives, the present invention employs the following technical solution:

[0008] A high-speed, high-precision voltage descent monitoring circuit includes an optimized ring oscillator, a sampling register array, a Nyquist counter, a high-speed voltage quantization circuit, and a frequency divider circuit. The optimized ring oscillator maps voltage changes to delay changes in standard cells, which are then controlled by the sampling register array according to the quantization clock F. D The voltage state of each node of the ring oscillator is sampled. Within n sampling periods, the flipping of the counting nodes is monitored by the counting sampling register of the Nyquist counter, and the number of flips is calculated by the coarse quantization circuit of the Nyquist counter to obtain the coarse quantization result L. The high-speed voltage quantization circuit performs fine quantization processing on the sampling result of the ring oscillator to obtain the flipping position of the ring oscillator and the fine quantization result D. Combined with the coarse quantization result L, the final voltage quantization code value VSout is calculated. The frequency divider circuit enables the frequency of the quantization clock to be configured to be 1 / n times the frequency of the sampling clock.

[0009] The optimization design method for ring oscillators includes circuit design and layout design levels, used to construct a ring oscillator with high voltage sensitivity and load balancing, thereby improving the resolution of the voltage descent monitoring circuit and suppressing output jitter; for the sampling register array of the ring oscillator's flip positions, at the quantization clock F DWhen the rising edge arrives, the voltage state of each node of the ring oscillator is sampled and acquired; for the two counting sampling registers of the Nyquist counter, the voltage state of the counting node is sampled and acquired when the rising and falling edges of the sampling clock Clk arrive, respectively; the coarse quantization circuit of the Nyquist counter is used to count the number of toggles of the counting node within n sampling clock cycles, as the coarse quantization result; the high-speed voltage quantization circuit performs fine quantization operation based on the sampling results of the sampling register array and calculates the final quantization result; the frequency divider circuit is used to configure the quantization clock F. D The frequency of the sampling clock Clk can be configured to be 1 / n times the frequency of the sampling clock Clk, where n = 2^(i-1), and i is a positive integer not less than 1; the final quantization result is 10-bit data VSout.

[0010] The optimized ring oscillator design uses four dimensions—standard cell type, threshold, drive capability, and power consumption—as variables to find the ring oscillator circuit design with the highest voltage sensitivity, thereby improving the resolution of the voltage drop monitoring circuit. Furthermore, it provides a one-fold, compact ring oscillator layout design, ensuring load balance between each node of the ring oscillator and suppressing output jitter.

[0011] The Nyquist counter uses a high-frequency sampling clock to excite the sampling register, samples and processes the voltage state of the counting node, and obtains the number of times the counting node flips over a period of time. This solves the problem of metastable sampling caused by the counting delay of traditional counters, improves the monitoring range of the voltage drop monitoring circuit, and maintains the load balance between each node of the ring oscillator.

[0012] The high-speed voltage quantization circuit sends the sampling results from the ring oscillator nodes to the top-level voltage domain for XOR operation, uses transcoding logic to obtain fine quantization results, and combines them with coarse quantization results to calculate the final voltage quantization code value. This high-speed voltage quantization circuit achieves fine quantization of the ring oscillator's flip position and, in its architecture, processes coarse and fine quantization in parallel, improving the sensor's maximum sampling rate and the frequency of its maximum quantization clock.

[0013] The high-speed, high-precision voltage sag monitoring circuit achieves high voltage resolution and sampling and quantization frequencies up to GHz levels through optimized ring oscillator design. It can effectively monitor the most severe first-order voltage sag phenomenon and solve the problem of accurate and timely monitoring of voltage sag phenomenon in large-scale integrated circuits.

[0014] Furthermore, the circuit design method for the ring oscillator is as follows: using four dimensions—standard cell type, threshold, driving capability, and power consumption—as variables, different node frequencies of the ring oscillator are obtained through simulation experiments. Under a fixed voltage difference, the ring oscillator structure with a larger node frequency difference has higher voltage sensitivity, and the voltage descent monitoring circuit built based on it has better resolution. The specific steps of the ring oscillator circuit design are as follows:

[0015] Step 1: The ring oscillator consists of x identical standard units, where x is an odd number greater than or equal to 3. The standard units are connected in a cascaded manner, with the output of each standard unit connected to the input of the next standard unit, and the output of the last standard unit connected to the input of the first standard unit, forming a ring.

[0016] Step 2: Evaluate the node frequency of different ring oscillators using four dimensions as variables: standard cell type, threshold, drive capability, and power consumption cost.

[0017] Step 3: Under a fixed voltage difference, calculate the node frequency difference, find the ring oscillator structure with the larger difference, and improve the resolution of the voltage drop monitoring circuit.

[0018] Furthermore, the layout optimization design method for the ring oscillator is as follows: the layout of the ring oscillator adopts a one-fold, compact layout design; among which, the standard cells constituting the ring oscillator are arranged in the inner layer, divided into two rows, each row is placed at equal intervals, and the distance between the two rows is the minimum distance allowed by the wiring rules; the sampling register corresponding to each standard cell is arranged in the outer layer, and the two are placed adjacent to each other; this ensures that the connection distance between the standard cells constituting the ring oscillator is equal, minimizes the wiring distance from the output end of the standard cell to the input end of the sampling register, and ensures the load balance between the nodes of the ring oscillator. Since the output nodes of the standard cells constituting the x-level ring oscillator, namely a[0], a[1], ..., a[x-1], must be connected to the data end of the corresponding sampling register, the ring oscillator and the sampling register array must be considered together at the layout design level. The specific steps of the layout optimization design of the ring oscillator are as follows:

[0019] Step 1: The layout of the ring oscillator adopts a one-fold design. The standard cells that constitute the ring oscillator are arranged in the inner layer, divided into two rows, with equal spacing between each row. The distance between the two rows is the minimum distance allowed by the wiring rules.

[0020] Step 2: The sampling register corresponding to each standard cell is placed on the outer layer, adjacent to each other. The purpose is to minimize the wiring distance from the oscillator node to the register data terminal and the wiring distance between standard cells, reduce the additional load introduced to the node, and ensure load balance at each node.

[0021] Furthermore, the ring oscillator sampling method is as follows: the ring oscillator and sampling register are arranged in the voltage domain under test, the nodes of the ring oscillator are connected one-to-one to the data terminals of the sampling register array, and the clock terminal of the sampling register array is connected to the quantization clock F. D Its frequency is the quantization frequency. Each time the rising edge of the quantization clock arrives, the sampling register array completes one sampling operation, and the voltage states of nodes a[0], a[1], ..., a[x-1] are sampled as the register outputs A[0], A[1], ..., A[x-1]. A[0], A[1], ..., A[x-1] are then sent to the top-level voltage domain via a level shifter for fine quantization processing.

[0022] Furthermore, the Nyquist counter connects the counting node located on the ring oscillator to the data terminal of a counting sampling register triggered by the falling edge of the sampling clock and the data terminal of a counting sampling register triggered by the rising edge of the sampling clock. This makes the actual sampling rate of the Nyquist counter twice the sampling clock frequency, and the actual sampling rate is always higher than twice the toggling frequency of the counted node, thus satisfying the Nyquist sampling theorem.

[0023] In traditional counters, the counting node is connected to the clock terminal of the register as a trigger signal. However, this introduces excessive additional load to the counting node, severely disrupting the load balance among the x nodes of the ring oscillator. On the other hand, there is a delay from the flipping of the counting node to the completion of the "+1" by the counter, which easily leads to metastable sampling, resulting in incorrect quantization results. The Nyquist counter provided by this invention first places two counting sampling registers in the voltage domain under test, connects the data terminal to the counting node a[0], and connects the clock terminal to the sampling clock Clk (whose frequency is the sampling frequency). This design can significantly reduce the load introduced to the counting node a[0], and the flipping feature is immediately recorded when Clk arrives, eliminating the metastable sampling problem present in traditional counters. One counting sampling register is triggered by the rising edge of Clk, and the other counting sampling register is triggered by the falling edge of Clk. This design increases the actual sampling frequency of the counting node to twice that of Clk. Therefore, by controlling the number of stages x of the ring oscillator so that the frequency of the counting node does not exceed the frequency of Clk within the voltage monitoring range, the Nyquist sampling theorem can be satisfied, and the switching of the node will not be missed. Finally, two level shifters send the sampling results to the top-level voltage domain.

[0024] Further, the coarse quantization circuit of the Nyquist counter is as follows: The sampled data of the counting node is sent to the top-level voltage domain through a level converter. First, two groups of shift registers shift and store the signals from the level converter. Correspondingly, the two groups of registers drive the corresponding counting sample registers, which are triggered by the rising edge and falling edge of the sampling clock Clk respectively, and store the sampled data of the counting node within a quantization clock period in chronological order. Second, the state of the counting node within a quantization clock period is called, and the exclusive OR logic is used to determine whether two adjacent states are the same. If they are different, a flip occurs; otherwise, there is no flip. Finally, a group of adders counts the number of flips within a quantization clock period to obtain L, completing the coarse quantization.

[0025] Further, the method for the high-speed voltage quantization circuit to perform fine quantization on the sampling result is as follows: According to x sampled data, A[0], A[1], ···, A[x - 1], perform the fine quantization operation. First, the data terminals of a group of register arrays located in the top-level voltage domain are connected to the output terminals of the level converter, and the excitation is the quantization clock F D , obtaining a group of x-bit data AA[0], AA[1], ···, AA[x - 1]. Second, two adjacent data are used as the inputs of the exclusive NOR logic to obtain a group of x-bit data P[0], P[1], ···, P[x - 1], aiming to find the flip position of the ring oscillator at the sampling moment, that is, obtaining a group of one-hot codes to complete the flip positioning. Finally, the one-hot codes are converted into binary code values by the transcoding logic to complete the fine quantization operation and obtain D.

[0026] Further, the method for the high-speed voltage quantization circuit to calculate the final voltage quantization result is as follows: Fine quantization and coarse quantization are executed in parallel to shorten the length of the critical path and achieve fast calculation. The high-speed voltage quantization circuit records the fine quantization result Dp when the previous quantization clock arrives. The counting node of the Nyquist counter is located at a[0]. If D > Dp, execute the quantization logic of formula 1, subtract the two fine quantization results, multiply the coarse quantization result L by the number of stages x of the ring oscillator, and then sum the two. Subtract 1 from the difference between the two fine quantization results, multiply the coarse quantization result minus 1 by the number of stages of the ring oscillator, and then sum the two. If D < Dp, it means that the Nyquist counter has performed an additional "+1" operation and needs to be corrected by "-1", that is, execute the quantization logic of formula 2, subtract 1 from the difference between the two fine quantization results, multiply the coarse quantization result minus 1 by the number of stages of the ring oscillator, and then sum the two. The sum result is the change amount of the flip position of the ring oscillator within a quantization period, obtaining the 10-bit quantization code value VSout of the current voltage. At a certain quantization clock frequency, the code value size of VSout corresponds to the voltage state, and the larger the value, the higher the voltage

[0027] Vsout = (D - DP )-x*L (1)

[0028] VSout = (DD) P -1)-x*(L-1) (2)

[0029] Furthermore, the frequency of the quantization clock is configured as follows: through a configurable register frequency divider circuit, the configuration signal is SR, so that the frequency of the quantization clock is 1 / n times the frequency of the sampling clock, where n = 2^(i-1), and i is a positive integer not less than 1. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the circuit design method for the ring oscillator of the present invention.

[0031] Figure 2 This is a schematic diagram of the circuit connection of the 7-stage ring oscillator and sampling register of this invention.

[0032] Figure 3 This is a schematic diagram of the layout design of the 7-stage ring oscillator and sampling register of this invention.

[0033] Figure 4 This is a schematic diagram of the design framework of the high-speed, high-precision voltage drop monitoring circuit of the present invention.

[0034] Figure 5 This is a schematic diagram of the fine quantification process of the present invention.

[0035] Figure 6 This is a schematic diagram of the Nyquist counter circuit design of this invention.

[0036] Figure 7 This is the coarse quantization process of the Nyquist counter in this invention.

[0037] Figure 8 This is a schematic diagram of the method for calculating the final quantification result of this invention.

[0038] Figure 9 This is a schematic diagram of the frequency divider circuit of the present invention.

[0039] Figure 10 This is a schematic diagram of the final quantization results of the present invention at different quantization clock frequencies. Detailed Implementation

[0040] To better understand the purpose, structure, and function of this invention, the high-speed and high-precision voltage drop monitoring circuit of this invention will be described in further detail below with reference to the accompanying drawings.

[0041] Figure 1The diagram illustrates an example of the circuit design method for a ring oscillator provided by this invention. The ring oscillator being evaluated is constructed from 63 inverter stages (i.e., x = 63). For ring oscillators based on inverters with different threshold voltages (SVT, LVT, ULVT) and different drive capabilities (D1, D2, D4, D8), the junction frequency difference and power consumption at 1.1V and 0.6V are evaluated. The performance of ring oscillators constructed from other standard cells can also be evaluated using this method. Figure 1 The data in this paper is based on simulations using a 28nm process. It can be seen that compared to ring oscillators based on SVT inverters, ring oscillators based on LVT or ULVT inverters achieve frequency difference gains of 10.41%-13.47% and 12.16%-18.40%, respectively, implying higher voltage sensitivity. However, this comes at the cost of power consumption increases of 10.68%-20.97% and 23.68%-36.56%, respectively. Therefore, this case study chose an SVT D4 inverter to construct the ring oscillator, improving its voltage sensitivity with lower power consumption.

[0042] Figure 2 The circuit connection method is illustrated using a ring oscillator composed of 7 inverters as an example. Correspondingly, Figure 3 This is a schematic diagram of the layout design for a ring oscillator composed of 7 inverters. Each node of the ring oscillator is connected to the data terminal of a sampling register. The inverters are arranged in two rows (folded once), and the sampling registers corresponding to each inverter are arranged adjacent to each other and placed outside the inverters. It can be seen that the wiring distance from each node of the oscillator to the data terminal of the register is the same, and the wiring distance between standard cells is also the same. Similarly, the layout design of the 63-stage ring oscillator used in this case can be implemented by analogy.

[0043] Figure 4 The diagram illustrates a design framework example for the high-speed, high-precision voltage descent monitoring circuit of this invention. The clock input of the sampling register array is connected to the quantization clock F. D With each rising edge of the clock, the sampling register completes a sampling operation, and the voltage state of node a[62:0] is sampled as the register output A[62:0]. The ring oscillator and the sampling register are deployed in the voltage domain being measured. A[62:0] is sent to the top-level voltage domain via a level shifter.

[0044] The high-speed voltage quantization circuit performs fine quantization according to A[62:0]. First, the data terminal of the register array located in the top voltage domain is connected to the output terminal of the level converter, and the excitation clock is F. DFirst, AA[62:0] is obtained. Next, two adjacent data points are used as inputs to an XOR logic to obtain P[62:0], the purpose of which is to find the toggle position of the ring oscillator at the sampling time. For example, when AA

[10] and AA

[11] are at the same level, P

[10] is 1, and the outputs of other XOR logics are all 0, thus obtaining a set of one-hot codes and completing the toggle positioning. Finally, the one-hot codes are converted into binary code values ​​by the transcoding logic to complete the fine quantization operation, obtaining D. The high-speed voltage quantization circuit records the fine quantization result Dp when the previous quantization clock arrives. Figure 5 Let's illustrate the above process with a case study. The first F D When the rising edge arrives, the fine quantization result is D=10; the second F D When the rising edge arrives, the fine quantization result is D=31, while the previous round of fine quantization result is stored as Dp=10.

[0045] Figure 6 The present invention provides a Nyquist counter design. First, two sampling registers are placed in the voltage domain under test, with the data terminal connected to the counting node a[0] and the clock terminal connected to the sampling clock Clk. One sampling register is triggered by the rising edge of Clk, and the other by the falling edge of Clk. The sampled data is sent to the top-level voltage domain by two level shifters. The signals from the level shifters are shifted and stored using the two sets of registers to obtain S1-S9. Correspondingly, the two sets of registers are triggered by the rising and falling edges of Clk, respectively.

[0046] Figure 7 The case study was used to illustrate the Nyquist counter's processing procedure. Taking Clk = 2 GHz as an example:

[0047] When configuring F D When Clk = 2GHz (i.e., n = 1), the configuration signal SR[1:0] = 2'b00, and F3-F8 are locked to 0. S1-S3 are XORed to obtain F1-F2, which contains one "1", and after accumulation, L = 1.

[0048] When configuring F D When 1 / 2 * Clk = 1 GHz (i.e., n = 2), the configuration signal SR[1:0] = 2'b10, and F5-F8 are locked to 0. S1-S5 are XORed to obtain F1-F4, which contains 3 "1"s. After accumulation, L = 3.

[0049] When configuring F D When 1 / 4 * Clk = 500MHz (i.e., n = 4), the configuration signal SR[1:0] = 2'b11, and F1-F8 are not locked. S1-S9 are XORed to obtain F1-F8, which contain 5 "1"s. After accumulation, L = 5.

[0050] Figure 8 A case for calculating the final quantization result is provided, where the flips do not completely pass through the entire ring oscillator. The counting node of the Nyquist counter is at a[0]:

[0051] When D > Dp, as Figure 7 On the left side, D = 30 and Dp = 10. Among them, the arc arrow (representing the flip) does not pass through the counting node a[0]. Therefore, L = 0 is correct. According to Formula 1, VSout = 20 can be calculated.

[0052] When D < Dp, as Figure 7 On the right side, D = 10 and Dp = 50. Among them, the arc arrow (representing the flip) passes through the counting node a[0]. Also, since the flip does not pass through the entire ring oscillator, L = 1 is incorrect. It is necessary to select Formula 2 (with the "-1" correction) to calculate VSout = (10 - 50 - 1) + 63 * (1 - 1). Among them, "10 - 50 - 1" is the binary cyclic subtraction, which is equivalent to "10 - 0" + "64 - 50 - 1" = 10 + 13 = 23.

[0053] So far, within only one quantization clock cycle, the voltage quantization task is completed. By monitoring the magnitude of VSout, the purpose of voltage steep drop monitoring is achieved.

[0054] Figure 9 It is a schematic diagram of the frequency division circuit. In this case, the quantization clock F D can be configured through the SR signal. When SR is 00, the frequency of the quantization clock F D is equal to the frequency of the sampling clock Clk, which is 2 GHz. When SR is 10, the frequency of the quantization clock F D is 1 / 2 times the frequency of the sampling clock Clk, that is, n = 2, F D = 1 GHz. When SR is 11, the frequency of the quantization clock F D is 1 / 4 times the frequency of the sampling clock Clk, that is, n = 4, F D = 500 MHz. A lower quantization clock frequency can significantly improve the voltage resolution of the voltage steep drop monitoring circuit. For example, the voltage resolution of the voltage steep drop monitoring circuit at F D = 1 GHz is twice that at F D [[ID=]]= 2 GHz

[0055] Figure 10 It is a schematic diagram of the final quantization result of this case at different quantization clock frequencies. The present invention is completed with tape-out and testing under the 28nm process, and the test data is used for plotting Figure 10The standard voltage of the chip designed based on the 28nm process is 0.9V (900mV). Since the first-order voltage descent, which poses the greatest threat to the system, typically has a drop rate greater than 100mV and a fall time less than 10ns, the most critical voltage monitoring range is between 700mV and 900mV. When the quantization clock F... D The frequency is 2GHz. When the measured voltage is 700mV, the value of VSout is 36; when the measured voltage is 900mV, the value of VSout is 65. Therefore, the quantization clock F D When the frequency is 2GHz, the high-speed, high-precision voltage sag monitoring circuit of this invention has an average voltage resolution of (700mV-900mV) / (65-36)≈6.90mV / LSB in the 700mV to 900mV range. Similarly, the quantization clock F D At frequencies of 1 GHz and 500 MHz, the high-speed, high-precision voltage sag monitoring circuit of this invention achieves average voltage resolutions of 3.51 mV / LSB and 1.75 mV / LSB, respectively, in the 700 mV to 900 mV range. The highest quantization clock F of this invention... D With a frequency of 2GHz and a sampling clock Clk frequency of 6.90mV / LSB, its performance is superior to traditional voltage drop monitoring circuit designs, enabling accurate and timely monitoring of voltage drop phenomena.

[0056] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A high-speed, high-precision voltage descent monitoring circuit, characterized in that, The circuit includes: Optimized design of ring oscillator, sampling register array, Nyquist counter, high-speed voltage quantization circuit, frequency divider circuit; The voltage variation is mapped to the delay variation of a standard cell using an optimized ring oscillator, and the sampling register array determines the delay based on the quantization clock F. D The system samples the voltage state of each node of the ring oscillator. Within n sampling clock cycles, the voltage state of the counting nodes is sampled by the counting sampling register of the Nyquist counter. The sampling result is sent to the top-level voltage domain, and the coarse quantization circuit of the Nyquist counter calculates the number of toggles to obtain the coarse quantization result L. The high-speed voltage quantization circuit sends the sampling result of the ring oscillator to the top-level voltage domain to perform an XOR operation. The transcoding logic is used to obtain the toggles of the ring oscillator and the fine quantization result D. Combined with the coarse quantization result L, the final voltage quantization code value VSout is calculated. The frequency divider circuit allows the frequency of the quantization clock to be configured to be 1 / n times the frequency of the sampling clock. The optimized ring oscillator design uses four dimensions—standard cell type, threshold, drive capability, and power consumption—as variables to find the ring oscillator circuit design with the highest voltage sensitivity, thereby improving the resolution of the voltage drop monitoring circuit. Furthermore, it provides a one-fold, compact ring oscillator layout design to ensure load balance between each node of the ring oscillator. The layout optimization design method for the ring oscillator is as follows: the layout of the ring oscillator adopts a one-fold design, in which the standard cells constituting the ring oscillator are arranged in the inner layer, divided into two rows, with equal spacing between each row, and the distance between the two rows is the minimum distance allowed by the wiring rules; the sampling register corresponding to each standard cell is arranged in the outer layer, and the two are placed adjacent to each other; this ensures that the wiring distance between the standard cells constituting the ring oscillator is equal, minimizes the wiring distance from the output of the standard cell to the input of the sampling register, and ensures the load balance between the nodes of the ring oscillator.

2. The high-speed, high-precision voltage drop monitoring circuit according to claim 1, characterized in that, The circuit design method for ring oscillators is as follows: using four dimensions as variables—standard cell type, threshold, driving capability, and power consumption—to obtain different node frequencies of ring oscillators through simulation experiments; under a fixed voltage difference, the ring oscillator structure with a larger node frequency difference has higher voltage sensitivity.

3. The high-speed, high-precision voltage drop monitoring circuit according to claim 1, characterized in that, The sampling method of the ring oscillator is as follows: the ring oscillator and the sampling register array are arranged in the voltage domain to be measured. The nodes of the ring oscillator are connected to the data terminals of the sampling register array. Sampling is completed when the rising edge of each quantization clock arrives. The sampled data is sent to the top voltage domain for quantization processing after passing through a level converter.

4. The high-speed, high-precision voltage drop monitoring circuit according to claim 1, characterized in that, The Nyquist counter connects the counting node on the ring oscillator to the data terminal of a counting sampling register triggered by the falling edge of the sampling clock and the data terminal of a counting sampling register triggered by the rising edge of the sampling clock. This makes the actual sampling rate of the Nyquist counter twice the sampling clock frequency, and the actual sampling rate is always higher than twice the toggling frequency of the counting node, which satisfies the Nyquist sampling theorem.

5. The high-speed, high-precision voltage drop monitoring circuit according to claim 4, wherein the coarse quantization circuit of the Nyquist counter is characterized as follows: the sampled data of the counting node is sent to the top-level voltage domain after being converted by a level converter; two sets of shift registers are located in the top-level voltage domain, and the excitation corresponds to the counting sampling register, namely the rising edge of the sampling clock and the falling edge of the sampling clock; the two sets of shift registers are used to store the sampled data of the counting node in time sequence; adjacent data levels are different and flipped, which is implemented by XOR logic; the number of flips in this time period is counted to achieve the counting purpose.

6. The high-speed, high-precision voltage drop monitoring circuit according to claim 1, characterized in that, The method for fine quantization of the sampling results by the high-speed voltage quantization circuit is as follows: the sampling results of adjacent nodes of the ring oscillator are sent to the top-level voltage domain to perform an XOR operation to obtain a set of one-hot codes, which are then converted into binary code values, which are the flip positions of the ring oscillator at the sampling time.

7. The high-speed, high-precision voltage drop monitoring circuit according to claim 6, characterized in that, The method for the high-speed voltage quantization circuit to calculate the final voltage quantization result is as follows: record the two fine quantization results, namely D and Dp; if D > Dp, subtract the two fine quantization results, multiply the coarse quantization result by the number of stages of the ring oscillator, and then sum the two results; if D < Dp, subtract the two fine quantization results and then subtract 1, multiply the coarse quantization result minus 1 by the number of stages of the ring oscillator, and then sum the two results; the sum result is the position change amount of the ring oscillator flip within one quantization period.

8. The high-speed, high-precision voltage descent monitoring circuit according to claim 1, characterized in that: through a configurable register frequency divider circuit, the configuration signal is SR, such that the frequency of the quantization clock is 1 / n times the frequency of the sampling clock, wherein, n = 2^(i - 1), where i is a positive integer not less than 1.

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