Intelligent Detection System and Detection Method for Chip Signal Connection

Abstract

An intelligent chip signal connection detection system and method relates to integrated circuit technology. The detection system includes a global signal function database, a basic signal information database, a system-level global signal hierarchy extraction component, a multi-module homonymous signal hierarchy extraction component, a uniquely named signal hierarchy extraction component, a signal path back-annotated global function form component, an automatic signal connection relationship and condition constraint generation component, an automatic assertion generation component, and an automatic detection result output and transmission component for outputting inspection result reports. This system significantly reduces maintenance time and labor costs, can be used uniformly in subsequent chip development, and offers strong integration, speed, and accuracy.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology. Background Art

[0002] The integrated circuit industry is rapidly developing, and the scale and complexity of digital integrated circuits are growing exponentially. Chip designs in the industry are reaching tens of millions of gates, and high-end, complex chips can reach hundreds of millions of gates. This increases the difficulty and development cycle of chips. Reports indicate that chip verification accounts for over 60% of the chip development cycle. Reducing time and improving quality and efficiency across all stages of chip verification is crucial to the overall chip launch and quality. During chip verification, interface connectivity checks involve numerous and complex interactions with all modules within the chip, and any single step can impact the entire system. Current verification scenarios either rely on simple connectivity checks or rely on sequential signal simulations using Verilog. There are no standardized processes or tools that can easily and fully automate global chip signal verification and output files for reference at each stage, resulting in relatively low overall efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a chip signal connection intelligent detection system and detection method to reduce chip development time, in view of the problems that project team members have difficulty in aligning signal information, the chip signal connection inspection cycle is long, prone to errors, and the labor cost is high in the current chip development process.

[0004] The technical solution adopted by the present invention to solve the above technical problem is to provide a chip signal connection intelligent detection system, which is characterized by comprising the following parts:

[0005] Signal global function database, used to store the corresponding information of all chip pins;

[0006] Signal basic information database, used to store information of target signals to be checked;

[0007] Signal system-level global hierarchical extraction component, used to extract all hierarchical paths of all signals in the chip.

[0008] Then, perform string processing on each path information, convert it into the path format required for subsequent connectivity checks, and output a complete signal path file;

[0009] Multi-module signal hierarchy extraction component with the same name, used to match signals with the same name with the complete signal path file;

[0010] A uniquely named signal hierarchy extraction component is used to extract a uniquely named signal hierarchy path from a complete signal path file and generate a uniquely named signal path file;

[0011] The signal path back-labeling global function form component is used to back-label the corresponding path in the corresponding path information column of the global function form;

[0012] The signal connection relationship and condition constraint automatic generation component is used to generate the connection relationship of the target signal based on the global function database and the signal basic information database;

[0013] Assertion automatic generation component, used to automatically generate connection relationship check assertion statements used in simulation based on signal connection relationships and condition constraint comma files;

[0014] The test result automatic output and sending component is used to output the inspection result report.

[0015] The data stored in the signal global function database is defined by the signal global function form specification, which is used to define the content and format of the corresponding information of all chip pins, including pin name, pin type, multiplexing function corresponding name, multiplexing function direction, and multiplexing function chip hierarchical path.

[0016] The data stored in the signal basic information database is defined by the signal basic information form specification, which is used to define the information content and format of the target signal to be checked, including the function name corresponding to the target signal in the global function form, the target signal name, whether there are signal level depth requirements and the signal person in charge information.

[0017] The signal system-level global hierarchical extraction component is used to automatically extract all hierarchical paths of all signals in the chip, then perform string processing on each path information, convert it into a path in the format required for subsequent connectivity checks, and output a processed complete signal path file.

[0018] The multi-module same-name signal hierarchy extraction component is used to take the function name corresponding to the target signal in the global function form in the signal basic information database, the target signal name, and whether there is a signal hierarchy depth requirement as input. The component processes the above data, matches it with the complete signal path file, and automatically extracts the matching path, while retaining the corresponding name information of the corresponding multiplexed function to generate a multi-module same-name signal path file.

[0019] The uniquely named signal hierarchy extraction component is used to extract uniquely named signal hierarchy paths from a complete signal path file while retaining the corresponding name information of the corresponding multiplexing function to generate a uniquely named signal path file.

[0020] If the direction of the multiplexing function is bidirectional, the signal path back-labeling global function form component fills in the signal input direction path, signal output direction path and the path of the signal corresponding to the output enable signal in the path column, separates the paths with semicolons, and updates the global database.

[0021] The present invention also provides a detection method using the chip signal connection intelligent detection system.

[0022] By formulating standard specifications for forms, the present invention unifies the core information source of chip signals, has high readability, and is easy to understand and use for reference, thereby greatly reducing maintenance time and labor costs. Subsequent chip development can use it in a unified manner, with strong inheritance, quickness, and accuracy. At the same time, according to the form information, signal levels of any depth can be intelligently extracted, and connectivity comparison can be automatically completed. The output and prompt components of the comparison results can reduce communication costs, enable project members to quickly align project progress, and facilitate progress tracking. The present invention has achieved good application results after actual application in the development of multiple chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a system block diagram of the present invention. DETAILED DESCRIPTION

[0024] In response to the current problems in chip development, such as difficulty in signal information alignment among project team members, long chip signal connection inspection cycles, prone to errors, and high labor costs, we invented a chip signal connection intelligent detection system. This system has been actually applied in the development of multiple chips, has good versatility, and reduces chip development time.

[0025] The chip signal connection intelligent detection system of the present invention includes the following parts:

[0026] (1) Signal global function form specification and signal global function database;

[0027] (2) Signal basic information form specifications and signal basic information database;

[0028] (3) signal system-level global hierarchical extraction components;

[0029] (4) Multi-module signal hierarchy extraction component with the same name;

[0030] (5) Name unique signal level extraction component;

[0031] (6) Signal path back-labeling global function form component;

[0032] (7) Automatically generate components based on signal connection relationships and conditional constraints;

[0033] (8) Assertions automatically generate components;

[0034] (9) Automatic output and sending component of test results.

[0035] They are explained as follows:

[0036] (1) The signal global function form specification specifies the content and format of the corresponding information of all the pins of the chip, including the pin name, pin type, the corresponding name of the multiplexing function, the multiplexing function direction, and the multiplexing function chip level path. The present invention supports the automatic extraction of the above information and processing to form a signal global function database for subsequent use. Through this standard form, only one engineer is required to maintain the information, ensuring the consistency of the signal global function information and reducing labor costs. At the same time, the standardized form is highly readable, which facilitates all members of the project team to grasp and unify the global signal function information and reduce communication costs. The form specification can be applied to all subsequent chip projects and is highly versatile and inherited. The multiplexing function chip level path in the form will be completed by the target signal level back-labeling global function form component in the present invention to complete the level path back-labeling back to the form.

[0037] (2) The signal basic information form specification specifies the information content and format of the target signal to be checked, including the function name corresponding to the target signal in the global function form, the target signal name, whether there is a signal layer depth requirement, and the person in charge of the signal. The function name corresponding to the target signal in the global function form is automatically generated by the corresponding name list of the multiplexing function in the signal global function database. If the multiplexing function direction is a bidirectional signal, an output direction enable control signal needs to be added. The system of the present invention will automatically extract the information in the signal basic information form and process it to form a signal basic information database for subsequent use. Through this standardized form, project team members can clearly understand the information of the target detection signal. Through the person in charge information, the signal connection check report can be sent to the person in charge as soon as it is generated to quickly locate the problem. At the same time, the form provides information on whether the signal has a layer depth requirement. After extracting this information, the system can automatically complete the target signal connectivity check of the corresponding matching layer depth. If there is no such requirement, the default target signal deepest path level connectivity check will be performed.

[0038] (3) Signal system-level global hierarchical extraction component. This component automatically extracts all hierarchical paths of all signals in the chip, then performs string processing on each path information, converting it into a path format required for subsequent connectivity checks, and outputs a processed complete signal path file, which will serve as input information for subsequent components.

[0039] (4) Multi-module signal hierarchy extraction component. In chip design, there may be signals with the same name in multiple modules. For example, the sin input signal is instantiated in both the UART1 and UART2 modules. When checking the connectivity of the target sin signal, it is necessary to check the sin signal paths of the two modules to avoid omissions. For this type of signal with the same name in multiple modules, the multi-module signal hierarchy extraction component in the system of the present invention will automatically process the signal. The component uses the function name, target signal name, and whether there is a signal hierarchy depth requirement corresponding to the target signal in the global function table in the signal basic information database as input. The component processes the above data, matches it with the complete signal path file, automatically extracts the matching path, and retains the corresponding name information of the corresponding multiplexed function to generate a multi-module signal path file for use by subsequent components.

[0040] (5) The uniquely named signal hierarchy extraction component is different from the multi-module signal hierarchy extraction component in that it extracts the uniquely named signal hierarchy path from the complete signal path file while retaining the corresponding name information of the corresponding multiplexed function to generate a uniquely named signal path file for use by subsequent components.

[0041] (6) The signal path back-labeling global function form component has obtained all the paths of all target detection signals in the chip in the multi-module signal path file with the same name and the signal path file with a unique name. There are multiple multiplexing function chip level path information columns corresponding to the pins in the signal global function form. The signal path back-labeling global function form component will back-label the corresponding path in the corresponding path information column of the global function form according to the matching of the corresponding name and path information of the multiplexing function in the signal global function form. If the direction of the multiplexing function is bidirectional, the path column will be filled with the signal input direction path, the signal output direction path and the path of the signal corresponding output enable signal. The paths are separated by semicolons and the global database is updated.

[0042] (7) Automatically generate components for signal connection relationships and conditional constraints. Based on the global function database and the signal basic information database, generate a comma-separated file of the connection relationship of the target signal and the general conditions that need to be constrained when the connection relationship is checked for connectivity in the chip. The output file can clearly display the source and target in the chip signal connection, the hierarchical path of the source and target, and the signal corresponding to the multiplexing function selection condition. If the multiplexing function is bidirectional, add the signal output enable control condition to the constraint condition when checking the output direction.

[0043] (8) Assertion automatic generation component, based on the signal connection relationship and condition constraint comma file, automatically generates the connection relationship check assertion statement used in simulation, and completes the signal connectivity relationship check through assertion logic during system-level verification through formal methods.

[0044] (9) Automatic output and sending of detection results. After completing the connection relationship check of all target signals in the signal connection relationship comma file, the inspection result report is output. The report contains the inspection result of each connection relationship, the assertion statement conditions used in the connection relationship, and the person in charge. The result report is automatically sent to the person in charge of signal management.

[0045] Example 1

[0046] Figure 1 The overall situation of the components and data flow of the chip signal connection intelligent detection system of the present invention is shown. This embodiment will be introduced in accordance with the order of each component and process combined with the situation of use in actual projects.

[0047] Table 1

[0048]

[0049] The signal global function form specification for this embodiment is shown in Table 1. It contains information such as the chip pin name, pin type, corresponding multiplexing function name, multiplexing function direction, and multiplexing function chip-level path. Except for the multiplexing function chip-level path, which is automatically back-labeled by subsequent components, the remaining information is completed and maintained by one person. This single-person maintenance can greatly ensure the accuracy and consistency of the original signal information and avoid information confusion caused by multiple people maintaining it. As the initial input information for the system, the accuracy of the global form information must be guaranteed and must undergo multiple verifications. The information in the signal global function form is necessary for signal connectivity checks. The clear display of the form information helps project team members understand the chip signal connection relationship. The system of the present invention will automatically read all the information in this form and perform data processing, including string case consistency and special symbol processing. The processed data will be stored in the signal global function database for subsequent use. Taking Table 1 as an example, the PE3 pin type in the chip is IO, with three multiplexing functions to choose from. Optional function 1 is UART4_TX, with a direction of DIO bidirectional signal. The back-labeled path field AF0_PATH is reserved.

[0050] Table 2

[0051]

[0052] The signal basic information form specification and the signal basic information database, the signal basic information form specification specified in the present invention is shown in Table 2, including the function name corresponding to the target signal in the global function form, the target signal name, whether there is a signal level depth requirement, and the signal person in charge. The function name corresponding to the target signal in the global function form is automatically generated after being sorted by the global function database. The generated function name combines the direction of the function, such as UART_RX_IN, UART_RX_OUT, indicating that the function signal needs to be checked for connectivity in both directions. If the function signal is a bidirectional signal, an additional UART_RX_OE output enable control signal needs to be generated. The target signal name and whether there is a signal level depth requirement are filled in by the signal person in charge. The target signal name is the signal defined on the interface when the corresponding function is used inside the chip module, such as the name of the interface definition in the UART4 function module is rx_sin. If the level depth requirement is to fill in the instantiation name u_uart4 used by the UART4 module in the chip in CUSTOM_HIER, then the target signal at that depth in the chip will be intelligently selected for inspection during the inspection. Otherwise, the default path depth is the deepest path of the target signal in the chip for inspection.

[0053] The signal system-level global hierarchy extraction component extracts all signal paths in the chip, and the component processes the path format to output the signal global path file for use by subsequent components.

[0054] The component for extracting signals with the same name from multiple modules is used to extract signals with the same name from multiple modules. For example, if the rx_sin signal is defined in both the UART4 and UART5 modules, the component will extract the signals with the same name from multiple modules by combining the module and signal name, while retaining the corresponding name information of the multiplexed functions. The extracted path will be output as a path file for signals with the same name from multiple modules to ensure that the connectivity check of the signals is not missed.

[0055] The uniquely named signal hierarchy extraction component extracts the hierarchical path of the signal defined in only one module in the chip, while retaining the corresponding name information of the multiplexed function, and outputs the extracted path to a uniquely named signal path file.

[0056] Table 3

[0057]

[0058] Signal path back-annotation global function form component: This component will check the corresponding name information of the multiplexed functions retained in the multi-module signal path file with the same name and the unique signal path file with the corresponding name of the multiplexed function in the global function form in turn. If there is a match, the path to be checked in the chip will be back-annotated in the signal global function form. In particular, as shown in Table 3, the multiplexed function is UART4_RX, and its direction is DIO bidirectional. It can be output from the module or used as the input signal of the module, but there can only be one direction in a scenario. Therefore, when the signal is selected as the output direction, the path matching back-annotation of the output control enable signal of the signal is added. When in assertion detection, constraints are added to control its output enable signal to maintain a high level. There are three path information in the path back-annotation column in Table 3, namely the signal path in the input direction, the signal path in the output direction, and the path of the output control signal. The three paths are separated by seals.

[0059] The component for automatically generating signal connection relationships and conditional constraints automatically generates a comma-separated file of the target check signal connection relationship and the general conditional constraints during the check based on the data in the global function database. It detects the connectivity relationship from the rx_sout signal to the PI9_PAD direction in the UART4 module, including the starting end path level, starting end signal name, target end path level, target end signal name, general multiplexing function selection control conditions of the connection relationship to be tested, and output enable control conditions added to the output direction connection check if it is a bidirectional signal.

[0060] The assertion automatic generation component automatically generates assertion statements for each signal when performing connection checks at the system level based on the signal connection relationship and condition constraint comma file. Formal verification is performed based on this assertion to check the consistency of its assertion in the new statistical innocence process, that is, the connectivity of the corresponding information of the target signal.

[0061] The test result automatic output and transmission component automatically generates a test result report after all the signals under test have completed the connection check. The report reflects the direction of the connectivity relationship and the signals at both ends, the simulation constraints during the test, and whether the test result passed. The report is then sent to the person in charge based on the person in charge's information for confirmation. This completes the operation of the chip signal connection intelligent detection system of the present invention.

[0062] Example 2

[0063] The current mainstream method for verifying chip signal connectivity is to build a verification environment using Verilog, SystemVerilog, and UVM after chip design and integration are complete. After sorting out all the connections to be verified, coding is performed, stimulating the source signal of each connection signal to be tested, and encoding the necessary conditions for the connection relationship. After running the test case, the target signal is checked for consistency with the source signal. Traditional verification methods require a significant amount of manpower and time to build the verification platform, sort out signal connections and necessary conditions, code test cases, and encode the connection relationship check code. Without automated optimization, this process is extremely labor-intensive and has extremely low accuracy due to the excessive human involvement. When errors occur, a significant amount of time is required to locate the problem, leading to the embarrassing situation of incomplete modifications causing further problems.

[0064] This invention eliminates the traditional approach of building a verification environment and programming stimuli to verify chip signal connectivity. Instead, it uses the form specifications provided by this invention to extract database information, automatically generating the connectivity relationship to be tested and the required condition assertions with one click, then using assertion tools to check the connectivity relationship. After the check is complete, a check report is automatically generated and sent to the project team. After completing the form with the specification information for the signal to be tested and reviewing it by the project team, only one verification engineer needs to quickly complete the chip signal connectivity check by following the following steps:

[0065] Step 1: Complete and review the signal global function form and basic information form;

[0066] Step 2: The verification engineer enters the chip signal connection intelligent detection system of the present invention, and automatically generates the connectivity relationship to be tested and the required condition assertions with one click, including all the inspection information, and completes the conversion of the original form information into the connection inspection code.

[0067] Step 3: Check the chip signal connection relationship assertion through the assertion checking tool.

[0068] Step 4: After the inspection is completed, an inspection report is generated and automatically sent to project team members.

[0069] The specification has fully explained the necessary technical contents of the present invention. A person skilled in the art is fully capable of implementing the present invention according to the specification, so further details will not be repeated.

Claims

1. Chip signal connection intelligent detection system, characterized in that, Includes the following parts: Signal global function database, used to store the corresponding information of all chip pins; Signal basic information database, used to store information of target signals to be checked; Signal system-level global hierarchical extraction component, used to extract all hierarchical paths of all signals in the chip. Then, perform string processing on each path information, convert it into the path format required for subsequent connectivity checks, and output a complete signal path file; Multi-module signal hierarchy extraction component with the same name, used to match signals with the same name with the complete signal path file; A uniquely named signal hierarchy extraction component is used to extract a uniquely named signal hierarchy path from a complete signal path file and generate a uniquely named signal path file; The signal path back-labeling global function form component is used to back-label the corresponding path in the corresponding path information column of the global function form; The signal connection relationship and condition constraint automatic generation component is used to generate the connection relationship of the target signal based on the global function database and the signal basic information database; Assertion automatic generation component, used to automatically generate connection relationship check assertion statements used in simulation based on signal connection relationships and condition constraint comma files; The test result automatic output and sending component is used to output the inspection result report.

2. The chip signal connection intelligent detection system according to claim 1, characterized in that: The data stored in the signal global function database is defined by the signal global function form specification, which is used to define the content and format of the corresponding information of all chip pins, including pin name, pin type, multiplexing function corresponding name, multiplexing function direction, and multiplexing function chip hierarchical path.

3. The chip signal connection intelligent detection system according to claim 1, characterized in that: The data stored in the signal basic information database is defined by the signal basic information form specification, which is used to define the information content and format of the target signal to be checked, including the function name corresponding to the target signal in the global function form, the target signal name, whether there are signal level depth requirements and the signal person in charge information.

4. The chip signal connection intelligent detection system according to claim 1, characterized in that: The signal system-level global hierarchical extraction component is used to automatically extract all hierarchical paths of all signals in the chip, then perform string processing on each path information, convert it into a path in the format required for subsequent connectivity checks, and output a processed complete signal path file.

5. The chip signal connection intelligent detection system according to claim 1, characterized in that: The multi-module same-name signal hierarchy extraction component is used to take the function name corresponding to the target signal in the global function form in the signal basic information database, the target signal name, and whether there is a signal hierarchy depth requirement as input. The component processes the above data, matches it with the complete signal path file, and automatically extracts the matching path, while retaining the corresponding name information of the corresponding multiplexed function to generate a multi-module same-name signal path file.

6. The chip signal connection intelligent detection system according to claim 1, characterized in that: The uniquely named signal hierarchy extraction component is used to extract uniquely named signal hierarchy paths from a complete signal path file while retaining the corresponding name information of the corresponding multiplexing function to generate a uniquely named signal path file.

7. The chip signal connection intelligent detection system according to claim 1, characterized in that: If the direction of the multiplexing function is bidirectional, the signal path back-labeling global function form component fills in the signal input direction path, signal output direction path and the path of the signal corresponding to the output enable signal in the path column, separates the paths with semicolons, and updates the global database.

8. A chip signal connection intelligent detection method using the chip signal connection intelligent detection system according to claim 1, characterized in that: The steps include: Step 1: Complete and review the signal global function form and basic information form; Step 2: Use the chip signal connection intelligent detection system to automatically generate the connectivity relationship to be tested and the required condition assertions, including all the inspection information, and complete the conversion of the original form information into the connection inspection code; Step 3: Check the chip signal connection relationship assertion through the assertion checking tool; Step 4: Generate inspection report.

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