Display panel

Abstract

A display panel includes a substrate, a first data line, a second data line, a third data line, a plurality of scan lines, a first active element, a second active element, and a plurality of pixel electrodes. The first data line and the third data line have a first polarity. The second data line has a second polarity, and the first polarity is different from the second polarity. A source electrode of the first active element disposed between the first data line and the second data line is electrically connected to the first data line. An extension region of a semiconductor pattern of the first active element extends toward and overlaps with the second data line. A source electrode of a second active element disposed between the second data line and the third data line is electrically connected to the second data line. An extension region of the semiconductor pattern of the second active element extends toward and overlaps with the third data line.

Description

Technical Field

[0001] The present invention relates to a display technology, and in particular to a display panel. Background Art

[0002] Generally speaking, LCD panels achieve varying grayscale display effects by adjusting the polarization of light through pixel electrodes within each pixel area to alter the arrangement of liquid crystal molecules. To meet the battery life requirements of electronic products (such as laptops, tablets, and smartphones), LCD panels can adjust the frame rate to reduce power consumption based on usage scenarios.

[0003] However, because the current pixel electrode configuration is prone to capacitive coupling with adjacent signal lines, and the switching elements used to control the pixel electrodes are susceptible to light exposure and leakage current, the voltage level applied to the pixel electrodes can easily shift within a single frame scan cycle, causing the display to flicker. This flicker is particularly severe when the LCD panel operates at a low frame refresh rate (e.g., 20Hz), affecting display quality. Summary of the Invention

[0004] The present invention provides a display panel which is less likely to experience flickering of displayed images at a lower image refresh rate.

[0005] The display panel of the present invention comprises a substrate, a plurality of data lines, a plurality of scan lines, a plurality of active components, and a plurality of pixel electrodes. The plurality of data lines are arranged at intervals on the substrate and include a first data line, a second data line, and a third data line arranged in sequence. The first data line and the third data line each have a first polarity. The second data line has a second polarity, and the first polarity is different from the second polarity. The plurality of scan lines are arranged at intervals on the substrate and intersect with the plurality of data lines to form a plurality of pixel regions. A plurality of active components are respectively arranged within these pixel regions, and each includes a semiconductor pattern, a source electrode, a drain electrode, and a gate electrode. The gate electrode is electrically connected to one of the scan lines. The semiconductor pattern has a source region and a drain region connected to the source electrode and the drain electrode, respectively, a channel region connected to the source region and the drain region, and an extension region extending from the drain region. A first active component among the plurality of active components is arranged between the first data line and the second data line. The source electrode of the first active component is electrically connected to the first data line. The extension region of the semiconductor pattern of the first active component extends toward and overlaps with the second data line. A second active element among the active elements is disposed between the second data line and the third data line. A source electrode of the second active element is electrically connected to the second data line. An extension region of the semiconductor pattern of the second active element extends toward and overlaps the third data line. A plurality of pixel electrodes are respectively disposed within the plurality of pixel regions and are respectively electrically connected to the plurality of drain electrodes of the plurality of active elements.

[0006] The display panel of the present invention includes a substrate, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, a first pixel structure, and a second pixel structure. The plurality of first data lines and the plurality of second data lines are alternately arranged on the substrate. The first data lines and the second data lines have a first polarity and a second polarity, respectively, and the first polarity is different from the second polarity. The plurality of scan lines are arranged at intervals on the substrate and intersect these first data lines and these second data lines. The first pixel structure is arranged between one of these first data lines and one of these second data lines, and has a first active element and a first pixel electrode. The first active element includes a first semiconductor pattern, a first source, a first drain, and a first gate. The first source is electrically connected to one of the first data lines and the first source region of the first semiconductor pattern. The first drain is electrically connected to the first pixel electrode and the first drain region of the first semiconductor pattern. The first gate overlaps with the first channel region of the first semiconductor pattern. The first channel region is connected between the first source region and the first drain region. The second pixel structure is arranged between one of the second data lines and another of the plurality of first data lines, and has a second active element and a second pixel electrode. The second active element includes a second semiconductor pattern, a second source, a second drain, and a second gate. The second source is electrically connected to one of the second data lines and the second source region of the second semiconductor pattern. The second drain is electrically connected to the second pixel electrode and the second drain region of the second semiconductor pattern. The second gate overlaps the second channel region of the second semiconductor pattern. The second channel region is connected between the second source region and the second drain region. The first semiconductor pattern has a first extension region extending from the first drain region. The second semiconductor pattern has a second extension region extending from the second drain region. The first extension region of the first semiconductor pattern extends toward one of the second data lines and overlaps with the one of the second data lines. The second extension region of the second semiconductor pattern extends toward the other of the first data lines and overlaps with the other of the first data lines.

[0007] Based on the foregoing, in a display panel according to one embodiment of the present invention, two data lines of opposite polarity are provided on opposite sides of an active element, each electrically connected to one of the data lines. By extending the semiconductor pattern of the active element toward and overlapping the other data line, the potential offset of the pixel electrode electrically connected to the active element can be reduced when the display panel operates at a low frame rate (e.g., 20 Hz), thereby improving the problem of display flicker. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic front view of a display panel according to a first embodiment of the present invention.

[0009] Figure 2 yes Figure 1An enlarged schematic diagram of a local area of ​​a display panel.

[0010] Figure 3 yes Figure 2 Schematic cross-sectional view of a display panel.

[0011] Figure 4 is a schematic front view of a display panel according to a second embodiment of the present invention.

[0012] Figure 5 is a schematic front view of a display panel of a comparative example.

[0013] Figure 6A 1 is a flicker value distribution diagram of a display panel according to a comparative example and an embodiment of the present invention operating at a frame refresh rate of 60 Hz.

[0014] Figure 6B 1 is a flicker value distribution diagram of a display panel according to a comparative example and an embodiment of the present invention operating at a frame refresh rate of 20 Hz.

[0015] Description of reference numerals:

[0016] 10, 10A, 10C: Display panel

[0017] 100: Substrate

[0018] BL: buffer layer

[0019] C: Compensation capacitor

[0020] CE: Common Electrode

[0021] CH1, CH2: channel area

[0022] d1: first distance

[0023] d2: second distance

[0024] DE: Drain

[0025] DL, DL1, DL2, DL3: data lines

[0026] DR: drain region

[0027] ETR: Extension Zone

[0028] GE1, GE2: Gate

[0029] GI: Gate Insulation

[0030] GL: Scanline

[0031] HDR: Heavily Doped Region

[0032] ILD: Interlayer insulation layer

[0033] LDR: Lightly Doped Region

[0034] PA: Pixel area

[0035] PE: pixel electrode

[0036] PL: Flat layer

[0037] PLa: Open

[0038] PTD: protrusion

[0039] PVa: Open Cell

[0040] PX, PX1, PX2, PX1-A, PX2-A, PX1-C, PX2-C: Pixel structure

[0041] Re: Side edge

[0042] SC, SC-A, SC-C: Semiconductor patterns

[0043] SE: Source

[0044] SLT: Slit

[0045] SM1, SM2: shading pattern

[0046] SR: Source region

[0047] T, T1, T2, TA, T1-A, T2-A, T1-C, T2-C: Active components

[0048] TH1, TH2: through hole

[0049] X, Y, Z: direction

[0050] A-A': section line DETAILED DESCRIPTION

[0051] As used herein, "about," "approximately," "substantially," or "substantially" include the stated value and the mean value within an acceptable deviation range for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within, for example, ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, as used herein, "about," "approximately," "substantially," or "substantially" can be selected based on the acceptable deviation range or standard deviation of the measured property, cut property, or other property, and may not apply to all properties without a single standard deviation.

[0052] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. is exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there is no intermediate element. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" may refer to the presence of other elements between two elements.

[0053] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in a figure is turned over, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the particular orientation of the figure. Similarly, if the device in a figure is turned over, the element described as being "below" or "beneath" the other elements will be oriented as being "above" the other elements. Thus, the exemplary terms "above" or "below" can include both "above" and "below" orientations.

[0054] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions and are not intended to limit the claims.

[0055] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, like reference numerals are used in the drawings and the description to refer to the same or like parts.

[0056] Figure 1 is a schematic front view of a display panel according to a first embodiment of the present invention. Figure 2 yes Figure 1 An enlarged schematic diagram of a local area of ​​a display panel. Figure 3 yes Figure 2 Schematic diagram of a cross-section of the display panel along the section line AA'. For the sake of clarity, Figure 2 Omitted Figure 3 The lightly doped region LDR and the heavily doped region HDR of the semiconductor pattern SC are shown.

[0057] Please refer to Figure 1 The display panel 10 includes a substrate 100, a plurality of scan lines GL, a plurality of data lines DL, and a plurality of pixel structures PX. In this embodiment, the plurality of data lines DL may be arranged on the substrate 100 at intervals along direction X and extend in direction Y, and the plurality of scan lines GL may be arranged on the substrate 100 at intervals along direction Y and extend in direction X. More specifically, the scan lines GL intersect with the data lines DL and define a plurality of pixel areas PA. The plurality of pixel structures PX are respectively disposed within these pixel areas PA and are each electrically connected to a corresponding scan line GL and a corresponding data line DL.

[0058] It is particularly noted that the polarities of any two adjacent data lines DL are different from each other (eg, polarity is reversed). Figure 2 In this embodiment, the display panel 10 may include a data line DL1, a data line DL2, and a data line DL3 arranged sequentially and adjacently along a direction X. The data line DL1 and the data line DL3 have a first polarity, and the data line DL2 has a second polarity, and the first polarity and the second polarity are opposite to each other. For example, the first polarity of the data line DL1 and the data line DL3 may be positive, and the second polarity of the data line DL2 may be negative, but the present invention is not limited thereto. In other embodiments, the first polarity of the data line DL1 and the data line DL3 may be negative, and the second polarity of the data line DL2 may be positive.

[0059] Alternatively, during a first frame period, the first polarity of the data lines DL1 and DL3 can be positive, while the second polarity of the data line DL2 can be negative. During a second frame period, the first polarity of the data lines DL1 and DL3 can be reversed to negative, while the second polarity of the data line DL2 can be reversed to positive. This is sufficient as long as the polarities of two adjacent data lines DL remain opposite.

[0060] Please refer to Figure 2 and Figure 3The pixel structure PX may include an active device T and a pixel electrode PE electrically connected to each other. The active device T may include a semiconductor pattern SC, a source electrode SE, a drain electrode DE, and a gate electrode GE1. The gate electrode GE1 is electrically connected to a corresponding scan line GL, and one end of the source electrode SE and one end of the drain electrode DE are electrically connected to two different regions of the semiconductor pattern SC. The other end of the source electrode SE is electrically connected to a corresponding data line DL, and the other end of the drain electrode DE is electrically connected to the pixel electrode PE. In this embodiment, the gate electrode GE1 is, for example, formed by the portion of the scan line GL extending along direction Y. The semiconductor pattern SC includes a source region SR, a drain region DR, and a channel region CH1. The channel region CH1 is connected between the source region SR and the drain region DR and overlaps with the gate electrode GE1. The overlapping relationship between the channel region CH1 and the gate electrode GE1 is defined, for example, along direction Z. Unless otherwise specified below, the overlapping relationship between any two components is defined in the same manner and will not be repeated.

[0061] From another perspective, based on the varying doping levels of a particular element, the semiconductor pattern SC can be divided into a channel region CH1, multiple lightly doped regions LDR, and multiple heavily doped regions HDR. These lightly doped regions LDR are located on opposite sides of the channel region CH1 and connect the channel region CH1 to the multiple heavily doped regions HDR. Portions of these heavily doped regions HDR can serve as source regions SR and drain regions DR, electrically connecting the source electrode SE and the drain electrode DE. In other words, the heavily doped regions HDR, source region SR, and drain region DR of the semiconductor pattern SC all have the same resistance.

[0062] It is particularly noteworthy that in this embodiment, the source SE and drain DE of the active device T can be disposed on opposite sides of the scan line GL. Therefore, the extension path of the semiconductor pattern SC not only overlaps the gate electrode GE1 but also further overlaps the scan line GL. More specifically, the orthographic projection of the portion of the semiconductor pattern SC extending from the drain region DR to the source region SR in this embodiment on the substrate 100 is generally L-shaped, but this is not a limitation.

[0063] In this embodiment, the portion where the scan line GL overlaps the semiconductor pattern SC can serve as another gate GE2 of the active device T. Conversely, the portion where the semiconductor pattern SC overlaps the scan line GL can serve as another channel region CH2 of the semiconductor pattern SC, and opposite sides of the channel region CH2 can be connected to the lightly doped regions LDR. Meanwhile, the portion where the data line DL overlaps the source region SR of the semiconductor pattern SC can serve as the source SE of the active device T, but this is not limited to this. In another embodiment, the source of the active device can also be formed by the portion protruding from the data line DL.

[0064] In this embodiment, the gate electrodes GE1 and GE2 of the active device T may be selectively disposed above the semiconductor pattern SC to form a top-gate thin-film transistor (TFT), but the present invention is not limited thereto. According to other embodiments, the gate electrodes GE1 and GE2 of the active device may also be disposed below the semiconductor pattern SC to form a bottom-gate thin-film transistor (TFT). Furthermore, the semiconductor pattern SC in this embodiment may be made of polysilicon semiconductor material, meaning that the active device T may be a low-temperature polysilicon thin-film transistor (LTPS TFT). However, the present invention is not limited thereto. In other embodiments, the active device may also be an amorphous silicon thin-film transistor (a-Si TFT), a microcrystalline silicon thin-film transistor (micro-Si TFT), a metal oxide transistor (MT), an oxynitride semiconductor, an organic semiconductor, a combination thereof, or other suitable materials.

[0065] The steps of forming the active device T may include: sequentially forming a buffer layer BL, a semiconductor pattern SC, a gate insulating layer GI, gates GE1 and GE2, an interlayer insulating layer ILD, a source electrode SE, and a drain electrode DE on the substrate 100, wherein the source electrode SE and the drain electrode DE are electrically connected to the source region SR and the drain region DR of the semiconductor pattern SC via through holes TH1 and TH2 in the interlayer insulating layer ILD and the gate insulating layer GI, respectively.

[0066] It should be noted that the gate GE1, the gate GE2, the source SE, the drain DE, the buffer layer BL, the gate insulating layer GI, the interlayer insulating layer ILD and the planarizing layer PL can be respectively realized by any gate, any source, any drain, any buffer layer, any gate insulating layer, any interlayer insulating layer and any planarizing layer for a display panel known to any technician in the relevant technical field, and the gate GE1, the gate GE2, the source SE, the drain DE, the buffer layer BL, the gate insulating layer GI, the interlayer insulating layer ILD and the planarizing layer PL can respectively be formed by any method known to any technician in the relevant technical field, so they will not be elaborated here.

[0067] In this embodiment, the display panel 10 may further include a plurality of common electrodes CE, each of which overlaps with the plurality of pixel electrodes PE of the plurality of pixel structures PX. For example, the steps of forming the common electrode CE and the pixel electrode PE may include sequentially forming a planarization layer PL, a common electrode CE, a passivation layer PV, and a pixel electrode PE on the active device T, wherein the pixel electrode PE is electrically connected to the drain DE of the active device T via an opening PLa in the planarization layer PL and an opening PVa in the passivation layer PV.

[0068] Furthermore, the semiconductor pattern SC of the active device T further includes an extension region ETR extending from the drain region DR. The extension region ETR of the semiconductor pattern SC of the active device T electrically connected to any data line DL extends away from the channel region CH1 and the source region SR of the active device T and overlaps the other data line DL. In this embodiment, the orthographic projection of the extension region ETR of the semiconductor pattern SC on the substrate 100 is generally L-shaped, but this is not limiting.

[0069] For example, if Figure 2 As shown, a first active element T1 and a pixel electrode PE of a first pixel structure PX1 are disposed between data lines DL1 and DL2 of the display panel 10. The source electrode SE of the first active element T1 is electrically connected to the data line DL1. The extension region ETR of the semiconductor pattern SC of the first active element T1 extends toward and overlaps with the data line DL2. Similarly, a second active element T2 and a pixel electrode PE of a second pixel structure PX2 are disposed between the data lines DL2 and DL3. The source electrode SE of the second active element T2 is electrically connected to the data line DL2. The extension region ETR of the semiconductor pattern SC of the second active element T2 extends toward and overlaps with the data line DL3.

[0070] In this embodiment, the gate GE1 of the first active element T1 of the first pixel structure PX1 and the gate GE1 of the second active element T2 of the second pixel structure PX2 may be electrically connected to the same scan line GL, but the present invention is not limited thereto. In other embodiments not shown, the gates of the active elements of two adjacent pixel structures arranged along the direction X may also be electrically connected to different scan lines.

[0071] Because the polarity of data line DL1 is opposite to that of data line DL2, the compensation capacitor C (i.e., capacitive coupling effect) formed by the overlap between the extended region ETR of the semiconductor pattern SC of the first active device T1 and the data line DL2 can reduce the potential offset of the pixel electrode PE of the first pixel structure PX1 electrically connected to the data line DL1 via the first active device T1 within a single frame period. Similarly, because the polarity of data line DL2 is opposite to that of data line DL3, the capacitive coupling effect generated by the overlap between the extended region ETR of the semiconductor pattern SC of the second active device T2 and the data line DL3 can reduce the potential offset of the pixel electrode PE of the second pixel structure PX2 electrically connected to the data line DL2 via the second active device T2 within a single frame period. Consequently, when the display panel 10 operates at a lower frame refresh rate (e.g., 20 Hz), display quality can be improved.

[0072] Please refer to Figure 2 In this embodiment, the extension region ETR of the semiconductor pattern SC of the first active device T1 of the first pixel structure PX1 can further extend into the pixel region where the second pixel structure PX2 is located. In other words, the extension region ETR of the semiconductor pattern SC of the first active device T1 can extend to the side of the data line DL2 where the second active device T2 is located. Similarly, the extension region ETR of the semiconductor pattern SC of the second active device T2 can extend to the side of the data line DL3 away from the second active device T2 (i.e., the side where the third active device is located).

[0073] It is particularly noted that a first distance d1 is spaced between the drain electrode DE of the second active device T2 and the data line DL2 along the data line DL arrangement direction (e.g., direction X), while a second distance d2 is spaced between the side edge Re of the extended region ETR of the semiconductor pattern SC of the first active device T1, which is closest to the drain electrode DE of the second active device T2, and the data line DL2 along the direction X. Preferably, the ratio of the second distance d2 to the first distance d1 is less than 0.5. For example, when the first distance d1 is 9.5 microns and the display panel 10 operates at a frame refresh rate of 20 Hz, the flicker values ​​corresponding to second distances d2 of 0 microns, 1 micron, and 2 microns are -24 dB, -27 dB, and -27.3 dB, respectively.

[0074] That is, as the extended region ETR of the semiconductor pattern SC of the first active device T1 gets closer to the drain DE of the second active device T2, the capacitive coupling effect between the extended region ETR of the semiconductor pattern SC of the first active device T1 and the data line DL2 with opposite polarity and the drain DE of the second active device T2 becomes greater, thereby helping to further improve the display flicker phenomenon when the display panel 10 operates at a lower frame refresh rate (e.g., 20 Hz).

[0075] However, it should be noted that the extension region ETR of the semiconductor pattern SC of the first active device T1 does not overlap with the semiconductor pattern SC and drain DE of the second active device T2, to avoid capacitive coupling with the second active device T2 and thereby affecting the operating electrical properties of the second pixel structure PX2 (e.g., the potential of the pixel electrode PE of the second pixel structure PX2). From another perspective, the side edge Re of the extension region ETR of the semiconductor pattern SC of the first active device T1 that faces the drain DE of the second active device T2 is located within the space between the data line DL2 and the drain DE of the second active device T2.

[0076] Since the extension region ETR of the semiconductor pattern SC of the second active device T2 or other active devices T is configured in the same manner as that of the first active device T1 , further details will not be given here.

[0077] Furthermore, the aforementioned substrate 100 and the various film layers thereon may constitute the pixel array substrate of the display panel 10. The display panel 10 may further include a liquid crystal layer (not shown) and a color filter substrate (not shown), wherein the liquid crystal layer is sandwiched between the pixel array substrate and the color filter substrate. That is, the display panel 10 of this embodiment may be a liquid crystal display panel. For example, the electric field generated between the aforementioned pixel electrode PE and the common electrode CE may be used to change the alignment of the plurality of liquid crystal molecules in the liquid crystal layer, thereby modulating the polarization state of light after passing through the liquid crystal layer to achieve varying degrees of grayscale display effects. Since the composition and configuration of the liquid crystal layer and the color filter substrate may be formed using any liquid crystal layer and any color filter substrate known to those skilled in the art for use in liquid crystal display panels, they will not be described in detail here.

[0078] In the present embodiment, the pixel electrode PE may have a plurality of slits SLT, and the common electrode CE is located between the pixel electrode PE and the substrate 100. More specifically, the pixel structure PX of the present embodiment drives the aforementioned liquid crystal layer in, for example, a Fringe Field Switching (FFS) mode. However, the present invention is not limited thereto. In another embodiment, the pixel electrode may also be disposed between the common electrode and the substrate 100, and the common electrode may have a plurality of slits. In yet another embodiment, the common electrode and the pixel electrode may also be disposed on different substrates, respectively, that is, the pixel structure may also be driven in a vertical alignment (VA) mode. In yet another embodiment, in addition to the above, Figure 3 In addition to the structure, another common electrode may also be provided on another substrate of the display panel, that is, the pixel structure is driven in a mixed mode of fringe field switching FFS and vertical alignment VA.

[0079] On the other hand, in order to prevent external ambient light from irradiating the channel area CH1 and the channel area CH2 of the semiconductor pattern SC and generating leakage current, the display panel 10 may also selectively include a plurality of shading patterns, for example: a shading pattern SM1 and a shading pattern SM2 corresponding to each pixel structure PX. The shading pattern SM1 overlaps with the channel area CH1 of the semiconductor pattern SC. The shading pattern SM2 overlaps with the channel area CH2 of the semiconductor pattern SC. It is particularly noteworthy that in this embodiment, the channel area CH2 of the semiconductor pattern SC overlaps with the scan line GL and the data line DL at the same time. That is to say, the multiple shading patterns SM2 of the display panel 10 overlap at the intersection of multiple scan lines GL and multiple data lines DL, for example Figure 2 The data lines DL1, DL2 and DL3 in the figure are respectively located at intersections with the scan lines GL, but the present invention is not limited thereto.

[0080] For example, in this embodiment, the light-shielding pattern SM1 and the light-shielding pattern SM2 may be selectively disposed between the semiconductor pattern SC and the substrate 100 and covered by the buffer layer BL, but the present invention is not limited thereto.

[0081] Some other embodiments will be listed below to illustrate the present invention in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the above embodiments and will not be repeated below.

[0082] Figure 4 is a schematic front view of a display panel according to a second embodiment of the present invention. Figure 5 is a schematic front view of a display panel of a comparative example. Figure 6A 1 is a flicker value distribution diagram of a display panel according to a comparative example and an embodiment of the present invention operating at a frame refresh rate of 60 Hz. Figure 6B 1 is a flicker value distribution diagram of a display panel according to a comparative example and an embodiment of the present invention operating at a frame refresh rate of 20 Hz.

[0083] Please refer to Figure 4 The display panel 10A of this embodiment is Figure 2 The difference between the display panel 10 and the display panel 10A is that the configuration of the semiconductor pattern is different. Specifically, in this embodiment, the semiconductor pattern SC-A of the active device TA of the display panel 10A further has a protrusion PTD that protrudes from the extension region ETR and overlaps the data line DL.

[0084] For example, in this embodiment, the extension region ETR of the semiconductor pattern SC-A of the first active element T1-A of the first pixel structure PX1-A can further extend a protrusion PTD along the extension direction of the data line DL2 (for example, direction Y) in the portion overlapping with the data line DL2, and the extension region ETR of the semiconductor pattern SC-A of the second active element T2-A of the second pixel structure PX2-A can further extend a protrusion PTD along the extension direction of the data line DL3 in the portion overlapping with the data line DL3.

[0085] From another perspective, the extension region ETR of the semiconductor pattern SC-A of this embodiment is located on one side (eg, Figure 4 The protrusion PTD is extended from the lower side of the semiconductor pattern to overlap with the data line DL, but the present invention is not limited thereto. In another embodiment, the protrusion of the semiconductor pattern may also extend from the upper side of the extension region ETR.

[0086] Please refer to Figure 6A and Figure 6BCompared to the display panel 10 of the first embodiment, the display panel 10A of this embodiment (i.e., the second embodiment) has a better screen flicker value at either a 60 Hz or 20 Hz screen refresh rate because the semiconductor pattern SC-A has an additional protrusion PTD. In addition, whether it is the display panel 10 of the first embodiment of the present invention or the display panel 10A of the second embodiment, its screen flicker value at a 60 Hz or 20 Hz screen refresh rate is significantly better than that of the display panel 10C of the comparative example. Here, the display panel 10C of the comparative example (e.g., Figure 5 The semiconductor pattern SC-C of the first active element T1-C of the first pixel structure PX1-C (or the second active element T2-C of the second pixel structure PX2-C) does not have the same Figure 2 That is, in the display panel 10C of the comparative example, the semiconductor pattern SC-C of the first active device T1-C does not overlap with the data line DL2 of opposite polarity, and the semiconductor pattern SC-C of the second active device T2-C does not overlap with the data line DL3 of opposite polarity.

[0087] In summary, in a display panel according to one embodiment of the present invention, two data lines of opposite polarity are provided on opposite sides of an active element, each electrically connected to one of the data lines. By extending the semiconductor pattern of the active element toward and overlapping the other data line, the potential offset of the pixel electrode electrically connected to the active element can be reduced when the display panel operates at a low frame rate (e.g., 20Hz), thereby improving the problem of display flicker.

Claims

1. A display panel, comprising: a substrate; a plurality of data lines arranged at intervals on the substrate, the data lines including a first data line, a second data line, and a third data line arranged in sequence, the first data line and the third data line each having a first polarity, the second data line having a second polarity, and the first polarity being different from the second polarity; A plurality of scan lines are arranged at intervals on the substrate, and the data lines intersect with the scan lines and define a plurality of pixel areas; A plurality of active devices are respectively disposed in the pixel regions and each includes a semiconductor pattern, a source, a drain, and a gate. The gate is electrically connected to one of the scan lines. The semiconductor pattern has a source region and a drain region connected to the source and the drain, respectively, a channel region connected between the source and drain regions, and an extension region extending from the drain region. The active devices include: a first active device disposed between the first data line and the second data line, the source of the first active device being electrically connected to the first data line, and the extension region of the semiconductor pattern of the first active device extending toward the second data line and overlapping with the second data line; and a second active device disposed between the second data line and the third data line, the source of the second active device being electrically connected to the second data line, and the extension region of the semiconductor pattern of the second active device extending toward the third data line and overlapping the third data line; and A plurality of pixel electrodes are respectively disposed in the pixel regions and are respectively electrically connected to the plurality of drains of the active elements. 2 . The display panel as claimed in claim 1 , wherein the extension region of the semiconductor pattern of the first active device extends to a side of the second data line where the second active device is disposed. 3 . The display panel as claimed in claim 2 , wherein the extension region of the semiconductor pattern of the second active device extends to a side of the third data line away from the second active device. 4 . The display panel as claimed in claim 2 , wherein the extension region of the semiconductor pattern of the first active device does not overlap with the semiconductor pattern and the drain of the second active device.

5. The display panel as described in claim 2, wherein the drain of the second active element and the second data line have a first distance along an arrangement direction of the data lines, and a side edge of the extension region of the semiconductor pattern of the first active element closest to the drain of the second active element has a second distance from the second data line along the arrangement direction, and the ratio of the second distance to the first distance is less than 0.

5. 6 . The display panel as claimed in claim 1 , wherein the semiconductor pattern of each of the active devices further comprises a protruding portion protruding from the extension region and overlapping one of the data lines. 7 . The display panel as claimed in claim 6 , wherein a protruding direction of the protruding portion is parallel to an extending direction of the data lines.

8. The display panel according to claim 1, further comprising: A plurality of common electrodes are respectively arranged to overlap the pixel electrodes. 9 . The display panel as claimed in claim 8 , wherein each of the pixel electrodes or each of the common electrodes has a plurality of slits. 10 . The display panel as claimed in claim 1 , wherein the gate of the first active device and the gate of the second active device are electrically connected to the same one of the scan lines. 11 . The display panel as claimed in claim 1 , wherein the semiconductor pattern of each of the active devices further comprises another channel region overlapping an intersection of one of the scan lines and one of the data lines.

12. The display panel according to claim 11, further comprising: A plurality of light shielding patterns are disposed on the substrate and overlap the plurality of channel regions and the plurality of another channel regions of the plurality of semiconductor patterns of the active elements. 13 . The display panel as claimed in claim 1 , wherein the extension region, the drain region, and the source region of the semiconductor pattern have the same resistance.

14. A display panel comprising: a substrate; A plurality of first data lines and a plurality of second data lines are alternately arranged on the substrate, each of the first data lines has a first polarity, each of the second data lines has a second polarity, and the first polarity is different from the second polarity; A plurality of scan lines are arranged on the substrate at intervals, and the scan lines intersect the first data lines and the second data lines; a first pixel structure disposed between one of the first data lines and one of the second data lines, and having a first active device and a first pixel electrode, the first active device including a first semiconductor pattern, a first source, a first drain, and a first gate, the first source electrically connected to the one of the first data lines and a first source region of the first semiconductor pattern, the first drain electrically connected to the first pixel electrode and a first drain region of the first semiconductor pattern, the first gate overlapping a first channel region of the first semiconductor pattern, the first channel region connected between the first source region and the first drain region; and a second pixel structure disposed between one of the second data lines and another of the first data lines, and having a second active element and a second pixel electrode, the second active element including a second semiconductor pattern, a second source, a second drain, and a second gate, the second source electrically connected to the one of the second data lines and a second source region of the second semiconductor pattern, the second drain electrically connected to the second pixel electrode and a second drain region of the second semiconductor pattern, the second gate overlapping a second channel region of the second semiconductor pattern, the second channel region connected between the second source region and the second drain region, The first semiconductor pattern has a first extension region extending from the first drain region, the second semiconductor pattern has a second extension region extending from the second drain region, the first extension region of the first semiconductor pattern extends toward one of the second data lines and overlaps with the one of the second data lines, and the second extension region of the second semiconductor pattern extends toward the other one of the first data lines and overlaps with the other one of the first data lines. 15 . The display panel as claimed in claim 14 , wherein the first extension region of the first semiconductor pattern extends to a side of the one of the second data lines where the second drain is disposed. 16 . The display panel as claimed in claim 15 , wherein the second extension region of the second semiconductor pattern extends to a side of the other one of the first data lines away from the second drain. 17 . The display panel as claimed in claim 15 , wherein the first extension region of the first semiconductor pattern does not overlap with the second semiconductor pattern and the second drain.

18. A display panel as described in claim 15, wherein the second drain and one of the second data lines have a first distance along an arrangement direction of the second data lines, and a side edge of the first extension region of the first semiconductor pattern closest to the second drain and one of the second data lines have a second distance along the arrangement direction, and the ratio of the second distance to the first distance is less than 0.

5.

19. A display panel as described in claim 14, wherein the first semiconductor pattern further has a first protrusion protruding from the first extension area and overlapping with one of the second data lines, and the second semiconductor pattern further has a second protrusion protruding from the second extension area and overlapping with the other one of the first data lines, and the protruding directions of the first protrusion and the second protrusion are parallel to the extension directions of the first data lines and the second data lines.

20. The display panel according to claim 14, further comprising: A plurality of light shielding patterns are disposed on the substrate and overlap the first channel region of the first semiconductor pattern, the second channel region of the second semiconductor pattern, the intersections of the scan lines and the first data lines, and the intersections of the scan lines and the second data lines.

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