A high-speed voltage offset compensation system

Abstract

The present invention discloses a high-speed voltage offset compensation system, belonging to the field of integrated circuits, which includes an equalizer, a differential amplification module, a voltage offset judgment and detection module, and a voltage offset calibration module. The equalizer is used to equalize the monitoring and compensation of the DC offset voltage, and perform equalization compensation adjustment based on this until the signal reaches the optimal equalization state; the differential amplification module performs limiting amplification on the output signal of the equalizer to make the signal close to the ideal binary signal and outputs a reference signal for comparison; the voltage offset judgment and detection module compares the reference signal through a two-stage differential amplifier structure to output a voltage offset signal; the voltage offset calibration module quickly searches for the differential voltage offset, determines the offset depth, and performs offset compensation with variable precision. The present invention can reduce the static current, improve the accuracy and speed, and can achieve fast and high-precision compensation of the offset voltage in a high-speed environment.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a high-speed voltage offset compensation system. Background Art

[0002] Currently, the offset cancellation technology mainly adopts the input offset storage technology, which can effectively eliminate the offset voltage brought by the operational amplifier, but this structure requires a common-mode feedback and a bias circuit, making the circuit structure complex. Summary of the Invention

[0003] The purpose of the present invention is to provide a high-speed voltage offset compensation system to solve the problems in the background art.

[0004] To solve the above technical problems, the present invention provides a high-speed voltage offset compensation system, including:

[0005] An equalizer, which equalizes by monitoring and compensating the DC offset voltage, and adjusts the equalization compensation accordingly until the signal reaches the optimal equalization state;

[0006] A differential amplification module, which amplifies the output signal of the equalizer with limited amplitude to make the signal close to the ideal binary signal and outputs a reference signal for comparison;

[0007] A voltage offset judgment and detection module, which compares the reference signal through a two-stage differential amplifier structure and outputs a voltage offset signal;

[0008] A voltage offset calibration module, which quickly searches for the differential voltage offset, determines the offset depth, and compensates the offset with variable precision.

[0009] In one embodiment, the equalizer includes a linear analog equalizer and an offset voltage adjustment array;

[0010] The linear analog equalizer equalizes the input high-speed signal and controls the high-frequency gain through an adaptive source-level negative feedback capacitor;

[0011] The offset voltage adjustment array changes its current magnitude through a control matrix to adjust the output voltage.

[0012] In one embodiment, the linear analog equalizer includes a first triode, a second triode, a first resistor, a second resistor, a third resistor, a first capacitor, a first PMOS transistor, a second PMOS transistor, a first current source, and a ninth NMOS transistor to a twelfth NMOS transistor;

[0013] The bases of the first triode and the second triode are respectively connected to the differential signals INN and INP, the emitters are respectively connected to both ends of the third resistor and both ends of the first capacitor, and the collectors are respectively connected to the power supply VDD through the first resistor and the second resistor; the emitters of the first triode and the second triode are simultaneously grounded through the first current source;

[0014] The drain terminals of the first PMOS transistor and the second PMOS transistor are respectively connected to the collectors of the first triode and the second triode; the gate terminals of the first PMOS transistor and the second PMOS transistor are both connected to the n9 signal; the source terminal of the first PMOS transistor is simultaneously connected to the drain terminals of the ninth NMOS transistor and the twelfth NMOS transistor, and the source terminal of the second PMOS transistor is simultaneously connected to the drain terminals of the tenth NMOS transistor and the eleventh NMOS transistor;

[0015] The gate terminal of the ninth NMOS transistor is connected to the b1 signal, the gate terminal of the tenth NMOS transistor is connected to the b3 signal, the gate terminal of the eleventh NMOS transistor is connected to the b4 signal, the gate terminal of the twelfth NMOS transistor is connected to the b2 signal, and the source terminals of the ninth NMOS transistor to the twelfth NMOS transistor are all grounded.

[0016] In one embodiment, the offset voltage adjustment array includes the first NMOS transistor to the eighth NMOS transistor, the thirteenth NMOS transistor to the fifteenth NMOS transistor, the first inverter, and the second inverter;

[0017] The input terminal of the first inverter is connected to the start signal, and the output terminal is simultaneously connected to the second inverter and the gate terminal of the fifteenth NMOS transistor. The output terminal of the second inverter is connected to the gate terminal of the thirteenth NMOS transistor. The drain terminal of the thirteenth NMOS transistor is connected to VDD, and the source terminal is simultaneously connected to the drain terminals of the fourteenth NMOS transistor and the fifteenth NMOS transistor. The source terminals of the fourteenth NMOS transistor and the fifteenth NMOS transistor are both grounded; the drain terminal of the fourteenth NMOS transistor is connected to its own gate terminal;

[0018] The source terminals of the first NMOS transistor, the third NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor are simultaneously connected to the gate terminal of the fourteenth NMOS transistor; the drain terminals of the first NMOS transistor, the third NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor are respectively connected to the drain terminals of the second NMOS transistor, the fourth NMOS transistor, the sixth NMOS transistor, and the eighth NMOS transistor; the source terminals of the second NMOS transistor, the fourth NMOS transistor, the sixth NMOS transistor, and the eighth NMOS transistor are all grounded; the gate terminals of the first NMOS transistor to the eighth NMOS transistor are respectively connected to the n1 signal to the n8 signal.

[0019] In one embodiment, the differential amplification module includes a programmable gain amplification circuit, a limiting amplification module A, and a limiting amplification module B;

[0020] The programmable gain amplifier circuit amplifies the equalized signal, can conduct a very large current, and accelerates the signal amplification rate;

[0021] The limiting amplifier module A and the limiting amplifier module B perform limiting amplification on the output signal of the programmable gain amplifier circuit, making the signal close to an ideal binary signal, and simultaneously outputting two reference signals for comparison in the subsequent stage.

[0022] In one embodiment, the programmable gain amplifier circuit includes a third triode to a sixth triode, a third resistor, a fourth resistor, and a second current source;

[0023] The bases of the third triode and the fourth triode are connected to the equalized signal, the collectors are both connected to the power supply VDD, and the emitters are respectively connected to the collectors of the fifth triode and the sixth triode; the bases of the fifth triode and the sixth triode are interconnected, and the emitters are respectively grounded through the third resistor and the fourth resistor.

[0024] The positive pole of the second current source is simultaneously connected to the bases of the fifth triode and the sixth triode, and the negative pole is grounded.

[0025] In one embodiment, the limiting amplifier module A includes a sixteenth NMOS transistor to a twenty-first NMOS transistor, a third current source to a fifth current source;

[0026] The drain terminals of the sixteenth NMOS transistor and the seventeenth NMOS transistor are respectively connected to the power supply VDD through a resistor, and the source terminals are grounded through the third current source; the drain terminals of the eighteenth NMOS transistor and the nineteenth NMOS transistor are respectively connected to the power supply VDD through a resistor, and the source terminals are grounded through the fourth current source; the drain terminals of the twentieth NMOS transistor and the twenty-first NMOS transistor are respectively connected to the power supply VDD through a resistor, and the source terminals are grounded through the fifth current source;

[0027] The gate terminal of the sixteenth NMOS transistor is connected to the emitter of the third triode, the gate terminal of the seventeenth NMOS transistor is connected to the emitter of the fourth triode, the gate terminal of the eighteenth NMOS transistor is connected to the drain terminal of the sixteenth NMOS transistor, the gate terminal of the nineteenth NMOS transistor is connected to the drain terminal of the seventeenth NMOS transistor, the gate terminal of the twentieth NMOS transistor is connected to the drain terminal of the nineteenth NMOS transistor, and the gate terminal of the twenty-first NMOS transistor is connected to the drain terminal of the eighteenth NMOS transistor;

[0028] The limiting amplifier module B and the limiting amplifier module A are mirror modules of each other and have the same structure.

[0029] In one embodiment, the voltage offset judgment and detection module includes a third PMOS transistor to a sixth PMOS transistor, a twenty-second NMOS transistor to a twenty-fifth NMOS transistor;

[0030] The source terminals of the third to sixth PMOS transistors are all connected to the power supply VDD. The gate terminal of the third PMOS transistor is simultaneously connected to the gate terminal and the drain terminal of the fourth PMOS transistor. The drain terminal of the third PMOS transistor is connected to the drain terminal of the twenty-fifth NMOS transistor. The drain terminal of the fourth PMOS transistor is connected to the drain terminal of the twenty-third NMOS transistor. The source terminal of the twenty-third NMOS transistor is connected to the positive pole of the sixth current source, and the reference signal is input to the gate terminal.

[0031] The gate terminal of the twenty-fifth NMOS transistor is connected to the gate terminal and the drain terminal of the twenty-fourth NMOS transistor. The source terminals of the twenty-fifth NMOS transistor and the twenty-fourth NMOS transistor are grounded.

[0032] The gate terminal of the sixth PMOS transistor is simultaneously connected to the gate terminal and the drain terminal of the fifth PMOS transistor. The drain terminal of the sixth PMOS transistor is connected to the drain terminal of the twenty-fourth NMOS transistor. The drain terminal of the fifth PMOS transistor is connected to the drain terminal of the twenty-second NMOS transistor. The source terminal of the twenty-second NMOS transistor is connected to the positive pole of the sixth current source, and the reference signal is input to the gate terminal.

[0033] In one embodiment, the voltage offset calibration module adopts the SAR voltage offset calibration algorithm to subdivide the entire output offset voltage VOUT according to the accuracy.

[0034] A high-speed voltage offset compensation system provided by the present invention, compared with the traditional compensation algorithm, has a reduced static current, improved accuracy, and increased speed. Because it is digitally implemented, the ability to resist noise interference is greatly enhanced, and fast and high-precision compensation of the offset voltage in a high-speed environment can be achieved. Brief Description of the Drawings

[0035] Figure 1 It is a block diagram of a high-speed voltage offset compensation system provided by the present invention.

[0036] Figure 2 It is a schematic circuit diagram of the equalizer.

[0037] Figure 3 It is a schematic circuit diagram of the differential amplification module.

[0038] Figure 4 It is a schematic circuit diagram of the voltage offset judgment and detection module.

[0039] Figure 5 It is a schematic circuit diagram of the voltage offset calibration module. Detailed Embodiments

[0040] The following further describes in detail a high-speed voltage offset compensation system proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0041] The present invention provides a high-speed voltage offset compensation system, and its structural block diagram is as Figure 1 shown, including an equalizer, a differential amplification module, a voltage offset judgment and detection module, and a voltage offset calibration module. The equalizer is used to equalize the monitoring and compensation of the DC offset voltage, and perform equalization compensation adjustment based on this until the signal reaches the best equalization state; the differential amplification module performs clipping amplification on the output signal of the equalizer to make the signal close to the ideal binary signal and outputs a reference signal for comparison; the voltage offset judgment and detection module compares the reference signal through a two-stage differential amplifier structure and outputs a voltage offset signal; the voltage offset calibration module quickly searches for the differential voltage offset, determines the offset depth, and performs offset compensation with variable precision.

[0042] The internal structure of the equalizer consists of a linear analog equalizer and an offset voltage adjustment array. The upper part is a linear analog equalizer, and the lower part is a bias matrix controlled by the digital terminal. The two are superimposed on the output OUTP / OUTN to achieve the effect of changing the current size. Its framework diagram is shown in Figure 2 , the linear analog equalizer includes transistors Q1 to Q2, resistors R1 to R3, capacitor C1, PMOS transistors P1 to P2, current source I1, and NMOS transistors M9 to M12; the bases of transistors Q1 and Q2 are respectively connected to the differential signals INN and INP, the emitters are respectively connected to both ends of resistor R3 and both ends of capacitor C1, and the collectors are respectively connected to the power supply VDD through resistors R1 and R2; the emitters of transistors Q1 and Q2 are simultaneously grounded through current source I1; the drain terminals of PMOS transistors P1 and P2 are respectively connected to the collectors of transistors Q1 and Q2; the gate terminals of PMOS transistors P1 and P2 are both connected to the n9 signal; the source terminal of PMOS transistor P1 is simultaneously connected to the drain terminals of NMOS transistor M9 and NMOS transistor M12, and the source terminal of PMOS transistor P2 is simultaneously connected to the drain terminals of NMOS transistor M10 and NMOS transistor M11; the gate terminal of NMOS transistor M9 is connected to the b1 signal, the gate terminal of NMOS transistor M10 is connected to the b3 signal, the gate terminal of NMOS transistor M11 is connected to the b4 signal, the gate terminal of NMOS transistor M12 is connected to the b2 signal, and the source terminals of NMOS transistors M9 to M12 are all grounded.

[0043] The offset voltage regulation array includes NMOS transistors M1 to M8, NMOS transistors M13 to M15, and inverters INV1 to INV2. The input terminal of inverter INV1 is connected to a start signal, and the output terminal is simultaneously connected to the gate terminal of inverter INV2 and NMOS transistor M15. The output terminal of inverter INV2 is connected to the gate terminal of NMOS transistor M13. The drain terminal of NMOS transistor M13 is connected to VDD, and the source terminal is simultaneously connected to the drain terminals of NMOS transistor M14 and NMOS transistor M15. The source terminals of NMOS transistor M14 and NMOS transistor M15 are both grounded. The drain terminal of NMOS transistor M14 is connected to its own gate terminal. The source terminals of NMOS transistors M1, M3, M5, and M7 are simultaneously connected to the gate terminal of NMOS transistor M14. The drain terminals of NMOS transistors M1, M3, M5, and M7 are respectively connected to the drain terminals of NMOS transistors M2, M4, M6, and M8. The source terminals of NMOS transistors M2, M4, M6, and M8 are all grounded. The gate terminals of NMOS transistors M1 to M8 are respectively connected to signals n1 to n8.

[0044] The specific working process of the linear analog equalizer is as follows:

[0045] INP and INN are input differential signals. The signals pass through the analog differential operational amplifiers of the analog linear equalizer CTLE for transistors Q1 and Q2, and the equalization gain is adjusted through resistor R3 and programmable capacitor C1. The signals are sent to the output terminals OUTP / OUTN. At this time, if a voltage offset occurs in the system, the offset signal is transmitted to terminals a1, a2, a3, a4, and a5 through the digital SAR offset compensation algorithm. Among them, a5 is a judgment signal for determining whether to adjust the left matrix or the right matrix. If a5 is '1', the left bias matrix starts to work. If a5 is '0', the right bias matrix works. a1, a2, a3, and a4 in the adjustment signals are adjustment signals with precision. When the left side starts to work, if a1 is '0', then n2 is '1' and n1 is '0', so NMOS transistor M1 is turned off and NMOS transistor M2 is turned on, resulting in b1 being at a low level, NMOS transistor M9 is turned off, and there is no current change in PMOS transistor P1, and there is no adjustment change in the system. If a1 is '1', then n2 is '0' and n1 is '1', so NMOS transistor M2 is turned off and NMOS transistor M1 is turned on. The bias current source composed of NMOS transistors M13, M15, and M14 provides current to b1 through NMOS transistor M1. NMOS transistor M9 causes a current change in PMOS transistor P1, and the system starts to make adjustments. Finally, the adjusted current is added to the OUT / OUTP output and output to the subsequent module. Other signals such as a2, a3, a4, etc. are similar.

[0046] The differential amplification module includes a programmable gain amplification circuit, a limiting amplification module A, and a limiting amplification module B, and its structure is shown in Figure 3 . The programmable gain amplification circuit includes transistors Q3 to Q6, resistor R3, resistor R4, and current source I2; the bases of transistors Q3 and Q4 are connected to the balanced signal, the collectors are both connected to power supply VDD, and the emitters are respectively connected to the collectors of transistors Q5 and Q6; the bases of transistors Q5 and Q6 are interconnected, and the emitters are grounded through resistor R3 and resistor R4 respectively; the positive pole of current source I2 is simultaneously connected to the bases of transistors Q5 and Q6, and the negative pole is grounded.

[0047] The limiting amplification module A includes NMOS transistors M16 to M21, current sources I3 to I5; the drain terminals of NMOS transistors M16 and M17 are respectively connected to power supply VDD through a resistor, and the source terminals are grounded through current source I3; the drain terminals of NMOS transistors M18 and M19 are respectively connected to power supply VDD through a resistor, and the source terminals are grounded through current source I4; the drain terminals of NMOS transistors M20 and M21 are respectively connected to power supply VDD through a resistor, and the source terminals are grounded through current source I5; the gate terminal of NMOS transistor M16 is connected to the emitter of transistor Q3, the gate terminal of NMOS transistor M17 is connected to the emitter of transistor Q4, the gate terminal of NMOS transistor M18 is connected to the drain terminal of NMOS transistor M16, the gate terminal of NMOS transistor M19 is connected to the drain terminal of NMOS transistor M17, the gate terminal of NMOS transistor M20 is connected to the drain terminal of NMOS transistor M19, and the gate terminal of NMOS transistor M21 is connected to the drain terminal of NMOS transistor M18;

[0048] The limiting amplification module B and the limiting amplification module A are mirror modules with the same structure.

[0049] The specific working process of the differential amplification module is as follows:

[0050] The balanced signal is the differential pair INN / INP, which is amplified by the programmable gain amplification circuit (i.e., VGA). This VGA circuit includes a pair of transistors Q3 and Q4. This structure can conduct a large current, and the large current can accelerate the signal amplification rate. This circuit uses a current source I2 connected to the bases of transistors Q5 and Q6, so that the current source I2 can control the conduction effect of transistors Q5 and Q6, thereby generating a large current to control the current magnitude of the differential pair of transistors Q3 and Q4, so as to achieve the purpose of gain improvement. The amplified signal is subjected to limiting amplification of the VGA output signal by module A and module B to make the signal close to the ideal binary signal, and at the same time, two reference signals OUTA and OUTB for subsequent comparison are output. Module A and module B are mirror modules with the same structure, and both contain several limiting amplifiers, such asFigure 3 A similar structure composed of NMOS transistors M16, M17, M18, M19, M20, M21, etc. Among them, there can be many differential pair structures composed of NMOS transistors M16 and M17 cascaded after the differential pair composed of NMOS transistors M16 and M17, not limited to the number shown in the figure. The swing of the output signal of these limiting amplifiers is positively correlated with the magnitude of the tail current. The symmetrical structure composed of NMOS transistors M20 and M21 generates the tail current for it. The current source I5 of this structure can be adjusted, and different tail currents can be generated by adjusting the current source I5.

[0051] The internal structure of the voltage offset judgment and detection module is a second-order comparator, and its structure is shown in Figure 4 , the voltage offset judgment and detection module includes PMOS transistors P3 to P6, NMOS transistors M22 to M25; the source terminals of PMOS transistors P3 to P6 are all connected to the power supply VDD. The gate terminal of PMOS transistor P3 is connected to the gate terminal and drain terminal of PMOS transistor P4 at the same time. The drain terminal of PMOS transistor P3 is connected to the drain terminal of NMOS transistor M25. The drain terminal of PMOS transistor P4 is connected to the drain terminal of NMOS transistor M23. The source terminal of NMOS transistor M23 is connected to the positive pole of current source I6, and the gate terminal is connected to the reference signal. The gate terminal of NMOS transistor M25 is connected to the gate terminal and drain terminal of NMOS transistor M24. The source terminals of NMOS transistors M25 and M24 are grounded. The gate terminal of PMOS transistor P6 is connected to the gate terminal and drain terminal of PMOS transistor P5 at the same time. The drain terminal of PMOS transistor P6 is connected to the drain terminal of NMOS transistor M24. The drain terminal of PMOS transistor P5 is connected to the drain terminal of NMOS transistor M22. The source terminal of NMOS transistor M22 is connected to the positive pole of current source I6, and the gate terminal is connected to the reference signal.

[0052] The specific working process of the voltage offset judgment and detection module is as follows:

[0053] Two reference signals OUTA (i.e., INA) and OUTB (i.e., INB) are used as the inputs of the voltage offset judgment and detection module. This module includes a second-order differential comparison circuit, which is composed of three pairs of current mirrors composed of a pair of differential input pairs of NMOS transistors M22 and M23, four PMOS transistors P6, P3, P4, P5, and two NMOS transistors M24 and M25. After the signal passes through this circuit, it is output single-ended (VOUT), and compared with a single-order comparator, it has higher accuracy.

[0054] The voltage offset calibration module adopts the SAR voltage offset calibration algorithm, and its structure is as shown in Figure 5 shown, and the working process is as follows:

[0055] The entire output offset voltage VOUT is subdivided according to precision. For example, the precision in this embodiment is 5 bits. To improve precision, it can also be further divided into 6 bits, 7 bits, etc. Then the entire voltage can be subdivided into a 16-bit 4-bit + 1-bit adjustment signal, and then the output value of VOUT is sampled. Since 5-bit precision is used for sampling in this embodiment, that is, sampling is carried out with five clock cycles as an adjustment stage, and this stage is a cyclic process. The highest bit, bit5, corresponds to the a5 input terminal in the equalizer, and the other bits correspond to the a1, a2, a3, and a4 input terminals in the equalizer.

[0056] First, the algorithm matrix is given an initial value of '10000'. The selection range of the initial value is the intermediate value between the values of '11000' and '01000'. This is reflected in the current matrix of the analog equalizer as all being turned off. The equalizer enters the initial stage without any current adjustment. At the same time, the highest bit being '1' represents that the offset occurs on the left side of the differential section of the equalizer, and '0' represents that the offset occurs on the right side of the differential section of the equalizer, that is, a3 in the equalizer module.

[0057] In the first cycle, the VOUT output being '0' means that the offset value is greater than '10000'. At the same time, the highest bit '1' represents that the offset is on the right side of the equalizer. Immediately, the initial value is adjusted and the matrix '11000' is given. At this time, it is reflected in the equalizer that the output voltage on the right side is offset, and the current value on the right side of the equalizer is adjusted.

[0058] In the second cycle, the VOUT output being '1' means that the offset value is less than '11000'. '11000' is in the middle of the range between '11100' and '10100'. Immediately, the initial value is adjusted and the matrix '10100' is given. At this time, it is reflected in the equalizer that the output voltage on the right side is offset, and the current value on the right side of the equalizer is adjusted.

[0059] And so on until all five steps are completed, and then a fixed adjustment value is output to completely eliminate the voltage offset.

[0060] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A high-speed voltage offset compensation system, characterized in that, it includes: An equalizer, which monitors and compensates for the DC offset voltage, and adjusts the equalization compensation accordingly until the signal reaches the optimal equalization state; A differential amplification module, which limits and amplifies the output signal of the equalizer to make the signal close to the ideal binary signal and outputs a reference signal for comparison; A voltage offset judgment and detection module, which compares the reference signal through a two-stage differential amplifier structure and outputs a voltage offset signal; A voltage offset calibration module, which quickly searches for the differential voltage offset, determines the offset depth, and compensates for the offset with variable precision; The equalizer includes a linear analog equalizer and an offset voltage adjustment array; The linear analog equalizer equalizes the input high-speed signal and controls the high-frequency gain through an adaptive source-level negative feedback capacitor; The offset voltage adjustment array changes its current magnitude through a control matrix to adjust the output voltage; The linear analog equalizer includes a first triode, a second triode, a first resistor, a second resistor, a third resistor, a first capacitor, a first PMOS transistor, a second PMOS transistor, a first current source, a ninth NMOS transistor to a twelfth NMOS transistor; The bases of the first triode and the second triode are respectively connected to the differential signals INN and INP, the emitters are respectively connected to both ends of the third resistor and both ends of the first capacitor, and the collectors are respectively connected to the power supply VDD through the first resistor and the second resistor; the emitters of the first triode and the second triode are simultaneously grounded through the first current source; The drains of the first PMOS transistor and the second PMOS transistor are respectively connected to the collectors of the first triode and the second triode; the gates of the first PMOS transistor and the second PMOS transistor are both connected to the n9 signal; the source of the first PMOS transistor is simultaneously connected to the drains of the ninth NMOS transistor and the twelfth NMOS transistor, and the source of the second PMOS transistor is simultaneously connected to the drains of the tenth NMOS transistor and the eleventh NMOS transistor; The gate of the ninth NMOS transistor is connected to the b1 signal, the gate of the tenth NMOS transistor is connected to the b3 signal, the gate of the eleventh NMOS transistor is connected to the b4 signal, the gate of the twelfth NMOS transistor is connected to the b2 signal, and the sources of the ninth NMOS transistor to the twelfth NMOS transistor are all grounded; The offset voltage adjustment array includes a first NMOS transistor to an eighth NMOS transistor, a thirteenth NMOS transistor to a fifteenth NMOS transistor, a first inverter, and a second inverter; The input end of the first inverter is connected to the start signal, the output end is simultaneously connected to the gate of the second inverter and the fifteenth NMOS transistor, the output end of the second inverter is connected to the gate of the thirteenth NMOS transistor, the drain of the thirteenth NMOS transistor is connected to VDD, and the source is simultaneously connected to the drains of the fourteenth NMOS transistor and the fifteenth NMOS transistor. The sources of the fourteenth NMOS transistor and the fifteenth NMOS transistor are both grounded; the drain of the fourteenth NMOS transistor is connected to its own gate; The source terminals of the first NMOS transistor, the third NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor are simultaneously connected to the gate terminal of the fourteenth NMOS transistor; the drain terminals of the first NMOS transistor, the third NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor are respectively connected to the drain terminals of the second NMOS transistor, the fourth NMOS transistor, the sixth NMOS transistor, and the eighth NMOS transistor; the source terminals of the second NMOS transistor, the fourth NMOS transistor, the sixth NMOS transistor, and the eighth NMOS transistor are all grounded; the gate terminals of the first NMOS transistor to the eighth NMOS transistor are respectively connected to the n1 signal to the n8 signal.

2. The high-speed voltage offset compensation system according to claim 1, characterized in that, the differential amplification module includes a programmable gain amplification circuit, a limiting amplification module A, and a limiting amplification module B; the programmable gain amplification circuit amplifies the equalized signal, can conduct a very large current, and accelerates the signal amplification rate; the limiting amplification module A and the limiting amplification module B perform limiting amplification on the output signal of the programmable gain amplification circuit, make the signal approach an ideal binary signal, and simultaneously output two reference signals for comparison in the subsequent stage.

3. The high-speed voltage offset compensation system according to claim 2, characterized in that, the programmable gain amplification circuit includes the third triode to the sixth triode, the third resistor, the fourth resistor, and the second current source; the bases of the third triode and the fourth triode are connected to the equalized signal, the collectors are both connected to the power supply VDD, and the emitters are respectively connected to the collectors of the fifth triode and the sixth triode; the bases of the fifth triode and the sixth triode are interconnected, and the emitters are respectively grounded through the third resistor and the fourth resistor; the positive pole of the second current source is simultaneously connected to the bases of the fifth triode and the sixth triode, and the negative pole is grounded.

4. The high-speed voltage offset compensation system according to claim 3, characterized in that, the limiting amplification module A includes the sixteenth NMOS transistor to the twenty-first NMOS transistor, the third current source to the fifth current source; the drain terminals of the sixteenth NMOS transistor and the seventeenth NMOS transistor are respectively connected to the power supply VDD through a resistor, and the source terminals are grounded through the third current source; the drain terminals of the eighteenth NMOS transistor and the nineteenth NMOS transistor are respectively connected to the power supply VDD through a resistor, and the source terminals are grounded through the fourth current source; the drain terminals of the twentieth NMOS transistor and the twenty-first NMOS transistor are respectively connected to the power supply VDD through a resistor, and the source terminals are grounded through the fifth current source; the gate terminal of the sixteenth NMOS transistor is connected to the emitter of the third triode, the gate terminal of the seventeenth NMOS transistor is connected to the emitter of the fourth triode, the gate terminal of the eighteenth NMOS transistor is connected to the drain terminal of the sixteenth NMOS transistor, the gate terminal of the nineteenth NMOS transistor is connected to the drain terminal of the seventeenth NMOS transistor, the gate terminal of the twentieth NMOS transistor is connected to the drain terminal of the nineteenth NMOS transistor, and the gate terminal of the twenty-first NMOS transistor is connected to the drain terminal of the eighteenth NMOS transistor; the limiting amplification module B and the limiting amplification module A are mirror modules to each other and have the same structure.

5. The high-speed voltage offset compensation system according to claim 4, characterized in that, The voltage offset judgment and detection module includes a third PMOS transistor to a sixth PMOS transistor, and a twenty-second NMOS transistor to a twenty-fifth NMOS transistor; The source terminals of the third PMOS transistor to the sixth PMOS transistor are all connected to the power supply VDD. The gate terminal of the third PMOS transistor is simultaneously connected to the gate terminal and the drain terminal of the fourth PMOS transistor. The drain terminal of the third PMOS transistor is connected to the drain terminal of the twenty-fifth NMOS transistor. The drain terminal of the fourth PMOS transistor is connected to the drain terminal of the twenty-third NMOS transistor. The source terminal of the twenty-third NMOS transistor is connected to the positive electrode of the sixth current source, and the gate terminal is connected to the reference signal; The gate terminal of the twenty-fifth NMOS transistor is connected to the gate terminal and the drain terminal of the twenty-fourth NMOS transistor. The source terminals of the twenty-fifth NMOS transistor and the twenty-fourth NMOS transistor are grounded; The gate terminal of the sixth PMOS transistor is simultaneously connected to the gate terminal and the drain terminal of the fifth PMOS transistor. The drain terminal of the sixth PMOS transistor is connected to the drain terminal of the twenty-fourth NMOS transistor. The drain terminal of the fifth PMOS transistor is connected to the drain terminal of the twenty-second NMOS transistor. The source terminal of the twenty-second NMOS transistor is connected to the positive electrode of the sixth current source, and the gate terminal is connected to the reference signal.

6. The high-speed voltage offset compensation system according to claim 5, characterized in that the voltage offset calibration module adopts the SAR voltage offset calibration algorithm to subdivide the entire output offset voltage VOUT according to the accuracy.

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