Method, apparatus, electronic device, and storage medium for data processing

Abstract

The application discloses a data processing method and device, electronic equipment and a storage medium, and relates to the technical field of computers. A specific implementation manner of the method comprises the following steps: in response to a data processing request, obtaining a corresponding to-be-processed array, and generating a matrix corresponding to each to-be-processed array; wherein each to-be-processed array comprises at least two data, each data in the to-be-processed array is in one-to-one correspondence with a row vector in the corresponding matrix, and the arrangement order of the row vectors in the matrix is the arrangement order of the corresponding data in the to-be-processed array; calculating the transpose matrix of each matrix, performing a preset Boolean operation on the row vectors at the same positions in the transpose matrices in sequence, and obtaining an operation result matrix; transposing the operation result matrix, obtaining a data processing result, and sending the data processing result. The implementation manner can solve the problem that when the amount of data that needs to be operated is large, the operation mode of a single bit will take a long operation time and the efficiency is low.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a data processing method, apparatus, electronic device, and storage medium. Background Technology

[0002] Boolean operations are computations applicable in many scenarios. For example, in information retrieval, Boolean operations can be used to connect search keywords to perform corresponding information searches. In current computer systems, Boolean operations on data are typically performed single-bit operations, that is, operations are performed on each bit of the data sequentially from the least significant bit to the most significant bit to obtain the final result. However, when dealing with large amounts of data, the computation logic needs to be executed iteratively, so single-bit operations take a long time and are inefficient. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a data processing method, apparatus, electronic device, and storage medium that can solve the problem that single-bit operations take a long time and are inefficient when the amount of data to be processed is large.

[0004] To achieve the above objectives, according to one aspect of the present invention, a data processing method is provided.

[0005] An embodiment of the present invention provides a data processing method comprising: responding to a data processing request, obtaining a corresponding array to be processed, and generating a matrix corresponding to each array to be processed; wherein each array to be processed includes at least two data items, each data item in the array to be processed corresponds one-to-one with a row vector in the corresponding matrix, and the order of the row vectors in the matrix is ​​the same as the order of the corresponding data items in the array to be processed; calculating the transpose of each matrix, sequentially performing a preset Boolean operation on the row vectors at the same position in each transpose matrix to obtain a result matrix; transposing the result matrix to obtain a data processing result and sending it.

[0006] In one embodiment, performing a preset Boolean operation on the row vectors at the same position in each transpose matrix to obtain the result matrix includes:

[0007] For each transpose matrix, based on the order of the row vectors in the transpose matrix, the row vectors in the transpose matrix are stored sequentially into the first register corresponding to the transpose matrix;

[0008] The number of column vectors included in the transpose matrix is ​​determined to be the number of bits of the output data each time the first register is triggered, so as to perform the Boolean operation on the data in each of the first registers and obtain the operation result matrix.

[0009] In yet another embodiment, performing the Boolean operation on the data in each of the first registers includes:

[0010] After monitoring that each of the first registers is triggered, the data in the same position in the output data of each of the first registers are identified as a group of Boolean operation inputs to perform the Boolean operation.

[0011] In yet another embodiment, the Boolean operation includes a first operation and a second operation;

[0012] Performing the Boolean operation on the data in each of the first registers includes:

[0013] After monitoring that each of the first registers is triggered, the data in the same position in the output data of each of the first registers are identified as a group of Boolean operation inputs to perform the first Boolean operation, and then the operation result is stored in the corresponding second register;

[0014] Once the second register is detected to be triggered, the data output by the second register is used to perform the second operation.

[0015] In yet another embodiment, generating the matrix corresponding to each of the arrays to be processed includes:

[0016] For each array to be processed, the data in the array to be processed is converted into row vectors of a preset format, and the row vectors are combined according to the order in which the data is arranged in the array to be processed to obtain the corresponding matrix.

[0017] In another embodiment, a preset Boolean operation is performed sequentially on the row vectors at the same position in each of the transpose matrices, including:

[0018] Obtain the operation identifier in the data processing request to query the Boolean operation model corresponding to the operation identifier;

[0019] The Boolean operation model is invoked, and the row vectors at the same position in each transpose matrix are sequentially input into the Boolean operation model to perform the operation.

[0020] To achieve the above objectives, according to another aspect of the present invention, a data processing apparatus is provided.

[0021] An embodiment of the present invention provides a data processing apparatus comprising: a generation unit, configured to, in response to a data processing request, acquire a corresponding array to be processed and generate a matrix corresponding to each array to be processed; wherein each array to be processed includes at least two data items, each data item in the array to be processed corresponds one-to-one with a row vector in the corresponding matrix, and the order of the row vectors in the matrix is ​​the same as the order of the corresponding data items in the array to be processed; a calculation unit, configured to calculate the transpose matrix of each matrix, and sequentially perform a preset Boolean operation on the row vectors at the same position in each transpose matrix to obtain a result matrix; and a sending unit, configured to transpose the result matrix to obtain a data processing result and send it.

[0022] In one embodiment, the computing unit is specifically used for:

[0023] For each transpose matrix, based on the order of the row vectors in the transpose matrix, the row vectors in the transpose matrix are stored sequentially into the first register corresponding to the transpose matrix;

[0024] The number of column vectors included in the transpose matrix is ​​determined to be the number of bits of the output data each time the first register is triggered, so as to perform the Boolean operation on the data in each of the first registers and obtain the operation result matrix.

[0025] In yet another embodiment, the computing unit is specifically used for:

[0026] After monitoring that each of the first registers is triggered, the data in the same position in the output data of each of the first registers are identified as a group of Boolean operation inputs to perform the Boolean operation.

[0027] In yet another embodiment, the Boolean operation includes a first operation and a second operation;

[0028] The computing unit is specifically used for:

[0029] After monitoring that each of the first registers is triggered, the data in the same position in the output data of each of the first registers are identified as a group of Boolean operation inputs to perform the Boolean operation, and then the operation result is stored in the corresponding second register;

[0030] Once the second register is detected to be triggered, the data output by the second register is used to perform the second operation.

[0031] In yet another embodiment, the generating unit is specifically used for:

[0032] For each array to be processed, the data in the array to be processed is converted into row vectors of a preset format, and the row vectors are combined according to the order in which the data is arranged in the array to be processed to obtain the corresponding matrix.

[0033] In yet another embodiment, the computing unit is specifically used for:

[0034] Obtain the operation identifier in the data processing request to query the Boolean operation model corresponding to the operation identifier;

[0035] The Boolean operation model is invoked, and the row vectors at the same position in each transpose matrix are sequentially input into the Boolean operation model to perform the operation.

[0036] To achieve the above objectives, according to another aspect of the present invention, an electronic device is provided.

[0037] An electronic device according to an embodiment of the present invention includes: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the data processing method provided in the embodiment of the present invention.

[0038] To achieve the above objectives, according to another aspect of the present invention, a computer-readable medium is provided.

[0039] An embodiment of the present invention provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the data processing method provided in the embodiment of the present invention.

[0040] One embodiment of the above invention has the following advantages or beneficial effects: In this embodiment, in response to a data processing request, a corresponding array to be processed is obtained, i.e., an array that needs to perform the same Boolean operation. Each array to be processed includes at least two data items, i.e., multiple data items need to perform Boolean operations. Then, a matrix corresponding to each array to be processed can be generated. Each data item in the array to be processed corresponds one-to-one with the row vectors in the corresponding matrix, and the order of the row vectors in the matrix is ​​the same as the order of the corresponding data in the array to be processed. That is, the order of the row vectors in the matrix is ​​the same as the order of the corresponding data in the array to be processed, thereby ensuring that the data to be processed are in their respective matrices. The positions are consistent; then the transpose matrix of each matrix is ​​calculated, that is, the row vectors corresponding to each data are converted into column vectors. At this time, each row vector in the transpose matrix is ​​an element of the same bit position in the data included in the matrix. The operation logic is the same, so Boolean operation can be directly performed on the row vectors of the same position in each transpose matrix. That is, the corresponding elements of the row vectors of the same position in each transpose matrix can simultaneously perform the preset Boolean operation. That is, Boolean operation is performed on the data in each data group in parallel to obtain the operation result matrix. Finally, the operation result matrix is ​​transposed again to obtain the result of Boolean operation on the row vectors of the same position in each matrix to be processed. Thus, in this embodiment of the invention, when there is a lot of data to be processed, Boolean operation can be performed on each data in parallel, thereby improving the efficiency of data processing and saving data processing time.

[0041] The further effects of the aforementioned unconventional alternative methods will be explained below in conjunction with specific implementation methods. Attached Figure Description

[0042] The accompanying drawings are provided to better understand the invention and are not intended to unduly limit the scope of the invention. Wherein:

[0043] Figure 1 This is a schematic diagram of a Boolean circuit according to an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of a main flow of a data processing method according to an embodiment of the present invention;

[0045] Figure 3 This is a schematic diagram of the main flow of a Boolean operation method according to an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram of the main units of a data processing apparatus according to an embodiment of the present invention;

[0047] Figure 5 This is an exemplary system architecture diagram in which embodiments of the present invention can be applied;

[0048] Figure 6 This is a schematic diagram of the structure of a computer system suitable for implementing embodiments of the present invention. Detailed Implementation

[0049] The following description, in conjunction with the accompanying drawings, illustrates exemplary embodiments of the present invention, including various details to aid understanding. These details should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0050] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0051] This invention provides a data processing system that can be used in scenarios where multiple data points perform the same Boolean operation. Boolean operations can include various operations, and these operations can be combined based on requirements. This invention uses the calculation of "==" as an example. Data x and data y are set as the data to be processed, i.e., the two data points that need to perform the "==" operation. Taking x and y as a vector containing four elements, i.e., x = (x3, x2, x1, x0) and y = (y3, y2, y1, y0), where the elements in x are x3, x2, x1, x0 from least significant bit to most significant bit, and the elements in y are y3, y2, y1, y0 from least significant bit to most significant bit, with each element being 1 bit. The operation logic of x == y consists of a combination of multiple Boolean operations, and the specific operation circuit can be as follows... Figure 1 As shown. When a computing device performs the operation x == y, it first stores the vectors of x and y in their respective shift registers in ascending order of their least significant bits. Each time the two shift registers are triggered, they output 1 bit of data. Then, a Boolean operation is performed on each 1 bit output from the two shift registers, and the result is stored in a preset shift register as the input data for the overall operation. Since x and y contain four elements, four XOR operations are performed sequentially. Then, a OR operation is performed on the XOR result, and finally, the NOT operation is performed to obtain the result Equal, which is the result of the x == y operation. If the Equal result is 1, it means x and y are equal; if the Equal result is 0, it means x and y are not equal. Because the "==" operation requires the above process, it takes a long time to process when dealing with a large amount of data, resulting in low efficiency. For example, two data sets X containing 1024 data points... 1024 and Y 1024 , that is, X 1024 It contains 1024 x, Y 1024It contains 1024 y's, and X needs to be executed. 1024 ==Y 1024 The operation, that is, the operation on X 1024 and Y 1024 The "==" operation is performed on data in the same position, meaning the "==" operation needs to be performed 1024 times. The result is a bit vector of length 1024 named Equal. 1024 Among them, Equal 1024 The i-th (0≤i≤1023) bit in the Equal 1024 [i] = 1, indicating that X 1024 The i-th data X 1024 [i] and Y 1024 The i-th data Y 1024 [i] Equal; Equal 1024 The i-th bit in Equal 1024 [i] = 0, indicating that X 1024 The i-th data X 1024 [i] and Y 1024 The i-th data Y 1024 If [i] are not equal, it will take a long time to perform the calculation, which is inefficient.

[0052] This invention provides a data processing method that can be executed by a computing device, such as... Figure 2 As shown, the method includes:

[0053] S201: In response to a data processing request, obtain the corresponding array to be processed and generate a matrix corresponding to each array to be processed.

[0054] Each array to be processed includes at least two data points. Each data point in the array to be processed corresponds one-to-one with a row vector in the corresponding matrix, and the order of the row vectors in the matrix is ​​the same as the order of the corresponding data in the array to be processed.

[0055] After receiving a data processing request, the system can obtain the corresponding arrays to be processed, which are the arrays that need to undergo Boolean operations. The number of arrays to be processed is determined by the number of inputs for the specific Boolean operation. For example, if the "NOT" operation requires one input, there is one array to be processed; if the "XOR" operation requires two inputs, there are two arrays to be processed. The arrays to be processed contain the data for which Boolean operations will be performed. When there is more than one array, Boolean operations are typically performed between data in the same position within each array. For example, if there are two arrays, an XOR operation is performed between data in the same position within the two arrays. For instance, if array A is (a1, a2) and array B is (b1, b2), then a1 and b1 will be processed together, and a2 and b2 will be processed together.

[0056] In this embodiment of the invention, the data processing request may include identifiers for each array to be processed, so that the array to be processed can be obtained in this step based on the identifiers of each array to be processed. The data in each array to be processed can also be stored in a vector format, so the vector to be processed can also be obtained in this step.

[0057] For each array to be processed, a matrix can be generated. Specifically, this can be done as follows: for each array to be processed, the data in the array is converted into row vectors of a preset format, and the row vectors are combined according to the order of the data in the array to obtain the corresponding matrix.

[0058] Computing devices typically process binary data, so the default format is binary. Each data element in the array to be processed can be converted to binary data, which can be represented as a row vector. The combination of these row vectors in an array yields the corresponding matrix, thus creating a one-to-one correspondence between the data in the array and the row vectors in the matrix. Since Boolean operations are required between data at the same positions in the arrays, to ensure accuracy, the row vectors in the corresponding matrices must be arranged in the same order as the data in the arrays. In other words, the order of the row vectors in the matrix corresponds to the order of the data in the array.

[0059] For example, arrays X and Y are the arrays to be processed, containing data X = {x0, x1, x2, x3} and Y = {y0, y1, y2, y3}, respectively. Taking each data point as having 4 bits in binary as an example, the row vector after converting x0 to binary is (x03, x02, x01, x00), and the row vector after converting y0 to binary is (y03, y02, y01, y00), and so on. This allows us to derive the row vectors corresponding to each data point, thereby generating matrices X4 and Y4 as shown in Formula 1 below.

[0060]

[0061] In this embodiment of the invention, the data processing request may further include an operation identifier to indicate the Boolean operation to be performed on the data to be processed, and then the Boolean operation model corresponding to the operation identifier can be queried; subsequently, the Boolean operation model can be called to perform the corresponding Boolean operation.

[0062] S202: Calculate the transpose of each matrix, and perform a preset Boolean operation on the row vectors at the same position in each transpose matrix in turn to obtain the result matrix.

[0063] In step S101, after obtaining the matrix corresponding to each data point, the transpose matrix of each matrix can be calculated first. For example, after transposing X4 and Y4, the transpose matrices TX and TY can be obtained as shown in Formula 2.

[0064]

[0065] Based on Formulas 1 and 2, the k-th row of TX (0≤k≤3) contains the k-th bit from the left in the row vector of X4. For example, the 0th row of TX contains the 0th bit (the most significant bit) from the left of x0, x1, x2, and x3, and the 3rd row of TX contains the 3rd bit (the least significant bit) from the left of x0, x1, x2, and x3. Thus, the elements in each row vector of TX and TY belong to different data in the corresponding array to be processed. They have the same computational logic and are not related, so they can be executed in parallel. That is, operations can be performed on each element in the row vector simultaneously. Furthermore, since Boolean operations are all equal-width operations (the input and output of AND, OR, NOT, XOR, etc., are all bit-based), performing a Boolean operation between the 0th row vector of TX and the 0th row vector of TY is equivalent to performing Boolean operations on x03 and y03, x13 and y13, x23 and y23, and x33 and y33 respectively, and obtaining their respective results. Therefore, it is equivalent to simultaneously performing operations between the leftmost bits of the four elements in X and the leftmost bits of the four elements in Y. From the perspective of CPU execution time overhead, since CPU operations are typically based on 64-bit or 32-bit (the maximum number of bits a processor can process at a time) registers, the time overhead of simultaneously performing operations on four elements is the same as performing operations on one element—one CPU instruction cycle. Therefore, the Boolean operation method for multiple data in this embodiment of the invention can save computation time.

[0066] In this step, a preset Boolean operation is performed sequentially on the row vectors at the same position in each transpose matrix. This yields the result of the operation on each row vector. The results of the operation on each row vector are then sorted based on their corresponding row vectors to obtain the final matrix. Specifically, computing devices typically perform Boolean operations through registers, meaning that preset registers store the input data and output results. Therefore, this step can be specifically executed as follows: For each transpose matrix, based on the order of the row vectors in the transpose matrix, the row vectors are sequentially stored in the first register corresponding to the transpose matrix; the number of column vectors included in the transpose matrix is ​​determined as the number of bits in the output data of each time the first register is triggered, and Boolean operations are performed on the data in each of the first registers to obtain the final matrix.

[0067] In this step, a corresponding first register can be set for each transpose matrix to store the input data of the operation, namely TX and TY. The data in the register is output in order. Therefore, based on the arrangement order of the row vectors in the transpose matrix, the row vectors in each transpose matrix are stored in the corresponding first register in sequence, so that the first register can output in sequence based on the arrangement order of the row vectors in the transpose matrix.

[0068] In this embodiment of the invention, the principle is to perform Boolean operations in parallel on the elements of the row vectors of the transposed matrix. Thus, when the first register outputs data, it needs to output the elements of one row vector at a time. Since the row vectors in the transposed matrix are stored in the first register in the order they are arranged, it is only necessary to control the number of bits of data output by the first register each time to be equal to the number of column vectors included in the transposed matrix. This ensures that the first register outputs the elements of one row vector each time. Therefore, in this step, the number of column vectors included in the transposed matrix is ​​determined as the number of bits of data output by the first register each time it is triggered.

[0069] It should be noted that since Boolean operations are usually performed on data from the least significant bit to the most significant bit, in this step, the row vectors in the transpose matrix can be stored in the corresponding first registers in order of the elements in the row vector from the least significant bit to the most significant bit.

[0070] Specifically, performing Boolean operations on the data in each first register can be done as follows: after monitoring that each first register is triggered, the data in the same position in the output data of each first register is determined as a group of Boolean operation inputs to perform Boolean operations.

[0071] The first register outputs data by triggering, so by monitoring the triggering of each first register, it can be determined that each first register has output data. Then, Boolean operations can be performed on the output data. That is, data in the same position in the output data of each first register are determined as a group of Boolean operation inputs, and then Boolean operations are performed on each group of Boolean operation inputs.

[0072] Since some operations involve combinations of multiple Boolean operations, this embodiment of the invention only improves the initial input of the overall operation. After performing the first Boolean operation on the initial input, subsequent operations can be performed according to the original operation method. Specifically, the entire operation process is divided into a first operation and a second operation, where the first operation is the first Boolean operation in the overall operation process, and the second operation is the other operations after the first Boolean operation in the overall operation process. At this time, the Boolean operation is performed on the data in each of the first registers, including: after monitoring that each of the first registers is triggered, determining the data in the same position in the data output by each of the first registers as a group of Boolean operation inputs to perform the first Boolean operation, and then storing the operation result in the corresponding second register; after monitoring that each of the second registers is triggered, performing the second operation on the data output by each of the second registers. The data output by the first register can be stored in a preset second register after performing the first operation, and then the second register can be triggered to output data to perform the second operation.

[0073] S203: Transpose the result matrix to obtain the data processing result and send it.

[0074] In step S202, the result matrix is ​​the result of the operation corresponding to the transpose matrix. Therefore, in this step, the result matrix needs to be transposed to obtain the data processing result and then send the data processing result.

[0075] It should be noted that different processors in computing devices have different maximum numbers of bits of data that can be processed at one time. In this embodiment of the invention, the number of bits that can be used to perform Boolean operations in parallel cannot exceed the maximum number of bits of data that the processor in the computing device can process at one time. Therefore, in this step, if the amount of data to be processed is too large, it is necessary to split it first. Specifically, before step S202, the following steps can be performed: determine whether the number of row vectors in the matrix is ​​greater than the maximum number of bits of data that the processor can process at one time. If not, then step S202 is executed; if so, the matrices corresponding to each data are split in the same way so that the number of row vectors in the split matrix is ​​not greater than the maximum number of bits of data that the processor can process at one time.

[0076] In this embodiment of the invention, when there is a large amount of data to be processed, Boolean operations can be performed on each data in parallel, thereby improving the efficiency of data processing and saving data processing time.

[0077] In this embodiment of the invention, taking the arrays to be processed as X4 = [1001, 1100, 0101, 1110] and Y4 = [1001, 1100, 1011, 1110], and the Boolean operation X4 == Y4 as an example, the Boolean operation method in step S202 is explained. Since "==" is implemented by a combination of multiple Boolean operations, the first Boolean operation "XOR" is determined as the first operation, and the other operations after "XOR" are determined as the second operations, such as... Figure 4 As shown, the method includes:

[0078] S301: Transpose the matrix corresponding to the array to be processed to obtain the transposed matrix.

[0079] The matrices corresponding to X4 and Y4 are shown in Equation 3, and the transposed matrix is ​​shown in Equation 4.

[0080]

[0081]

[0082] S302: Perform the first Boolean operation sequentially on the row matrices at the same positions of the transpose matrix to obtain the first operation result.

[0083] Typically, in a matrix's row vector, the leftmost element corresponds to the least significant bit, and the rightmost element corresponds to the most significant bit. Therefore, after transposing, the 0th row of the transposed matrix contains the least significant bit, and the 3rd row contains the most significant bit. In this step, TX and TY can be stored sequentially in the first register from top to bottom, and the first register can be set to output 4 bits per trigger, so that it outputs one row vector each time it is triggered. After the first register is triggered, the first operation (XOR operation) is performed on the output data, and the result of each operation can be stored in the corresponding second register for subsequent operations. The specific code can be found here:

[0084] temp0=TX[0]^TY[0]=1101^1111=0010

[0085] temp1=TX[1]^TY[1]=0111^0101=0010

[0086] temp2=TX[2]^TY[2]=0001^0011=0010

[0087] temp3=TX[3]^TY[3]=1010^1010=0000

[0088] Where temp0 represents the result of XORing TX[0] in the 0th row of TX with TY[0] in the 0th row of TY; temp1 represents the result of XORing TX[1] in the 1st row of TX with TY[1] in the 1st row of TY; temp2 represents the result of XORing TX[2] in the 2nd row of TX with TY[2] in the 2nd row of TY; and temp3 represents the result of XORing TX[3] in the 3rd row of TX with TY[3] in the 3rd row of TY. temp0, temp1, temp2, and temp3 are the results of the first operation and can be stored in their respective second registers.

[0089] S303: Perform the second operation on the result of the first operation to obtain the result matrix.

[0090] After obtaining the XOR result, you need to perform an OR operation on temp0, temp1, temp2, and temp3 first, and then perform the NOT operation. The specific code is as follows:

[0091] tt0=temp0|temp1=0010|0010=0010

[0092] tt1=temp2|temp3=0010|0000=0010

[0093] ttt=tt0|tt1=0010|0010=0010

[0094] tequal = ~ttt = 1101

[0095] In the code above, first, OR operations are performed on each pair of temp0, temp1, temp2, and temp3. tt0 represents the result of the OR operation between temp0 and temp1, and tt1 represents the result of the OR operation between temp2 and temp3. Then, OR operations are performed on the results of the pairwise operations to obtain the result ttt of the OR operation between temp0, temp1, temp2, and temp3. Finally, the NOT operation is performed to obtain the result matrix tequal. The result matrix in this operation is a row vector.

[0096] It should be noted that after obtaining the result matrix in this step, transposing it will give the result that X4 == Y4.

[0097] In this embodiment of the invention, for a given set of four data points X4 and Y4, the prior art requires the execution time of 4×4 XOR operations to perform an XOR operation, while this embodiment of the invention only requires the execution time of 4 XOR operations, thus improving computational efficiency and significantly enhancing the overall computational performance of the computing device.

[0098] To address the problems existing in the prior art, embodiments of the present invention provide a data processing apparatus 400, such as... Figure 4 As shown, the device 400 includes:

[0099] The generation unit 401 is used to respond to a data processing request, obtain the corresponding array to be processed, and generate a matrix corresponding to each array to be processed; wherein each array to be processed includes at least two data, each data in the array to be processed corresponds one-to-one with the row vector in the corresponding matrix, and the order of the row vectors in the matrix is ​​the order of the corresponding data in the array to be processed;

[0100] The calculation unit 402 is used to calculate the transpose matrix of each matrix, and sequentially perform a preset Boolean operation on the row vectors at the same position in each transpose matrix to obtain the result matrix.

[0101] The sending unit 403 is used to transpose the operation result matrix to obtain the data processing result and send it.

[0102] It should be understood that the manner in which embodiments of the present invention are implemented is different from the implementation method. Figure 2 The embodiments shown are the same and will not be described again here.

[0103] In one implementation of this invention, the computing unit 402 is specifically used for:

[0104] For each transpose matrix, based on the order of the row vectors in the transpose matrix, the row vectors in the transpose matrix are stored sequentially into the first register corresponding to the transpose matrix;

[0105] The number of column vectors included in the transpose matrix is ​​determined to be the number of bits of the output data each time the first register is triggered, so as to perform the Boolean operation on the data in each of the first registers and obtain the operation result matrix.

[0106] In another implementation of this invention, the computing unit 402 is specifically used for:

[0107] After monitoring that each of the first registers is triggered, the data in the same position in the output data of each of the first registers are identified as a group of Boolean operation inputs to perform the Boolean operation.

[0108] In another implementation of this invention, the Boolean operation includes a first operation and a second operation;

[0109] The computing unit 402 is specifically used for:

[0110] After monitoring that each of the first registers is triggered, the data in the same position in the output data of each of the first registers are identified as a group of Boolean operation inputs to perform the Boolean operation, and then the operation result is stored in the corresponding second register;

[0111] Once the second register is detected to be triggered, the data output by the second register is used to perform the second operation.

[0112] In another implementation of this invention, the generation unit 401 is specifically used for:

[0113] For each array to be processed, the data in the array to be processed is converted into row vectors of a preset format, and the row vectors are combined according to the order in which the data is arranged in the array to be processed to obtain the corresponding matrix.

[0114] In another implementation of this invention, the computing unit 402 is specifically used for:

[0115] Obtain the operation identifier in the data processing request to query the Boolean operation model corresponding to the operation identifier;

[0116] The Boolean operation model is invoked, and the row vectors at the same position in each transpose matrix are sequentially input into the Boolean operation model to perform the operation.

[0117] It should be understood that the manner in which embodiments of the present invention are implemented is different from the implementation method. Figure 2 or Figure 3 The embodiments shown are the same and will not be described again here.

[0118] In this embodiment of the invention, in response to a data processing request, a corresponding array to be processed is obtained, i.e., an array that needs to perform the same Boolean operation. Each array to be processed includes at least two data items, meaning multiple data items need to undergo Boolean operations. Then, a matrix corresponding to each array to be processed can be generated. Each data item in the array to be processed corresponds one-to-one with a row vector in the corresponding matrix, and the order of the row vectors in the matrix is ​​the same as the order of the corresponding data items in the array to be processed. That is, the order of the row vectors in the matrix is ​​the same as the order of the corresponding data items in the array to be processed, thereby ensuring that the data items to be processed are in the same position in their respective matrices. Then, each... The transpose of a matrix is ​​obtained by converting the row vectors corresponding to each data point into column vectors. Each row vector in the transpose matrix represents an element with the same bit position in the data contained within that matrix. Since their operational logic is the same, Boolean operations can be directly performed on the row vectors at the same position in each transpose matrix. This means that corresponding elements in the row vectors at the same position in each transpose matrix can simultaneously undergo a preset Boolean operation. In other words, Boolean operations are performed on the data in each data group in parallel to obtain the result matrix. Finally, the result matrix is ​​transposed to obtain the result of Boolean operations on the row vectors at the same position in each matrix to be processed. Thus, in this embodiment of the invention, when there is a large amount of data to be processed, Boolean operations can be performed on each data point in parallel, thereby improving data processing efficiency and saving data processing time.

[0119] According to embodiments of the present invention, an electronic device and a readable storage medium are also provided.

[0120] An electronic device according to an embodiment of the present invention includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the data processing method provided in the embodiment of the present invention.

[0121] Figure 5 An exemplary system architecture 500 is shown, in which a data processing method or data processing apparatus to which embodiments of the present invention can be applied is illustrated.

[0122] like Figure 5 As shown, system architecture 500 may include terminal devices 501, 502, and 503, a network 504, and a server 505. Network 504 serves as the medium for providing communication links between terminal devices 501, 502, and 503 and server 505. Network 504 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0123] Users can use terminal devices 501, 502, and 503 to interact with server 505 via network 504 to receive or send messages, etc. Various client applications can be installed on terminal devices 501, 502, and 503.

[0124] Terminal devices 501, 502, and 503 can be, but are not limited to, smartphones, tablets, laptops, and desktop computers, etc.

[0125] Server 505 can be a server that provides various services. The server can analyze and process the received data processing requests and other data, and feed back the processing results (e.g., data processing results - just an example) to the terminal device.

[0126] It should be noted that the data processing method provided in the embodiments of the present invention is generally executed by server 505, and correspondingly, the data processing device is generally located in server 505.

[0127] It should be understood that Figure 5 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0128] The following is for reference. Figure 6 It shows a schematic diagram of the structure of a computer system 600 suitable for implementing embodiments of the present invention. Figure 6 The computer system shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0129] like Figure 6 As shown, the computer system 600 includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 602 or programs loaded from storage section 608 into random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the system 600. The CPU 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0130] The following components are connected to I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 610 as needed so that computer programs read from it can be installed into storage section 608 as needed.

[0131] In particular, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 609, and / or installed from removable medium 611. When the computer program is executed by central processing unit (CPU) 601, it performs the functions defined above in the system of this invention.

[0132] It should be noted that the computer-readable medium shown in this invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this invention, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0133] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a unit, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0134] The units described in the embodiments of the present invention can be implemented in software or hardware. The described units can also be housed in a processor; for example, a processor can be described as including a generation unit, a calculation unit, and a transmission unit. The names of these units do not necessarily limit the specific unit; for example, a generation unit can also be described as "a unit that performs the functions of a generation unit."

[0135] In another aspect, the present invention also provides a computer-readable medium, which may be included in the device described in the above embodiments; or it may exist independently and not assembled into the device. The computer-readable medium carries one or more programs that, when executed by the device, cause the device to perform the data processing method provided by the present invention.

[0136] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can occur depending on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method of data processing, characterized by, The method comprises the following steps: In response to a data processing request, a corresponding to-be-processed array is obtained, and a matrix corresponding to each to-be-processed array is generated; each to-be-processed array comprises at least two data, each data in the to-be-processed array corresponds to a row vector in the corresponding matrix in a one-to-one manner, and the arrangement order of the row vectors in the matrix is the arrangement order of the corresponding data in the to-be-processed array; The transpose matrix of each matrix is calculated, a preset Boolean operation is performed on the row vectors at the same position in each transpose matrix in sequence, and a calculation result matrix is obtained; The calculation result matrix is transposed to obtain a data processing result and send the data processing result; The preset Boolean operation is performed on the row vectors at the same position in each transpose matrix in sequence, and the calculation result matrix is obtained, which comprises the following steps: For each transpose matrix, the row vectors in the transpose matrix are stored in a first register corresponding to the transpose matrix in sequence based on the arrangement order of the row vectors in the transpose matrix; The number of column vectors included in the transpose matrix is determined as the number of bits of the output data of the first register each time the first register is triggered, so as to perform the Boolean operation on the data in each first register and obtain the calculation result matrix; The matrix corresponding to each to-be-processed array is generated, which comprises the following steps: For each to-be-processed array, the data in the to-be-processed array is converted into a row vector in a preset format, and the row vectors are combined in the arrangement order of the data in the to-be-processed array to obtain the corresponding matrix.

2. The method of claim 1, wherein, The Boolean operation is performed on the data in each first register, which comprises the following steps: After monitoring that each first register is triggered, the data at the same position in the data output by each first register is determined as a group of Boolean operation inputs to perform the Boolean operation.

3. The method of claim 1, wherein, The Boolean operation comprises a first operation and a second operation; The Boolean operation is performed on the data in each first register, which comprises the following steps: After monitoring that each first register is triggered, the data at the same position in the data output by each first register is determined as a group of Boolean operation inputs to perform the first operation, and the calculation result is stored in a corresponding second register; After monitoring that the second register is triggered, the data output by the second register is subjected to the second operation.

4. The method of claim 1, wherein, The preset Boolean operation is performed on the row vectors at the same position in each transpose matrix in sequence, which comprises the following steps: An operation identifier in the data processing request is obtained to query a Boolean operation model corresponding to the operation identifier; The Boolean operation model is called, and the row vectors at the same position in each transpose matrix are input into the Boolean operation model in sequence to perform the operation.

5. An apparatus for data processing, characterized by The method comprises the following steps: A generating unit is configured to obtain a corresponding to-be-processed array in response to a data processing request, and generate a matrix corresponding to each to-be-processed array; each to-be-processed array comprises at least two data, each data in the to-be-processed array corresponds to a row vector in the corresponding matrix in a one-to-one manner, and the arrangement order of the row vectors in the matrix is the arrangement order of the corresponding data in the to-be-processed array; A calculation unit is configured to calculate a transposed matrix of each of the matrices, and perform a preset Boolean operation on row vectors at the same positions in the transposed matrices in sequence to obtain a result matrix; A sending unit is configured to transpose the result matrix to obtain a data processing result and send the data processing result; The calculation unit is specifically configured to: For each transposed matrix, store row vectors in the transposed matrix into a first register corresponding to the transposed matrix in sequence based on an arrangement order of the row vectors in the transposed matrix; Determine a number of column vectors included in the transposed matrix as a bit number of output data of the first register each time triggered, so as to perform the Boolean operation on data in each of the first registers to obtain a result matrix; The generation unit is specifically configured to: For each of the to-be-processed arrays, convert data in the to-be-processed array into row vectors in a preset format, and combine the row vectors in an arrangement order of the data in the to-be-processed array to obtain a corresponding matrix.

6. An electronic device, comprising: comprise: one or more processors; a memory device for storing one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors implement the method in any one of claims 1-4.

7. A computer readable medium having stored thereon a computer program, characterized in that The program is executed by the processor to implement the method in any one of claims 1-4.

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