Information processing method, device and system based on simulation waveforms in chip simulation

Abstract

The application discloses a kind of information processing method, device and application based on simulation waveform in chip simulation, it is related to chip development technical field.The method includes the following steps: obtaining the IP level simulation waveform file of the IP module to be measured;According to the simulation timing of IP level test case, the bus transmission signal is parsed, the change information of bus transmission state with time is obtained, whether the code conversion operation is triggered according to the change of the bus transmission state;When triggering code conversion operation, the corresponding bus configuration information is obtained according to the current bus transmission state, and the corresponding SoC level test case code is formed, and the SoC level test case code is used for the SoC interface bus configuration of the IP module to be measured.The application realizes the automatic conversion of interface bus configuration of test case in different verification environment, can improve the efficiency of transplanting test case in IP level verification environment, so as to shorten the chip development cycle.

Description

Technical Field

[0001] This invention relates to the field of chip development technology, and in particular to a method, apparatus and system for information processing based on simulation waveforms in chip simulation. Background Technology

[0002] A typical large-scale system-on-chip (SoC) generally includes circuitry designed by the chip designer and purchased IP modules. IP modules, also known as IP cores, are mature designs of independent functional circuit modules within the chip, such as DSP (Digital Signal Processor) modules, DRAM (Dynamic Random Access Memory) modules, and USB modules. Interconnection between IP modules is achieved through an on-chip bus. Using IP modules can shorten the design cycle and improve the success rate of chip design. Correspondingly, the functional verification design of SoC chips is usually divided into two parts: IP (Intellectual Property) level verification (also known as module-level verification) and SoC level verification (also known as chip-level verification). Simulation verification also requires setting up separate IP-level and SoC-level verification environments. The IP-level verification environment is mainly used to simulate and verify the functionality of individual IP modules, while the SoC-level verification environment is mainly used to verify whether the IP modules can function properly within the entire chip system and meet expected results. In actual chip simulation verification processes, some purchased IP modules often also require verification at both levels.

[0003] Common IP-level verification typically uses a UVM (Universal Verification Methodology) bus to stimulate the register interface of the control IP. A test bench can include the IP under test (DUT), a VIP (verification IP) tool, and a bus stimulus sequence of the bus functional model. The bus functional model operates at the clock frequency generated by the test bench to drive the interaction between the DUT and the VIP. The functionality of the DUT is then checked through the VIP. Currently, IP core vendors usually provide IP-level verification environments for their IP cores, enabling verification personnel to perform IP-level verification of IP core designs.

[0004] However, because the code in the verification environments provided by some vendors is often encrypted, verification personnel can only run the verification simulation environment but cannot modify the code information or directly port test cases. If verification personnel need to port simulation test cases (a series of codes written to verify the functionality or performance of a test item) from the IP-level verification environment to the SoC-level verification environment, the current industry practice is as follows: based on the test case information visible in the IP-level verification simulation environment, verification personnel decompose the detailed information of the test cases provided in the IP-level verification simulation environment, and then re-describe this detailed information using System Verilog to form test cases that can run in the SoC-level verification environment. The rewritten test cases are then added to the test case set of the test system. In the information analysis and recompilation of simulation test cases, analyzing and rewriting bus information (converting the bus information of IP-level test cases to the bus information of SoC-level test cases) is one of the important tasks. Manual analysis and rewriting are time-consuming, resulting in low test case porting efficiency and affecting the entire chip development cycle. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a method, apparatus, and application for information processing based on simulation waveforms in chip simulation. This invention analyzes simulation waveform files obtained from IP-level verification, automatically identifies and converts the corresponding bus configuration information to form test case code for SoC-level verification environments. This achieves automatic conversion of interface bus configurations for test cases in different verification environments, thereby improving the processing efficiency of porting test cases from IP-level verification environments to SoC-level verification environments, and thus shortening the chip development cycle.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A method for information processing based on simulation waveforms in chip simulation includes the following steps:

[0008] The IP-level simulation waveform file obtained after executing the IP-level test case of the IP module under test in the IP-level UVM verification environment contains the simulation timing information and bus transmission signals of the aforementioned IP-level test case.

[0009] The bus transmission signals are analyzed according to the simulation timing of the IP-level test case to obtain the information on the change of bus transmission status over time. Based on the change of the bus transmission status, it is determined whether the code conversion operation is triggered.

[0010] When the code conversion operation is triggered, the corresponding bus configuration information is obtained according to the current bus transmission status. The bus configuration information is described in System Verilog language to form the corresponding SoC-level test case code. The SoC-level test case code is used for the SoC interface bus configuration of the aforementioned IP module under test.

[0011] Furthermore, the IP module under test is a processor IP module, a memory IP module, an input / output (I / O) interface IP module, or other dedicated function IP modules.

[0012] Furthermore, the simulation waveform file also records the name and bus type of the IP module under test.

[0013] Furthermore, the connection bus of the IP module under test is the Advanced Peripheral Bus (APB). In this case, the steps to determine whether the code conversion operation is triggered are as follows:

[0014] The bus clock signal PCLK, bus strobe signal PSEL, and enable control signal PENABLE in the APB bus transmission signals are analyzed to obtain information on the change of bus transmission status over time.

[0015] When the bus transfer state is in read / write transfer state, a code conversion operation is triggered.

[0016] Furthermore, when the bus transmission state is write transmission state, after obtaining the bus address and write data corresponding to this write operation according to the bus address signal PADDR and the bus write data signal PWDATA, the corresponding bus configuration information is described in System Verilog language to form the corresponding SoC-level test case code, and the code is added to the corresponding SoC-level test case of the IP module under test.

[0017] When the bus transfer state is read transfer state, the read data information corresponding to this read operation is obtained according to the bus address signal PADDR and the bus read data signal PRDATA. The corresponding bus configuration information is described in System Verilog language to form the corresponding SoC-level test case code, and the code is added to the corresponding SoC-level test case of the IP module under test.

[0018] Furthermore, it also includes verification steps for interface bus configuration conversion, as follows:

[0019] For the aforementioned IP-level simulation waveform file, the occurrence time and number of bus transmission states that triggered the code conversion operation are recorded, and a first table file is generated based on the occurrence time and number of occurrences; and,

[0020] Based on the SoC-level simulation waveform file obtained after executing the aforementioned SoC-level test case in the SoC-level UVM verification environment, the SoC-level simulation waveform file contains the simulation timing information and bus transmission signals of the aforementioned SoC-level test case. The aforementioned SoC-level simulation waveform file is parsed to obtain the bus transmission state change information over time. Based on the changes in the aforementioned bus transmission state, it is determined whether a code conversion operation is triggered. The occurrence time and number of bus transmission states that trigger the code conversion operation are recorded, and a second table file is generated.

[0021] Compare the first and second table files mentioned above to determine whether the contents recorded in the two are consistent;

[0022] When discrepancies are found, the inconsistencies are identified in the first and second table files and / or an error message is displayed.

[0023] The present invention also provides an information processing device based on simulation waveforms for chip simulation, comprising the following structure:

[0024] The information acquisition module is used to acquire the IP-level simulation waveform file obtained after the IP-level test case of the IP module under test is executed in the IP-level UVM verification environment. The IP-level simulation waveform file contains the simulation timing information and bus transmission signals of the aforementioned IP-level test case.

[0025] The waveform file parsing module parses the aforementioned bus transmission signals according to the simulation timing of the IP-level test case, obtains the information on the change of bus transmission status over time, and determines whether to trigger the code conversion operation based on the change of the aforementioned bus transmission status.

[0026] The code conversion module is used to obtain the corresponding bus configuration information based on the current bus transmission status when the code conversion operation is triggered, and to describe the bus configuration information in System Verilog language to form the corresponding SoC-level test case code. The SoC-level test case code is used for the SoC interface bus configuration of the aforementioned IP module under test.

[0027] The present invention also provides a method for case porting in chip simulation, including the step of converting the IP interface bus configuration of the IP module into the SoC interface bus configuration, wherein the interface bus configuration is automatically converted according to the aforementioned method.

[0028] The present invention also provides a chip testing system, the system including a test case porting device, the test case porting device being used to convert test cases in an IP-level UVM verification environment of an IP module into test cases in a SOC-level UVM verification environment, the test case porting device being configured to automatically convert interface bus configurations using the aforementioned method.

[0029] Furthermore, the IP-level UVM verification environment interacts with the IP module under test through the IP interface module, and performs module-level functional verification of the IP module through IP-level test cases; the SOC-level UVM verification environment interacts with the aforementioned IP module under test in the chip under test through the SOC interface module, and verifies the function of the IP module under test in the chip under test through the converted SOC-level test cases.

[0030] Compared with the prior art, this invention, by adopting the above technical solution, has the following advantages and positive effects: This invention analyzes the simulation waveform files obtained from IP-level verification, automatically identifies the corresponding bus configuration information based on the simulation waveform files, and converts it to form test case code for SoC-level verification environment. This realizes the automatic conversion of interface bus configuration of test cases in different verification environments, thereby improving the processing efficiency of porting test cases from IP-level verification environment to SoC-level verification environment, and thus shortening the chip development cycle. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of bus transmission signals recorded in a simulation waveform file provided for an embodiment of the present invention.

[0032] Figure 2 This is a schematic diagram illustrating the logic of triggering code conversion based on bus transmission status, provided in an embodiment of the present invention.

[0033] Figure 3 A flowchart illustrating the verification process for interface bus configuration conversion provided in this embodiment of the invention.

[0034] Figure 4 This is a schematic diagram illustrating the information output of the first table file provided in an embodiment of the present invention.

[0035] Figure 5 This is a schematic diagram illustrating the information output of the second table file provided in an embodiment of the present invention. Detailed Implementation

[0036] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more comprehensive overview of the information processing method, apparatus, and application based on simulation waveforms in chip simulation disclosed in this invention. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered isolated; they can be combined to achieve better technical effects. In the accompanying drawings of the following embodiments, the same reference numerals in each drawing represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0037] It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes and to aid those skilled in the art in understanding and reading the invention. They are not intended to limit the conditions under which the invention can be implemented. Any modifications to the structure, changes in proportions, or adjustments to size, provided they do not affect the effectiveness or purpose of the invention, should fall within the scope of the technical content disclosed in the invention. The scope of the preferred embodiments of the present invention includes other implementations, wherein functions may be performed not in the order stated or discussed, including substantially simultaneously or in reverse order, depending on the functions involved. This should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0038] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. Example

[0039] In System-on-a-Chip (SoC) design, the interconnection between integrated IP modules is achieved through on-chip buses. A bus is a communication line that transmits information between various functional components of a computer (arithmetic logic unit, controller, memory, input, output, etc.). Commonly used on-chip buses include the AMBA (Advanced Microcontroller Bus Architecture) bus. AMBA promotes modular design, reusability, compatibility, and scalability of IP modules. The AMBA bus specification defines different types of buses that can be used in combination, including: Advanced High-Performance Bus (AHB), Advanced System Bus (ASB), Advanced Peripheral Bus (APB), and Advanced Scalable Interface (AXI) bus.

[0040] In the design and development of AMBA bus-based SoC chips (i.e., SoC chips using the AMBA bus as their on-chip communication bus architecture), the performance of IP modules in the chip under test is typically verified using a UVM verification environment (i.e., SoC-level verification of IP modules). The IP modules are connected to an on-chip bus (such as the APB bus). During simulation verification, the read / write operation parameters of the IP module's bus (or interface bus) data are configured to verify the IP module's functionality. The bus configuration information forms the corresponding test case code. When performing EDA simulation using the test case code, the simulation results are usually saved in the form of simulation waveforms, such as FSDB (Fast Signal Data Base) waveforms.

[0041] Accordingly, the present invention provides an information processing method based on simulation waveforms in chip simulation, the method comprising the following steps:

[0042] S100: Obtain the simulation waveform file obtained after executing the IP-level test case of the IP module under test in the IP-level UVM verification environment. The simulation waveform file is called the IP-level simulation waveform file. The IP-level simulation waveform file contains the simulation timing information and bus transmission signals of the aforementioned IP-level test case.

[0043] S200 analyzes the aforementioned bus transmission signals according to the simulation timing of the IP-level test case to obtain information on the changes in the bus transmission status over time, and determines whether to trigger a code conversion operation based on the changes in the aforementioned bus transmission status.

[0044] S300, when the code conversion operation is triggered, obtains the corresponding bus configuration information according to the current bus transmission status, describes the bus configuration information in System Verilog language to form the corresponding SoC-level test case code, and the SoC-level test case code is used for the SoC interface bus configuration of the aforementioned IP module under test.

[0045] In this embodiment, the IP module under test can specifically be a processor IP module, a memory IP module, an input / output (I / O) interface IP module, or other dedicated function IP modules. As an example, and not a limitation, the processor IP module can be, for example, a DSP module; the memory IP module can be, for example, a DRAM module; the input / output (I / O) interface IP module can be, for example, a USB module, a UART module, etc.; and the other dedicated function IP modules can be, for example, an ADC module, a DAC module, a PLL module, etc.

[0046] The simulation waveform file also records the name of the IP module under test and its bus type. The bus type of the IP module under test can be, for example, Advanced High Performance Bus (AHB), Advanced System Bus (ASB), Advanced Peripheral Bus (APB), or Advanced Scalable Interface (AXI) bus.

[0047] As a preferred typical approach, for example, if the IP module under test is a USB module with an APB bus (the APB bus is mainly used for connecting low-bandwidth peripherals), the USB module is verified and tested using test case A in an IP-level UVM verification environment. The simulation result file is obtained, and the simulation results are stored in waveform format. The APB bus transmission signals recorded are described in [reference needed]. Figure 1 As shown. Figure 1In this context, PCLK represents the bus clock signal, PSEL represents the bus strobe signal, PADDR represents the bus address signal, PENABLE represents the enable signal, and PWDATA represents the bus write data.

[0048] The read and write data buses on the APB bus are separate and initialized to the IDLE state, during which no transfer operations are performed and no module is selected. When a transfer is to be performed, PSEL=1, PENABLE=0, and the bus enters the SETUP state, remaining there for only one cycle. When the next rising edge of PCLK arrives, the bus enters the ENABLE state. Upon entering the ENABLE state, PADDR, PSEL, and PWRITE remain unchanged from the SETUP state, and PENABLE is set to 1. The transfer also only lasts for one cycle in the ENABLE state, completing after the SETUP and ENABLE states. If no transfer is to be performed afterward, the bus enters the IDLE state to wait; if there are continuous transfers, the bus enters the SETUP state.

[0049] Data transmission on the APB bus includes write transfers and read transfers, each with its own write and read transfer states. A write transfer begins with all changes to the address, write data, write signal, and select signal after the rising edge of the clock. The timing sequence of the signals is the same as during a read transfer. In a read transfer, the slave device must provide data during the ENABLE cycle, and the data is sampled at the rising edge of the clock at the end of the ENABLE cycle. By analyzing the APB bus's transmission signals, information about the bus transmission state over time can be obtained. For example... Figure 1 The APB bus transmission signal shown in the example has two write transfer states, corresponding to two write transfer operations, occurring in the time periods T1-T3 and T4-T6 respectively. In the first write transfer operation, the CPU writes data date1 to address addr1, and in the second write transfer operation, the CPU writes data date2 to address addr2.

[0050] In this embodiment, the code conversion operation can be determined based on the changes in the aforementioned bus transmission state. As a typical example, taking the APB bus as an example, the specific steps for determining whether to trigger the code conversion operation are as follows: The bus clock signal PCLK, bus strobe signal PSEL, and enable control signal PENABLE in the APB bus transmission signals are parsed to obtain information on the changes in the bus transmission state over time; when the bus transmission state is a read / write transmission state, the code conversion operation is triggered. When the code conversion operation is triggered, the corresponding bus configuration information can be obtained based on the current bus transmission state (which can be a write transmission state or a read transmission state). The bus configuration information is then described using SystemVerilog language to form the corresponding SoC-level test case code. This SoC-level test case code is used for the SoC interface bus configuration of the aforementioned IP module under test.

[0051] Specifically, when the bus transfer state is write transfer state, the bus address and write data corresponding to this write operation can be obtained according to the bus address signal PADDR and the bus write data signal PWDATA. Then, the corresponding bus configuration information is described in System Verilog language to form the corresponding SoC-level test case code, and the code is added to the corresponding SoC-level test case of the IP module under test.

[0052] When the bus transfer state is read transfer state, the read data information corresponding to this read operation can be obtained according to the bus address signal PADDR and the bus read data signal PRDATA. Then, the corresponding bus configuration information is described in System Verilog language to form the corresponding SoC-level test case code, and the code is added to the corresponding SoC-level test case of the IP module under test.

[0053] As an example, not a limitation, Figure 1 Taking the APB bus transmission signal example, the identified bus transmission states include three states: State 1, no PSEL is detected at the rising edge of the PCLK clock (PSEL=0), which is the IDLE state; State 2, PSEL is detected at the rising edge of the PCLK clock, at which time PSEL=1 and PENABLE=0, which is the SETUP state; State 3, when PSEL is high, PENABLE is detected at the next rising edge of the PCLK clock, at which time PSEL=1 and PENABLE=1, which is the write transmission state. A code conversion operation is triggered in State 3.

[0054] The transition from state 1 to state 2 to state 3 and back to state 1 can be a cyclical state transition process, with the code transition operation triggered only in state 3. When the code transition operation is triggered, the corresponding bus configuration information can be obtained based on the current write transfer state. This bus configuration information is then described using System Verilog to form the corresponding SoC-level test case code, for example, based on... Figure 1 The simulated waveform shown is used to identify and convert the SoC-level test case code, which is as follows:

[0055] CPU_write(addr1, date1);

[0056] CPU_write(addr2, date2);

[0057] The corresponding bus configuration information is as follows:

[0058] The CPU writes data date1 to address addr1;

[0059] The CPU writes the data date2 to address addr2.

[0060] See Figure 3 As shown, in another embodiment of this example, a verification step for interface bus configuration conversion may also be included, which may be as follows:

[0061] For the aforementioned IP-level simulation waveform file—that is, the IP-level verification simulation waveform file—the occurrence time and number of bus transmission states that triggered the code conversion operation are recorded, and a first table file is generated based on the occurrence time and number of occurrences. Furthermore, based on the aforementioned SoC-level test case executed in the SoC-level UVM verification environment, a SoC-level simulation waveform file is obtained. This SoC-level simulation waveform file contains the simulation timing information and bus transmission signals of the aforementioned SoC-level test case. The aforementioned SoC-level simulation waveform file is parsed to obtain information on the changes in bus transmission states over time. Based on the changes in the aforementioned bus transmission states, it is determined whether a code conversion operation has been triggered. The occurrence time and number of bus transmission states that triggered the code conversion operation are recorded, and a second table file is generated. The aforementioned first table file and second table file are compared to determine whether the recorded contents are consistent. When the contents are determined to be inconsistent, the inconsistent contents are marked in the first table file and / or an error message is output.

[0062] As an example, and not a limitation, see the example of the first table file generated. Figure 4 As shown, the generated second table file can be found here. Figure 5 As shown, in Figure 4 and Figure 5The occurrence time and number of times of state 3 (bus transmission state that triggered code conversion operation) recorded in the first and second table files are inconsistent. The time of state 3 is different when the number of times is 2. Therefore, the inconsistent content is marked with a box in the first and second table files to prompt the user to verify the conversion information.

[0063] Another embodiment of the present invention also provides an information processing device based on simulation waveforms in chip simulation.

[0064] The information processing device includes an information acquisition module, a waveform file parsing module, and a code conversion module.

[0065] The information acquisition module is used to acquire the IP-level simulation waveform file obtained after the IP-level test case of the IP module under test is executed in the IP-level UVM verification environment. The IP-level simulation waveform file contains the simulation timing information and bus transmission signals of the aforementioned IP-level test case.

[0066] The waveform file parsing module parses the aforementioned bus transmission signals according to the simulation timing of the IP-level test case, obtains the information on the change of bus transmission status over time, and determines whether to trigger the code conversion operation based on the change of the aforementioned bus transmission status.

[0067] The code conversion module is used to obtain the corresponding bus configuration information based on the current bus transmission status when the code conversion operation is triggered, and to describe the bus configuration information in System Verilog language to form the corresponding SoC-level test case code. The SoC-level test case code is used for the SoC interface bus configuration of the aforementioned IP module under test.

[0068] The IP module under test can be a processor IP module, a memory IP module, an input / output (I / O) interface IP module, or other dedicated function IP modules.

[0069] The simulation waveform file can also record the name and bus type of the IP module under test.

[0070] Preferably, when the connection bus of the IP module under test is an Advanced Peripheral Bus (APB), the steps to determine whether to trigger the code conversion operation are as follows: parse the bus clock signal PCLK, bus strobe signal PSEL, and enable control signal PENABLE in the APB bus transmission signals to obtain information on the change of bus transmission status over time; when the bus transmission status is a read / write transmission status, trigger the code conversion operation.

[0071] Preferably, the information processing device may further include a verification module.

[0072] The verification module is configured to: record the occurrence time and number of bus transmission states that triggered code conversion operations for the aforementioned IP-level simulation waveform file, and generate a first table file based on the occurrence time and number of occurrences; and, based on the SoC-level simulation waveform file obtained after executing the aforementioned SoC-level test case in the SoC-level UVM verification environment, the SoC-level simulation waveform file records the simulation timing information and bus transmission signals of the aforementioned SoC-level test case, parse the aforementioned SoC-level simulation waveform file to obtain the bus transmission state change information over time, determine whether a code conversion operation is triggered based on the changes in the aforementioned bus transmission state, record the occurrence time and number of bus transmission states that triggered the code conversion operation, and generate a second table file; compare the aforementioned first table file and second table file to determine whether the contents recorded in the two are consistent; when the contents are determined to be inconsistent, mark the inconsistent contents in the first table file and / or output an error message in the second table file.

[0073] Other technical features are described in the previous embodiments and will not be repeated here.

[0074] Another embodiment of the present invention also provides a method for case porting in chip simulation, including the step of converting the IP interface bus configuration of the IP module into the SoC interface bus configuration, wherein the interface bus configuration is automatically converted according to the aforementioned method.

[0075] Other technical features are described in the previous embodiments and will not be repeated here.

[0076] Another embodiment of the present invention also provides a chip testing system, the system including a test case porting device, the test case porting device being used to convert test cases in an IP-level UVM verification environment of an IP module into test cases in a SOC-level UVM verification environment, the test case porting device being configured to automatically convert interface bus configurations using the aforementioned method.

[0077] The IP-level UVM verification environment interacts with the IP module under test through the IP interface module, and performs module-level functional verification of the IP module through IP-level test cases.

[0078] The SOC-level UVM verification environment interacts with the aforementioned IP module under test in the chip under test through the SOC interface module, and verifies the function of the IP module under test in the chip under test through the converted SOC-level test case.

[0079] Specifically, both the IP-level UVM verification environment and the SOC-level UVM verification environment are built using the general verification methodology UVM and the System Verilog language.

[0080] An IP-level UVM verification environment may include test cases and the following components: a reference model, an input agent (In_agent), an output agent (Out_agent), and a scoreboard. The input agent (In_agent) encapsulates and instantiates the sequencer, driver, and monitor. The sequencer manages the sequence generator to produce valid sequence sequences. The sequence generator produces transactions, which define basic item data packets. The driver applies test stimuli and performs data transformations on the IP modules. The monitor collects the output data from the IP modules and performs data transformations. The output agent (Out_agent) also includes a monitor to collect the output data from the IP modules after applying stimuli. The scoreboard, connected to the reference model, compares the output data collected by the monitor of the output agent with the expected values ​​of the reference model and outputs the comparison results.

[0081] The IP-level UVM verification environment may also include a top-level file called `testbench top`, which is used to initialize and connect the entire UVM verification environment. During testing, test cases are started and executed through the `run_test` function.

[0082] The SOC-level UVM verification environment is isomorphic (using the same structure) to the IP-level UVM verification environment, and also includes test cases and the aforementioned components: Reference model, In_agent, Out_agent, and scoreboard. The SOC-level UVM verification environment may also include a top-level file, `testbench top`, used for initializing and connecting the entire UVM verification environment. During testing, the `run_test` function is used to start and execute test cases. The setup of the UVM verification environment, configuration of verification components, and data processing can be found in existing technologies and will not be elaborated upon here.

[0083] The technical features of automatic conversion of interface bus configuration are described in the previous embodiments and will not be repeated here.

[0084] In the above description, the disclosure of this invention is not intended to limit itself to these aspects. Rather, within the scope of the objectives of this disclosure, components can be selectively and operationally combined in any number. Furthermore, terms such as “comprising,” “encompassing,” and “having” should be interpreted by default as inclusive or open-ended, rather than exclusive or closed, unless explicitly defined as such. All technical, scientific, or other terms are to be understood by those skilled in the art, unless defined as such. Public terms found in dictionaries should not be interpreted too idealistically or impractically in the context of the relevant technical documents, unless explicitly defined as such in this disclosure. Any modifications or alterations made by those skilled in the art based on the foregoing disclosure are within the scope of the claims.

Claims

1. A method of processing information based on a simulation waveform in chip simulation, characterized by The method comprises the steps of: obtaining an IP-level simulation waveform file obtained after an IP-level test case of a tested IP module is executed in an IP-level UVM verification environment, wherein the IP-level simulation waveform file records simulation timing information and bus transmission signals of the IP-level test case; analyzing the bus transmission signals according to the simulation timing of the IP-level test case to obtain information about the change of bus transmission states over time, and determining whether to trigger a code conversion operation according to the change of the bus transmission states; when the code conversion operation is triggered, obtaining corresponding bus configuration information according to the current bus transmission state, describing the bus configuration information in System Verilog language to form a corresponding SoC-level test case code, and using the SoC-level test case code for SoC interface bus configuration of the tested IP module.

2. The method of claim 1, wherein: The tested IP module is a processor IP module, a memory IP module, an input / output (I / O) interface IP module or other special function IP module.

3. The method of claim 1, wherein: The simulation waveform file also records the name of the tested IP module and the bus type.

4. The method of claim 1, wherein: The connection bus of the tested IP module is an advanced peripheral bus (APB) bus, and the step of determining whether to trigger the code conversion operation is as follows: analyzing bus clock signals PCLK, bus selection signals PSEL and enable control signals PENABLE in the APB bus transmission signals to obtain information about the change of bus transmission states over time; when the bus transmission state is a read / write transmission state, triggering the code conversion operation.

5. The method of claim 4, wherein: when the bus transmission state is a write transmission state, obtaining the bus address and write data corresponding to the write operation according to bus address signals PADDR and bus write data signals PWDATA, describing the corresponding bus configuration information in System Verilog language to form a corresponding SoC-level test case code, and adding the code to the corresponding SoC-level test case of the tested IP module; when the bus transmission state is a read transmission state, obtaining read data information corresponding to the read operation according to bus address signals PADDR and bus read data signals PRDATA, describing the corresponding bus configuration information in System Verilog language to form a corresponding SoC-level test case code, and adding the code to the corresponding SoC-level test case of the tested IP module.

6. The method of claim 1, wherein, The method further comprises a verification step of interface bus configuration conversion, which is as follows: for the IP-level simulation waveform file, recording the time points and the number of times when the bus transmission state triggering the code conversion operation occurs, and generating a first table file based on the time points and the number of times; and ​ According to the SoC-level simulation waveform file obtained after the execution of the aforementioned SoC-level test case in the SoC-level UVM verification environment, the simulation timing information and bus transmission signals of the aforementioned SoC-level test case are recorded in the SoC-level simulation waveform file, the bus transmission state change information over time is obtained by analyzing the aforementioned SoC-level simulation waveform file, whether the code conversion operation is triggered is determined according to the change of the aforementioned bus transmission state, the time point and the number of times of the occurrence of the bus transmission state triggering the code conversion operation are recorded, and a second table file is generated; The aforementioned first table file and the second table file are compared to determine whether the recorded contents are consistent; When it is determined that the contents are inconsistent, the inconsistent contents are marked in the first table file and the second table file, and / or an error prompt is output.

7. An information processing apparatus based on simulation waveforms in chip simulation, characterized by The structure comprises: An information acquisition module is configured to obtain an IP-level simulation waveform file obtained after the execution of an IP-level test case of an IP module in an IP-level UVM verification environment, and the simulation timing information and bus transmission signals of the aforementioned IP-level test case are recorded in the IP-level simulation waveform file; A waveform file analysis module is configured to analyze the aforementioned bus transmission signals according to the simulation timing of the IP-level test case to obtain bus transmission state change information over time, and determine whether the code conversion operation is triggered according to the change of the aforementioned bus transmission state; A code conversion module is configured to obtain corresponding bus configuration information according to the current bus transmission state when the code conversion operation is triggered, describe the bus configuration information in System Verilog language to form a corresponding SoC-level test case code, and use the SoC-level test case code for SoC interface bus configuration of the aforementioned IP module under test.

8. A method for case porting in chip emulation, comprising the step of converting an IP interface bus configuration of an IP module to a SoC interface bus configuration, characterized in that: The method according to any one of claims 1-6 is used for automatic conversion of interface bus configuration.

9. A chip testing system, characterized by: A case transplantation device is configured to convert a test case in an IP-level UVM verification environment of an IP module into a test case in an SoC-level UVM verification environment, and the case transplantation device is configured to perform automatic conversion of interface bus configuration by the method according to any one of claims 1-6.

10. The system for testing a chip according to claim 9, wherein: The IP-level UVM verification environment interacts with the IP module under test through an IP interface module, and performs module-level functional verification on the IP module through an IP-level test case; the SoC-level UVM verification environment interacts with the aforementioned IP module under test in the chip under test through an SoC interface module, and verifies the function of the IP module under test in the chip under test through the converted SoC-level test case.

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