Single non-volatile device stores synaptic structure of positive and negative weights, neural network circuit, computing and storing integrated chip and electronic equipment

Abstract

The application relates to a synapse structure for storing positive and negative weights of a single non-volatile device, which comprises a first non-volatile memory (NVM) column, a second NVM column, a current-voltage converter (IVC), an activation function circuit, a common-mode signal calculation circuit and a common-mode signal extraction circuit; the input ends of the first NVM column and the second NVM column are directly connected with an input signal group, the output end of the first NVM column is connected with the input end of the IVC, the output end of the IVC is connected with the input end of the activation function circuit, the output end of the second NVM column is connected with the input end of the common-mode signal calculation circuit, the output end of the common-mode signal calculation circuit is connected with the input end of the common-mode signal extraction circuit, and the output end of the common-mode signal extraction circuit is connected with the output end of the first NVM column. The application reduces the device resource consumption in a neural network circuit by sharing a common-mode conductance NVM column and a simple peripheral circuit.

Description

Technical Field

[0001] This invention relates to application-specific integrated circuits for artificial intelligence computing based on in-memory computing architecture, and particularly to synaptic structures, neural network circuits, in-memory computing chips, and electronic devices that store positive and negative weights in a single non-volatile device. Background Technology

[0002] In-memory computing (IMC) based AI computing is an important technology in the field of AI hardware computing with a wide range of applications. The basic unit of this IMC is modeled after the synaptic structure of a neuron, mainly consisting of columns of non-volatile memory (NVM) and peripheral circuits. The basic principle is to map the weights of the neural network to the conductance stored in the NVM and perform neuromorphic calculations using Kirchhoff's voltage and current laws.

[0003] Neurons can have both positive and negative weights, but NVMs can only store positive conductance. Traditional structures use two memristors to represent one synaptic weight, along with a current subtractor to store negative conductance, or they use differential input / output circuits to store negative conductance with two conductance values ​​and positive and negative input signals. These traditional structures incur significant overhead in terms of NVM and peripheral circuitry resources. Summary of the Invention

[0004] Therefore, it is necessary to propose a synaptic structure that stores positive and negative weights using a single non-volatile device to effectively optimize the device overhead problem in existing structures. To achieve this objective, the present invention adopts the following technical solution:

[0005] In a first aspect, a synaptic structure is provided for storing positive and negative weights in a single non-volatile device, comprising: a first non-volatile memory (NVM) column, a second NVM column, a current-to-voltage converter (IVC), an activation function (ACT) circuit, a common-mode signal calculation circuit, and a common-mode signal decimation circuit; the input terminals of the first NVM column and the second NVM column are directly connected to an input signal group, the output terminal of the first NVM column is connected to the input terminal of the IVC, the output terminal of the IVC is connected to the input terminal of the ACT, the output terminal of the second NVM column is connected to the input terminal of the common-mode signal calculation circuit, the output terminal of the common-mode signal calculation circuit is connected to the input terminal of the common-mode signal decimation circuit, and the output terminal of the common-mode signal decimation circuit is connected to the output terminal of the first NVM column.

[0006] Optionally, the NVMs in the first and second NVM columns are memristors, and the number of each is M. The input terminal of the i-th NVM is connected to the i-th input signal Vin of the input signal group. i, i = 1, 2, ..., M; the output terminals of all NVMs in the first NVM column are connected to the output terminal of the first NVM column, wherein the stored value of the i-th NVM in the first NVM column is the common-mode conductance (G) and the differential-mode conductance (g) value. i The sum of (i = 1, 2, ..., M); the output terminals of all NVMs in the second NVM column are connected to the output terminal of the second NVM column, and the stored value of the NVMs in the second NVM column is G.

[0007] Optionally, the IVC consists of an operational amplifier and a feedback resistor connected between the output and inverting input of the operational amplifier, with the non-inverting input connected to a standard potential V. ref The inverting input of the operational amplifier is connected to the output of the first NVM column as described above; the input signal group and the output voltage of the IVC satisfy the following relationship: V out -V ref =-R F *(Vin1*g1+Vin2*g2+...+Vin M *g M ), where V out V is the output voltage of the IVC. ref R is the standard potential. F For the feedback resistor value, Vin i Let g be the i-th input signal in the input signal group, i = 1, 2, ..., M. i This is the differential mode conductance value stored in the i-th NVM in the first NVM column.

[0008] Optionally, the input-output characteristic curves of this ACT are opposite in direction to the standard activation function curves and are scaled proportionally.

[0009] Optionally, the signal calculated by the common-mode signal calculation circuit is a common-mode current signal, and the calculated common-mode current satisfies the following relationship with the input signal group: I CM =G*(Vin1+Vin2+...+Vin) M ), where I CM G represents the common-mode current, and G is the common-mode conductance value stored in the NVMs of the first and second NVM columns. Vin i Let i be the i-th input signal in the input signal group, where i = 1, 2, ..., M;

[0010] The common-mode signal calculation circuit consists of a positive current mirror and a negative current mirror. The input terminals of both the positive and negative current mirrors are connected to the output terminals of the second NVM column. The mirror terminals of both the positive and negative current mirrors are connected to a standard potential Vref. The current of the positive current mirror is I. P The output voltage V at the voltage output terminal of the forward current mirrorP with I P Related; the current of the negative current mirror is I. N The output voltage V at the negative current mirror voltage output terminal N with I N Related; I P I N and I CM Satisfy the following relationship: I CM =I N -I P .

[0011] Optionally, the common-mode signal extraction circuit consists of an NMOS and a PMOS. The source of the NMOS is connected to the lowest potential, and the source of the PMOS is connected to the highest potential. The drains of the NMOS and PMOS are connected to the output terminal of the first NMOS column as described above. The gates of the NMOS and PMOS are connected to the negative current mirror voltage output terminal and the positive current mirror voltage output terminal as described above, respectively. The extraction current I of the common-mode signal extraction circuit is... EX And the common-mode current I as described above CM The relationship satisfies the following relation: I EX =-I CM .

[0012] Secondly, a neural network circuit is provided, comprising multiple synaptic structures, as described above, where a single non-volatile device stores positive and negative weights.

[0013] Optionally, the multiple synaptic structures share one or more sets of NVM columns storing common-mode conductance values ​​G.

[0014] Thirdly, a memory computing chip is provided, including a synaptic structure for storing positive and negative weights or a neural network circuit as described above, using a single non-volatile device.

[0015] Fourthly, an electronic device is provided, comprising a synaptic structure storing positive and negative weights in a single non-volatile device as described above, or a neural network circuit as described above, or a memory computing chip as described above.

[0016] The present invention provides a synaptic structure for storing positive and negative weights using a single non-volatile device, comprising: a first non-volatile memory (NVM) column, a second NVM column, an inductively coupled current converter (IVC), an activation function circuit (ACT), a common-mode signal calculation circuit, and a common-mode signal decimation circuit; the input terminals of the first and second NVM columns are directly connected to an input signal group, the output terminal of the first NVM column is connected to the input terminal of the IVC, the output terminal of the IVC is connected to the input terminal of the ACT, the output terminal of the second NVM column is connected to the input terminal of the common-mode signal calculation circuit, the output terminal of the common-mode signal calculation circuit is connected to the input terminal of the common-mode signal decimation circuit, and the output terminal of the common-mode signal decimation circuit is connected to the output terminal of the first NVM column. By mapping synaptic weights to a combination of common-mode conductance and differential-mode conductance, and by extracting common-mode current to achieve the purpose of storing negative conductance, on the one hand, the NVM column storing common-mode conductance is shared in the same column in a large-scale synaptic array, reducing the overhead of NVM devices; on the other hand, compared with current subtractors or circuits with high common-mode requirements, the use of current buffers and current mirrors greatly reduces the device overhead of peripheral circuits. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0018] Figure 1 A circuit diagram of a synaptic structure storing positive and negative weights in a single non-volatile device in one embodiment;

[0019] Figure 2 The input-output characteristic curves of the activation function circuit used in one embodiment are shown.

[0020] Figure 3 This is an example of an activation function curve corresponding to the activation function circuit.

[0021] Figure 4 This is a traditional neural network circuit diagram;

[0022] Figure 5 This is a neural network circuit diagram in one embodiment. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] To facilitate understanding of the present invention and to make the above-mentioned objects, features, and advantages of the present invention more apparent, a detailed description of specific embodiments of the invention is provided in conjunction with the accompanying drawings. Numerous details are set forth in the following description to provide a thorough understanding of the invention, and preferred embodiments are shown in the accompanying drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of the invention. The invention can be implemented in many other ways than those described herein, and similar modifications can be made by those skilled in the art without departing from the spirit of the invention; therefore, the invention is not limited to the specific embodiments disclosed below.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or the number of named technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0026] With the continuous development of artificial intelligence, the computational demands of neural networks are increasing, placing new requirements on the hardware circuits used to implement them. The von Neumann architecture, with its "memory wall" characteristics, cannot efficiently complete neural network computation tasks. Therefore, new hardware implementations are constantly being proposed. One such implementation, an electronic neuron synaptic structure based on non-volatile memory (NVM), can efficiently perform neural network computations. However, research on existing synaptic structures has revealed significant device resource overhead. This invention proposes a synaptic structure based on differential-mode conductance and common-mode conductance, storing positive and negative weights using a single non-volatile device, thus effectively optimizing the device resource overhead problem.

[0027] Figure 1 A synaptic structure diagram illustrating the storage of positive and negative weights using a single non-volatile device, according to an embodiment of the present invention, is shown. Figure 1 As shown, it includes: a first non-volatile memory (NVM) column 11, a second NVM column 12, a current-to-voltage converter (IVC) 13, an activation function circuit (ACT) 14, a common-mode signal calculation circuit 15, and a common-mode signal extraction circuit 16;

[0028] The input terminals of the first NVM column 11 and the second NVM column 12 are directly connected to the input signal group. The output terminal of the first NVM column 11 is connected to the input terminal of IVC 13. The output terminal of IVC 13 is connected to the input terminal of ACT 14. The output terminal of the second NVM column 12 is connected to the input terminal of the common-mode signal calculation circuit 15. The output terminal of the common-mode signal calculation circuit 15 is connected to the input terminal of the common-mode signal extraction circuit 16. The output terminal of the common-mode signal extraction circuit 16 is connected to the output terminal of the first NVM column 11.

[0029] In this embodiment, the NVM can be selected as a memristor.

[0030] In another alternative embodiment, the NVM can be selected as a phase-change memory.

[0031] like Figure 1 As shown, the input terminals of different memristors in the first memristor column 11 are connected to different input signals Vin in the input signal group Vin. i Where i = 1, 2, ..., M, the output terminals of different memristors are connected together to form the output terminals of the first memristor column 11, and the conductance stored in the i-th memristor is the sum of the differential-mode conductance and the common-mode conductance, G + g. i The input terminals of different memristors in the second memristor column 12 are connected to different input signals Vin in the input signal group Vin. i , where i = 1, 2, ..., M, the output terminals of different memristors are connected together to form the output terminals of the second memristor column 12, and the conductance value stored in all memristors is the common-mode conductance G.

[0032] The IVC13 consists of an operational amplifier and a feedback resistor. The feedback resistor is connected between the output and inverting input of the operational amplifier, and the non-inverting input of the operational amplifier is connected to a standard potential V. ref The inverting input of the operational amplifier is connected to the output of the first NVM column 11, and the output of the IVC is connected to the input of the ACT14. In this embodiment, V ref If the voltage is set to 0V, then the output voltage of the IVC and the input signal group satisfy the following relationship: V out =-R F *(Vin1*g1+Vin2*g2+...+Vin M *g M ).

[0033] In another alternative embodiment, IVC13 can be selected as a transimpedance amplifier (TIA).

[0034] The output of ACT14 is the output of the synaptic structure. Due to the circuit characteristics of IVC13, the output voltage of IVC13 has a 180° phase difference compared to the standard circuit, which is inconsistent with the principle of traditional synaptic structures. Therefore, as... Figure 2 The ACT14 input-output characteristic curve shown is similar to... Figure 3 The activation function curves shown are in opposite directions and their sizes are scaled proportionally.

[0035] like Figure 1 As shown, in the common-mode current calculation circuit 15, M1 to M4 form a forward current mirror, the source terminal of M3 is the input terminal of the forward current mirror, and the source terminal of M4 is the mirror terminal of the forward current mirror and is connected to V. ref The source terminals of M1 and M2 are connected to VDD. The current flowing through M1 and M3 is equal to the current flowing through M2 and M4, both being I. P M5 to M6 form a negative current mirror. The source terminal of M5 is the input terminal of the negative current mirror, and the source terminal of M6 is the mirror terminal of the negative current mirror and is connected to V. ref The source terminals of M7 and M8 are connected to VSS. The current flowing through M5 and M7 is equal to the current flowing through M6 and M8, both being I. N The common-mode current I flowing into the common-mode current calculation circuit. CM with I P I N Satisfy the following relationship: I CM =I N -I P .

[0036] Since the mirror terminals of the forward current mirror and the reverse current mirror are connected to V... ref The current flowing through M3 and M4 is the same as the current flowing through M1 and M2, and the current flowing through M6 and M8 is the same as the current flowing through M5 and M7. Since their width-to-length ratios are identical, the voltage at the source terminals of M3 and M5 is clamped at V. ref I CM The input signal group Vin and common-mode conductance G satisfy the following relationship: I CM =G*(Vin1+Vin2+...+Vin) M Since MOSFETs M1 through M8 are all operating in the saturation region, the current I in the common-mode current calculation circuit 15 is... P and current I N They satisfy a square relationship with the output voltages Vp and Vn, respectively.

[0037] In the common-mode current extraction circuit 16, there are only two MOS transistors, M9 and M10, whose gate-source voltages are the same as those of M1 and M7 in the common-mode current calculation circuit 15, respectively. Since the non-inverting input of the operational amplifier in IVC13 is connected to V... ref Therefore, its inverting terminal potential is clamped at V. refTherefore, the source potentials of M9 and M10 are V. ref M9 and M10 operate in the saturation region, therefore the current flowing through M9 and M10 is equal to I... P and I N According to Kirchhoff's current law, we can obtain: I EX =I P -I N =-I CM .

[0038] Because the inverting input of the operational amplifier in IVC13 is clamped at V ref The current I1 flowing out from the first memristor column 11 is I1 = Vin1*(G+g1)+Vin2*(G+g2)+…+Vin M *(G+g M According to Kirchhoff's current law, the final current flowing into IVC13 is I2 = I1 + I... EX =I1-I CM =Vin1*g1+Vin2*g2+...+Vin M *g M Therefore, I2 is only related to the input voltage group Vin and the differential-mode conductance value g stored in the second memristor column 11. This differential-mode conductance can be positive or negative, thus completing the function of storing positive and negative conductance in a single memristor.

[0039] To further demonstrate the innovativeness of this invention, the following will explain the implementation principle of neural network circuits and highlight the advantages of the synaptic structure described in this invention by comparing traditional structures with the structure of this invention.

[0040] The core of a neural network is matrix multiplication, which is also the most computationally intensive operation in neural network algorithms. The basic principle of neural network matrix multiplication is to perform the calculation XW=Y, where the input vector is X, the weight matrix is ​​W, and the final multiplication result vector is Y. The three parameters X, W, and Y are mapped to three circuit parameters Vin, G, and I. Efficient matrix multiplication calculation is completed through a crossbar array composed of memristors and Kirchhoff's laws, that is, XW=Y is mapped to VinG=I.

[0041] The traditional neural network circuit diagram obtained based on VinG=I is as follows: Figure 4As shown, since a simple single memristor cannot store negative conductance, and the neural network weight matrix W requires negative parameters, the traditional solution requires two memristors and an additional current subtractor for each column to store the negative weights. On the one hand, this structure incurs significant overhead in memristor resources, as the number of memristors directly determines the complexity of the peripheral control circuit. On the other hand, the current subtractor requires multiple operational amplifiers to work together and necessitates resistors that are highly susceptible to the influence of CMOS process technology, which introduces errors into the final actual circuit.

[0042] Based on the shortcomings of the traditional structure, the proposed method of using a shared common-mode conductance NVM column solves this problem and accomplishes this function with fewer external circuit devices. Figure 5 This invention illustrates a neural network circuit that, unlike traditional structures, shares the same memristor column and a current buffer composed of eight MOSFETs. Furthermore, each column of the neural network circuit utilizes two additional MOSFETs to extract common-mode current. In summary, the structure proposed in this invention reduces device resource overhead at both the memristor and peripheral circuit levels.

[0043] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A synaptic structure for storing positive and negative weights using a single non-volatile device, characterized in that, include: The system includes a first non-volatile memory (NVM) column, a second NVM column, a current-to-voltage converter (IVC), an activation function circuit, a common-mode signal calculation circuit, and a common-mode signal extraction circuit. The input terminals of the first and second NVM columns are directly connected to the input signal group. The output terminal of the first NVM column is connected to the input terminal of the IVC, and the output terminal of the IVC is connected to the input terminal of the activation function circuit. The output terminal of the second NVM column is connected to the input terminal of the common-mode signal calculation circuit. The output terminal of the common-mode signal calculation circuit is connected to the input terminal of the common-mode signal decimation circuit, and the output terminal of the common-mode signal decimation circuit is connected to the output terminal of the first NVM column. The NVMs in the first and second NVM columns are memristors, and the number of each is M. The input terminal of the i-th NVM is connected to the i-th input signal Vin of the input signal group. i , i = 1, 2, ..., M; the output terminals of all NVMs in the first NVM column are connected to the output terminal of the first NVM column, wherein the stored values ​​of the i-th NVM in the first NVM column are the common-mode conductance value G and the differential-mode conductance value g. i The sum of i = 1, 2, ..., M; the output terminals of all NVMs in the second NVM column are connected to the output terminal of the second NVM column, and the stored value of the NVMs in the second NVM column is G. The common-mode signal calculation circuit calculates a common-mode current signal, and the calculated common-mode current and the input signal group satisfy the following relationship: I CM =G*(Vin1+Vin2+…+Vin) M ), where I CM G represents the common-mode current, G is the common-mode conductance value stored in NVM in the first and second NVM columns, and Vin is the common-mode current. i Let i be the i-th input signal in the input signal group, i = 1, 2, ..., M. The common-mode signal calculation circuit consists of a positive current mirror and a negative current mirror. The input terminals of the positive and negative current mirrors are connected to the output terminals of the second NVM column, and the mirror terminals of the positive and negative current mirrors are connected to a standard potential Vref. The current of the positive current mirror is I. P The output voltage V at the positive current mirror voltage output terminal P with I P Related; the current of the negative current mirror is I. N The output voltage V at the negative current mirror voltage output terminal N with I N Related; I P I N and I CM Satisfy the following relationship: I CM =I N -I P , The common-mode signal extraction circuit consists of an NMOS and a PMOS. The source of the NMOS is connected to the lowest potential, and the source of the PMOS is connected to the highest potential. The drains of the NMOS and PMOS are connected to the output terminal of the first NVM column. The gates of the NMOS and PMOS are connected to the negative current mirror voltage output terminal and the positive current mirror voltage output terminal, respectively. The extraction current I of the common-mode signal extraction circuit is... EX Common mode current I CM The relationship satisfies the following relation: I EX =-I CM , The activation function circuit uses a tanh-type activation function, and its input-output characteristic curve is inversely related to the standard activation function curve.

2. The synaptic structure for storing positive and negative weights using a single non-volatile device as described in claim 1, characterized in that, The IVC consists of an operational amplifier and a feedback resistor. The feedback resistor is connected between the output terminal and the inverting input terminal of the operational amplifier, and the non-inverting input terminal of the operational amplifier is connected to a standard potential V. ref The inverting input of the operational amplifier is connected to the output of the first NVM column; the input signal group and the output voltage of the IVC satisfy the following relationship: V out -V ref =-R F *(Vin1*g1+Vin2*g2+…+Vin M *g M ), where V out V is the output voltage of the IVC. ref R is the standard potential. F For the feedback resistor value, Vin i Let g be the i-th input signal in the input signal group, i = 1, 2, ..., M. i The differential mode conductance value stored in the i-th NVM in the first NVM column.

3. A neural network circuit, characterized in that, It includes multiple synaptic structures that store positive and negative weights in a single non-volatile device as described in any one of claims 1-2.

4. A neural network circuit according to claim 3, characterized in that, The multiple synaptic structures share one or more sets of NVM columns for storing common-mode conductance values ​​G.

5. A memory computing chip, characterized in that, This includes a synaptic structure for storing positive and negative weights in a single non-volatile device as described in any one of claims 1-2, or a neural network circuit as described in claims 3-4.

6. An electronic device, characterized in that, This includes a synaptic structure for storing positive and negative weights in a single non-volatile device as described in any one of claims 1-2, a neural network circuit as described in any one of claims 3-4, or a memory computing chip as described in claim 5.

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