Display panel, driving method thereof, and display device

Abstract

A display panel, a driving method thereof and a display device solve the problem of luminance difference in different display areas of an under-screen camera product in the prior art. The display panel comprises at least one selection signal line, at least one data signal line, a selection module, and an adjustable resistance module. The input end of the selection module is connected to the at least one selection signal line and the at least one data signal line, and the output end is connected to a plurality of first sub-pixel columns and the adjustable resistance module. The output end of the adjustable resistance module is connected to a plurality of second sub-pixel columns. The selection module is used for sequentially selecting one data signal line from the at least one data signal line based on selection signals received by the at least one selection signal line in sequence, and outputting a driving voltage on the selected data signal line. The adjustable resistance module is used for outputting the driving voltage to the plurality of second sub-pixel columns after voltage reduction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device. BACKGROUND

[0002] A display device, such as a mobile phone, usually sets a camera under the screen (referred to as an under-screen camera product). In order to ensure the light transmittance of the area where the camera is set, the pixel aperture ratio of the area of the display screen corresponding to the camera is usually lower than that of other areas. In this case, if the same driving voltage is used for the entire display screen, due to the difference in pixel aperture ratio, the area where the camera is set and other areas will present a difference in brightness, affecting the display effect. SUMMARY

[0003] Therefore, the embodiments of the present application provide a display panel, a driving method thereof and a display device to solve the problem of brightness difference between different display areas of the under-screen camera product in the prior art.

[0004] The first aspect of the present application provides a display panel having a first display area and a second display area, the display panel comprising a sub-pixel array, the sub-pixel array comprising a plurality of first sub-pixel columns located in the first display area and a plurality of second sub-pixel columns located in the second display area, the first sub-pixel columns and the second sub-pixel columns forming a pixel array, the aperture ratio of a sub-pixel in the first sub-pixel column being greater than the aperture ratio of a sub-pixel in the second sub-pixel column. The display panel further comprises: at least one gate signal line; at least one data signal line; a gate module having an input end connected to the at least one gate signal line and the at least one data signal line and an output end connected to the plurality of first sub-pixel columns and an adjustable resistance module; and the adjustable resistance module having an output end connected to the plurality of second sub-pixel columns. The gate module is configured to gate one data signal line in the at least one data signal line based on a gate signal received by the at least one gate signal line in sequence and output a driving voltage on the gated data signal line, and the adjustable resistance module is configured to output the driving voltage to the plurality of second sub-pixel columns after step-down.

[0005] The second aspect of the present application provides a driving method of a display panel for driving the display panel provided by the embodiments of the present application. The driving method comprises: obtaining a gray scale voltage signal of a to-be-displayed image frame and a gate signal, the timing of the gate signal being the same as that of a row scanning signal of a sub-pixel array; providing respective driving voltages of different color sub-pixels in the gray scale voltage signal to at least one data signal line; and sequentially providing the gate signal to at least one gate signal line to enable the display panel to display the to-be-displayed image frame.

[0006] The third aspect of the present application provides a display device comprising the display panel provided by any of the above embodiments.

[0007] According to the display panel and its driving method and display device provided in the embodiments of this application, by setting an adjustable resistor module in the display panel, a portion of the driving voltage is consumed by the adjustable resistor module before being provided to the second sub-pixel column, so that the driving voltage obtained by the sub-pixels of the second sub-pixel column is less than the driving voltage (Vdata) obtained by the sub-pixels of the first sub-pixel column. Since the light-emitting device in the sub-pixel is a P-type metal-oxide-semiconductor field-effect transistor (PMOS), the smaller the driving voltage Vdata obtained by the light-emitting device, the higher the brightness, thereby making the brightness of the main and sub-screens consistent. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an under-display camera product in related technologies.

[0009] Figure 2 This is a schematic diagram of the structure of the display panel provided in the first embodiment of this application.

[0010] Figure 3 This is a schematic diagram of the structure of the display panel provided in the second embodiment of this application.

[0011] Figure 4 This is a schematic diagram of the structure of the display panel provided in the third embodiment of this application.

[0012] Figure 5 This is a flowchart illustrating the driving method for a display panel provided in the first embodiment of this application.

[0013] Figure 6 This is a flowchart illustrating the driving method for a display panel provided in the second embodiment of this application. Detailed Implementation

[0014] Figure 1 This is a schematic diagram of an under-display camera product in related technologies. For example... Figure 1 As shown, this under-display camera product is, for example, a mobile phone. The mobile phone includes a display screen 11, which comprises a main screen area A and a secondary screen area B. The pixel aperture ratio of the main screen area A is greater than that of the secondary screen area B, resulting in higher light transmittance in the secondary screen area B compared to the main screen area A. The mobile phone also includes a camera 12, which is located on the non-display side of the secondary screen area B. Because the light transmittance of the secondary screen area B is higher than that of the main screen area A, it can be ensured that the camera 12 can capture sufficient light, thereby ensuring image capture quality.

[0015] for Figure 1 As shown in the under-display camera product, because the pixel aperture ratio of the main screen area A is greater than that of the secondary screen area B, the brightness of the main screen area A is higher than that of the secondary screen area B under the same driving voltage, resulting in a brightness difference that affects the display effect.

[0016] Therefore, the display panel, the manufacturing method thereof and the display device are provided. The adjustable resistance module is arranged in the display panel. The adjustable resistance module consumes part of the driving voltage, and then provides the sub-pixel in the secondary screen area B, so that the driving voltage obtained by the sub-pixel in the secondary screen is less than the driving voltage obtained by the sub-pixel in the primary screen. Since the light emitting device in the sub-pixel is a positive channel Metal Oxide Semiconductor (PMOS), the driving voltage V data The smaller the size is, the higher the brightness is, so that the brightness of the primary screen and the secondary screen is consistent.

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0018] Figure 2 The structural schematic diagram of the display panel provided by the first embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the display panel includes a sub-pixel array 22. The plurality of sub-pixels in the sub-pixel array 22 are arranged in rows in a first direction x and arranged in columns in a second direction y, and the first direction x and the second direction y are perpendicular. Figure 2

[0019] The sub-pixel array 22 includes a plurality of first sub-pixel columns 221 and a plurality of second sub-pixel columns 222. The aperture ratio of the sub-pixels in the first sub-pixel column 221 is greater than the aperture ratio of the sub-pixels in the second sub-pixel column 222. The plurality of first sub-pixel columns 221 and the plurality of second sub-pixel columns 222 are arranged in zones, that is, the plurality of first sub-pixel columns 221 are arranged in a first display area, and the plurality of second sub-pixel columns 222 are arranged in a second display area. The first display area and the second display area are adjacent. In this case, the non-display side of the second display area can be arranged with a camera.

[0020] For example, as shown in FIG. 2, the display panel includes a plurality of first sub-pixel columns 221 and a plurality of second sub-pixel columns 222. The plurality of first sub-pixel columns 221 are arranged in a first display area, and the plurality of second sub-pixel columns 222 are arranged in a second display area. The first display area and the second display area are adjacent. In this case, the non-display side of the second display area can be arranged with a camera. Figure 2 ​As shown, the arrangement of the sub-pixel array 22 is RGB arrangement. The plurality of first sub-pixel columns 221 includes first arrangement columns DL1 and second arrangement columns DL2, the arrangement of the sub-pixels in the first arrangement columns DL1 is for example GRBGRB....., and the arrangement of the sub-pixels in the second arrangement columns DL2 is for example BGRBGR....... The plurality of second sub-pixel columns 222 includes third arrangement columns DL3 and fourth arrangement columns DL4, the arrangement of the sub-pixels in the third arrangement columns DL3 is the same as the arrangement of the sub-pixels in the first arrangement columns DL1, and the arrangement of the sub-pixels in the fourth arrangement columns DL4 is the same as the arrangement of the sub-pixels in the second arrangement columns DL2.

[0021] The display panel 20 further includes at least one gate signal line sgn (n = 1, 2, 3,...) and at least one data signal line Vm (m = 1, 2, 3,...), a gate module 241 and an adjustable resistance module 242. At least one of the at least one gate signal line sgn (n = 1, 2, 3,...) and the at least one data signal line Vm (m = 1, 2, 3,...), the gate module 241 and the adjustable resistance module 242 can be arranged in the peripheral area of the sub-pixel array 22, for example, the frame area of the display panel.

[0022] Wherein, a predetermined number of adjacent sub-pixels in the sub-pixel array 22 constitute a pixel unit. For example, as shown in Figure 2 Each of the three adjacent sub-pixels constitutes a pixel unit, and the three sub-pixels include a red sub-pixel, a green sub-pixel and a blue sub-pixel. The number of the at least one gate signal line sgn (n = 1, 2, 3,...) depends on the number of rows occupied by the sub-pixels in the pixel unit. For example Figure 2 As shown in

[0023] The at least one data signal line Vm and the at least one gate signal line sgn are arranged in parallel. The number of the at least one data signal line Vm (m = 1, 2, 3,...) depends on the type of the color of the sub-pixels contained in the sub-pixel array 22. For example, as shown in Figure 2 The sub-pixel array 22 includes three colors of sub-pixels, and the at least one data signal line Vm (m = 1, 2, 3,...) includes three data signal lines, denoted as V1, V2 and V3.

[0024] The input end of the gate module 241 is connected with at least one gate signal line sgn (n = 1, 2, 3,...) and at least one data signal line Vm (m = 1, 2, 3,...), and the output end is connected with the plurality of first sub-pixel columns 221 and the adjustable resistance module 242.

[0025] Specifically, the gate module 241 includes a plurality of gate units, and the plurality of gate units are connected one by one with the plurality of first sub-pixel columns 221 and the plurality of second sub-pixel columns 222. For example, as shown in Figure 2 The plurality of gate units include a first gate unit 2411, a second gate unit 2412, a third gate unit 2413, and a fourth gate unit 2414. The first gate unit 2411 is connected with the first arrangement mode column DL1, the second gate unit 2412 is connected with the second arrangement mode column DL2, the third gate unit 2413 is connected with the third arrangement mode column DL3, and the fourth gate unit 2414 is connected with the fourth arrangement mode column DL4.

[0026] The circuit structures of the gate units connected by the first sub-pixel column 221 and the second sub-pixel column 222 with the same sub-pixel arrangement are the same. The same circuit structure means that the components included in the gate unit are the same, and the connection relationship between the components is the same. For example, the circuit structures of the first gate unit 2411 and the third gate unit 2413 are the same, and the circuit structures of the second gate unit 2412 and the fourth gate unit 2414 are the same.

[0027] The gate unit, for example, any one of the first gate unit 2411, the second gate unit 2412, the third gate unit 2413, and the fourth gate unit 2414 includes a plurality of transistors, and the gate of each transistor is connected with a gate signal line, the drain is connected with a data signal line, and the source is connected with a sub-pixel column. Different transistors are connected with different gate signal lines, and different transistors are connected with different data signal lines.

[0028] For example, as shown in Figure 2 The first gate unit 2411 includes a first transistor T1, a second transistor T2, and a third transistor T3. The gate of the first transistor T1 is connected with the first gate signal line sg1, the source is connected with the first arrangement mode column DL1, and the drain is connected with the first data signal line V1. The gate of the second transistor T2 is connected with the second gate signal line sg2, the source is connected with the first arrangement mode column DL1, and the drain is connected with the second data signal line V2. The gate of the third transistor T3 is connected with the third gate signal line sg3, the source is connected with the first arrangement mode column DL1, and the drain is connected with the third data signal line V3.

[0029] The second gating unit 2412 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The gate of the fourth transistor T4 is connected to the first gating signal line sg1, the source is connected to the second array DL2, and the drain is connected to the third data signal line V3. The gate of the fifth transistor T5 is connected to the second gating signal line sg2, the source is connected to the second array DL2, and the drain is connected to the first data signal line V1. The gate of the sixth transistor T6 is connected to the third gating signal line sg3, the source is connected to the second array DL2, and the drain is connected to the second data signal line V2.

[0030] The third gating unit 2413 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The gate of the seventh transistor T7 is connected to the first gating signal line sg1, its source is connected to the adjustable resistor module 242, and its drain is connected to the first data signal line V1. The gate of the eighth transistor T8 is connected to the second gating signal line sg2, its source is connected to the adjustable resistor module 242, and its drain is connected to the second data signal line V2. The gate of the ninth transistor T9 is connected to the third gating signal line sg3, its source is connected to the adjustable resistor module 242, and its drain is connected to the third data signal line V3.

[0031] The fourth selection unit 2414 includes a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The gate of the tenth transistor T10 is connected to the first selection signal line sg1, its source is connected to the adjustable resistor module 242, and its drain is connected to the third data signal line V3. The gate of the eleventh transistor T11 is connected to the second selection signal line sg2, its source is connected to the adjustable resistor module 242, and its drain is connected to the first data signal line V1. The gate of the twelfth transistor T12 is connected to the third selection signal line sg3, its source is connected to the adjustable resistor module 242, and its drain is connected to the second data signal line V2.

[0032] The output of the adjustable resistor module 242 is connected to a plurality of second sub-pixel columns 222. Specifically, the adjustable resistor module 242 includes at least one adjustable resistor group, which is connected to the plurality of second sub-pixel columns 222 in a one-to-one or one-to-many manner.

[0033] For example, such as Figure 2 As shown, the adjustable resistor module 242 includes multiple adjustable resistor groups, which are connected to multiple second sub-pixel columns 222 in a one-to-one manner. Specifically, the adjustable resistor module 242 includes a first adjustable resistor group 2421 and a second adjustable resistor group 2422. The first adjustable resistor group 2421 is connected to the third arrangement column DL3 and the third gating unit 2413, and the second adjustable resistor group 2422 is connected to the fourth arrangement column DL4 and the fourth gating unit 2414.

[0034] The first adjustable resistor group 2421 includes a first adjustable resistor R1, a second adjustable resistor R2, and a third adjustable resistor R3. The first adjustable resistor R1 is connected to the source of the seventh transistor T7 and the third arrangement column DL3, the second adjustable resistor R2 is connected to the source of the eighth transistor T8 and the third arrangement column DL3, and the third adjustable resistor R3 is connected to the source of the ninth transistor T9 and the third arrangement column DL3.

[0035] The second adjustable resistor group 2422 includes a fourth adjustable resistor R4, a fifth adjustable resistor R5, and a sixth adjustable resistor R6. The fourth adjustable resistor R4 is connected to the source of the tenth transistor T10 and the fourth arrangement column DL4, the fifth adjustable resistor R5 is connected to the source of the eleventh transistor T11 and the fourth arrangement column DL4, and the sixth adjustable resistor R6 is connected to the source of the twelfth transistor T12 and the fourth arrangement column DL4.

[0036] According to the display panel provided in any of the above embodiments, the gating module 241 is used to select one of the at least one data signal lines based on the gating signals received sequentially by at least one gating signal line, and outputs the driving voltage on the selected data signal line. The adjustable resistor module is used to step down the driving voltage and output it to multiple second sub-pixel columns. Specifically, at least one gating signal line sgn (n = 1, 2, 3...) receives the gating signal sequentially, and at least one data signal line Vm (m = 1, 2, 3...) receives at least one driving voltage respectively. At least one driving voltage corresponds one-to-one with the color of the sub-pixel in the sub-pixel array 22, that is, at least one driving voltage is used to drive sub-pixels of different colors respectively. The gating module 241 outputs at least one driving voltage sequentially column by column to the sub-pixels of corresponding colors in multiple first sub-pixel columns 221 and the adjustable resistor module 242 based on the gating signal. The adjustable resistor module 242 steps down the driving voltage and outputs it to the sub-pixels of corresponding colors in multiple second sub-pixel columns 222, that is, the adjustable resistor module 242 consumes part of the driving voltage. Since the light-emitting device in the sub-pixel is a P-type metal-oxide-semiconductor (PMOS), the lower the voltage, the higher the brightness, thus making the brightness of sub-pixels of the same color in the second sub-pixel column 222 and the first sub-pixel column 221 consistent.

[0037] Figure 2The display panel shown can also include a driving chip (not shown in the figure). The driving chip is connected with the adjustable resistance module 242. The driving chip pre-stores a corresponding relationship between driving voltage and resistance value, which is obtained by debugging the adjustable resistance module 242. The debugging process will be described in detail below. The driving chip is used to control the adjustable resistance module to adjust the resistance value according to at least one driving voltage and the corresponding relationship between the driving voltage and the resistance value, so that the luminance of the second sub-pixel column 222 and the first sub-pixel column 221 is consistent.

[0038] Figure 3 The structural schematic diagram of the display panel provided by the second embodiment of the present application is shown. The display panel provided by the second embodiment of the present application is shown in combination with Figure 3 and Figure 2 The difference between the display panel provided by the second embodiment of the present application and the display panel shown in Figure 2 is that the first arrangement mode column DL1 and the third arrangement mode column DL3 share the third gating unit 2413, thereby omitting the first gating unit 2431. The second arrangement mode column DL2 and the fourth arrangement mode column DL4 share the fourth gating unit 2414, thereby omitting the second gating unit 2412.

[0039] Specifically, the output end of the third gating unit 2413 is connected with the first adjustable resistance group 2421 in addition to the first arrangement mode column DL1. As shown in Figure 3 , the source electrode of the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 is respectively connected with the first arrangement mode column DL1. The output end of the fourth gating unit 2414 is connected with the second adjustable resistance 2412 in addition to the second arrangement mode column DL2. As shown in Figure 3 , the source electrode of the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 is respectively connected with the second arrangement mode column DL2.

[0040] According to the display panel provided by the second embodiment of the present application, compared with the display panel shown in Figure 2 , the number of gating units in the display panel shown in Figure 3 is smaller, thereby saving the occupied space, and the gating units in the display panel shown in Figure 2 are easier to wire.

[0041] Figure 4 The structural schematic diagram of the display panel provided by the third embodiment of the present application is shown. By comparing the embodiments shown in Figure 4 and Figure 2 , the difference between the display panel shown in Figure 4 and the display panel shown in Figure 2 is that, Figure 4 in the display panel shown in , at least one adjustable resistance group is connected with multiple second sub-pixel columns 222 in a one-to-many manner.

[0042] Specifically, the multiple second sub-pixel columns 222 include multiple pixel arrangement repeating units U, and the multiple pixel arrangement repeating units U include an M*N second sub-pixel array. The multiple second sub-pixel columns include multiple pixel units, and each pixel unit includes multiple sub-pixels of different colors. The value of M depends on the number of rows occupied by the multiple sub-pixels contained in the pixel unit, and N is any positive integer. The pixel arrangement repeating units U include an integer number of pixel units, and the multiple pixel arrangement repeating units U arranged sequentially can obtain a sub-pixel array with a predetermined arrangement. For example, for... Figure 4 In the RGB arrangement shown, the M*N second sub-pixel array is a 3*4 second sub-pixel array.

[0043] In an M*N second subpixel array, subpixels of the same color are connected to the same pixel circuit. Continuing the previous example, for a 3*4 second subpixel array, it includes subpixels of three colors, with four subpixels of the same color. These four subpixels of the same color are connected to the same pixel circuit; that is, the anodes of the four subpixels are each connected to the same pixel circuit. The pixel circuit can be positioned between the first and second display areas, thus avoiding affecting the light transmittance of the second display area.

[0044] In an M*N second subpixel array, subpixels of different colors are connected to multiple pixel circuits, each connected to an adjustable resistor group. Continuing the previous example, a 3*4 second subpixel array includes subpixels of three colors. Subpixels of the same color are connected to the same pixel circuit, meaning the 3*4 second subpixel array connects to three pixel circuits, and these three pixel circuits are connected to the same adjustable resistor group.

[0045] Specifically, such as Figure 4 As shown, the subpixel array includes a 6*4 subpixel array. The first display area includes four first subpixel columns 221, and the second display area includes four second subpixel columns 222. Each of the four second subpixel columns 222 includes two repeating pixel arrangement units U arranged along a first direction x.

[0046] The gating module 24 includes 5 gating units, i.e., 2 first gating units 2411, 2 second gating units 2412, and 1 third gating unit 2413. Among them, the first first gating unit 2411 is connected with the first first arrangement mode column DL1 of the first display area, and the second first gating unit 2411 is connected with the second first arrangement mode column DL1 of the first display area. The first second gating unit 2412 is connected with the first second arrangement mode column DL2 of the first display area, and the second second gating unit 2412 is connected with the second second arrangement mode column DL2 of the first display area. The third gating unit 2413 is connected with one adjustable resistance group 2421, and the adjustable resistance group 2421 is connected with two pixel arrangement repeating units U. Specifically, the two pixel arrangement repeating units U are linearly arranged along the first direction x, and the two pixel arrangement repeating units U include two third arrangement mode columns DL3, and the adjustable resistance group 2412 is connected with one of the two third arrangement mode columns DL3.

[0047] It should be noted that, as shown in Figure 4 In the repeating unit composed of 3 rows * (4 columns of first sub-pixel columns 221 + 4 rows of second sub-pixel columns 222), 2 first gating units 2411, 2 second gating units 2412, and 1 third gating unit 2413 need to be correspondingly arranged. Among them, in the first direction x, with the increase of one pixel arrangement repeating unit U, one third gating unit 2413 is correspondingly added. In the first direction x, with the increase of one first arrangement mode column DL1, one first gating unit 2411 is correspondingly added. In the first direction x, with the increase of one second arrangement mode column DL2, one second gating unit 2412 is correspondingly added.

[0048] According to the display panel provided by the embodiment of the present application, and Figure 2 Compared with the display panel shown in the figure, the number of gating units and adjustable resistance units is saved, the circuit complexity is reduced, and the occupied space is saved.

[0049] Figure 5 The flowchart of the driving method of the display panel provided by the first embodiment of the present application is shown. The driving method can be used in the debugging process of the adjustable resistance module in the display panel provided by any of the above embodiments. As shown in Figure 5 The driving method 500 includes:

[0050] In step S510, the gray scale voltage signal of the image frame to be displayed and the gate signal are obtained, and the timing of the gate signal and the row scanning signal of the sub-pixel array is the same.

[0051] In step S520, the driving voltage of each color sub-pixel in the gray scale voltage signal is provided to at least one data signal line.

[0052] Step S530, the gate signal is provided to at least one gate signal line in sequence, so that the display panel displays the image frame to be displayed.

[0053] Step S540, the luminance difference between the first display area and the second display area is obtained.

[0054] Step S550, the resistance value of the adjustable resistance module is adjusted based on the luminance difference, so that the luminance of the first display area and the second display area is the same.

[0055] Next, the driving method 500 is specifically described by taking the display panel shown in the figure as an example. Figure 2

[0056] Taking the green sub-pixel as an example, the adjustment principle of the adjustable resistance module 242 is as follows.

[0057] (1) The main screen area and the auxiliary screen area are driven to display green pictures at the same time according to the conventional driving method.

[0058] (2) The photoelectric probe is used to detect the first luminance value LA of the main screen area and the second luminance value LB of the auxiliary screen area respectively, and the light-emitting current value IA of the second luminance value LB and the light-emitting current value IB of the auxiliary screen area are obtained.

[0059] (3) Since the data voltages for driving the main screen area and the auxiliary screen area are equal, the main screen area and the auxiliary screen area have the following corresponding relationship: IA*RA=IB*RB=Vdata (Formula One). Wherein, RA represents the total power consumption resistance in the display process (1), RB represents the total power consumption resistance in the display process (2), and Vdata represents the data voltage.

[0060] (4) The light-emitting time, frame period and light-emitting efficiency of the main screen area and the auxiliary screen area are the same. Since the luminance is proportional to the average current in a frame * light-emitting efficiency * aperture ratio, and the average current in a frame * light-emitting efficiency * aperture ratio = light-emitting stage current × light-emitting time / frame period × light-emitting efficiency * aperture ratio. Therefore, the luminance LA of the display process (1) and the luminance LB of the display process (2) have the following corresponding relationship: LA:LB=(IA*KA):(IB*KB) (Formula Two). Wherein, KA represents the aperture ratio of the sub-pixel in the first sub-pixel column 221, and KB represents the aperture ratio of the sub-pixel in the second sub-pixel column 222.

[0061] (5) Combining Formula One and Formula Two, we can get: LA:LB=(RB*KA):(RA*KB).

[0062] In this case, in order to make LA and LB consistent during actual luminance adjustment, it is necessary to make RB*KA and RA*KB equal. After the display panel is produced, KA and KB are fixed values. From the perspective of production, it is impossible to change the values of KA and KB. Therefore, in order to make LA and LB consistent, it is necessary to make the resistance value of the adjustable resistance module 242 equal to the resistance value of the main screen area and the resistance value of the auxiliary screen area. Figure 2 ​It can be seen from the circuit diagram that by adjusting the resistance values of the second adjustable resistor R2 and the fifth adjustable resistor R5, the adjustment of the RB can be realized, so that the brightness of the green sub-pixels of the main screen area and the auxiliary screen area is consistent. It should be noted that as long as the combination of the resistance values of the second adjustable resistor R2 and the fifth adjustable resistor R5 can satisfy the formula given in step (5), there is no fixed relationship constraint between the second adjustable resistor R2 and the fifth adjustable resistor R5.

[0063] It can be seen from the above debugging principle of the green sub-pixel that by adjusting the resistance values of the first adjustable resistor R1 and the sixth adjustable resistor R6, the brightness consistency of the red sub-pixel of the main screen and the auxiliary screen can be realized. By adjusting the resistance values of the third adjustable resistor R3 and the fourth adjustable resistor R4, the brightness consistency of the blue sub-pixel of the main screen and the auxiliary screen can be realized.

[0064] The debugging process of the green sub-pixel includes:

[0065] According to step S510, the gray scale voltage signal and the gate signal of the green image frame to be displayed are obtained. The gray scale voltage signal includes the driving voltage corresponding to each color sub-pixel. Among them, the first driving voltage v1 of the green sub-pixel is the gray scale voltage corresponding to the green pixel gray scale binding point, and the gray scale voltage is selected from any one of the high voltage end voltage VGMP when displaying a black picture and the low voltage end voltage VGSP when displaying a white picture W255. When it is necessary to display a green picture, the second driving voltage v2 of the red sub-pixel and the third driving voltage v3 of the blue sub-pixel are both high voltage end voltage VGMP, so that the sub-pixel obtaining the high voltage end voltage VGMP is not lit. The timing of the gate signal and the row scanning signal of the sub-pixel array is the same.

[0066] According to step S520, the first driving voltage v1 is provided to the first data signal line V1, the second driving voltage v2 is provided to the second data signal line V2, and the third driving voltage v3 is provided to the third data signal line V3.

[0067] According to step S530, when the gate signal scans to the first gate signal line Sg1, so that the first gate signal line sg1 is low, the first row is scanned, and the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the tenth transistor T10 are turned on. The first driving voltage v1 reaches the first arrangement mode column DL1 and the third arrangement mode column DL3 through the first transistor T1 and the seventh transistor T7, respectively. The third driving voltage v3 reaches the second arrangement mode column DL2 and the fourth arrangement mode column DL4 through the fourth transistor T4 and the tenth transistor T10, respectively. The second arrangement mode column DL2 and the fourth arrangement mode column DL4 obtain the third driving voltage v3 as the high voltage end voltage VGMP, so that the blue sub-pixel is not lit. The green sub-pixel receiving only the first driving voltage v1 is lit when the first row is lit.

[0068] When the selection signal scans to the second selection signal line Sg2, so that the second selection signal line Sg2 is low, the second row is scanned, and the transistors T2, T5, T8, and T11 are turned on. The second driving voltage v2 reaches the first arrangement column DL1 and the third arrangement column DL3 through the transistors T2 and T8, respectively. The first driving voltage v1 reaches the second arrangement column DL2 and the fourth arrangement column DL4 through the transistors T5 and T11, respectively. The first arrangement column DL1 and the third arrangement column DL3 are high voltage VGMP due to the second driving voltage v2, so the red sub-pixels are not lit. The green sub-pixels receiving only the first driving voltage v1 are lit when the second row is lit.

[0069] When the selection signal scans to the third selection signal line Sg3, so that the third selection signal line Sg3 is low, the third row is scanned, and the transistors T3, T6, T9, and T12 are turned on. The third driving voltage v3 reaches the first arrangement column DL1 and the third arrangement column DL3 through the transistors T3 and T9, respectively. The second driving voltage v2 reaches the second arrangement column DL2 and the fourth arrangement column DL4 through the transistors T6 and T12, respectively. The first arrangement column DL1 and the third arrangement column DL3 are high voltage VGMP due to the third driving voltage v3, so the blue sub-pixels are not lit. The second arrangement column DL2 and the fourth arrangement column DL4 are high voltage VGMP due to the second driving voltage v2, so the red sub-pixels are not lit, so the third row is not lit as a whole.

[0070] When the selection signal scans to the fourth row, the signal transmission process of the first row sub-pixels is repeated; when the selection signal scans to the fifth row, the signal transmission process of the second row sub-pixels is repeated; when the selection signal scans to the sixth row, the signal transmission process of the third row sub-pixels is repeated, and so on, so that all the green sub-pixels on the screen are lit in a frame time.

[0071] According to step S540, the luminance LA of the first display area and the luminance LB of the second display area are detected by the photoelectric probe.

[0072] According to step S550, LA = LB by adjusting the resistance values of the second adjustable resistor R2 and the fifth adjustable resistor R5. The gray scale voltage of the green sub-pixel, the resistance value of the second adjustable resistor R2, and the resistance value of the fifth adjustable resistor R5 at this time are recorded.

[0073] The preset multiple green binding point gray scales are subjected to the above process respectively to obtain the corresponding relationship of the driving voltage, the resistance value of the second adjustable resistor R2 and the resistance value of the fifth adjustable resistor R5 corresponding to each green binding point gray scale. Then, the corresponding relationship of the gray scale-second adjustable resistor R2 resistance value-fifth adjustable resistor R5 resistance value corresponding to the green sub-pixel is obtained by interpolation method. Subsequently, the resistance value of the adjustable resistor module 242 is set by using the corresponding relationship, so that the brightness of the green sub-pixel on the entire screen body can be consistent.

[0074] The debugging process of the red sub-pixel includes:

[0075] According to step S510, the gray scale voltage signal of the red image frame to be displayed and the gate signal are obtained. The gray scale voltage signal includes the driving voltage corresponding to each color sub-pixel. Among them, the second driving voltage v2 of the red sub-pixel is the gray scale voltage corresponding to the red pixel gray scale binding point, and the selection range of the gray scale voltage is any one of the high voltage end voltage VGMP when displaying a black picture and the low voltage end voltage VGSP when displaying a white picture W255. When the red picture needs to be displayed, the first driving voltage v1 of the green sub-pixel and the third driving voltage v3 of the blue sub-pixel are both high voltage end voltage VGMP, so that the sub-pixel obtaining the high voltage end voltage VGMP is not lit. The timing of the gate signal and the row scanning signal of the sub-pixel array is the same.

[0076] According to step S520, the first driving voltage v1 is provided to the first data signal line V1, the second driving voltage v2 is provided to the second data signal line V2, and the third driving voltage v3 is provided to the third data signal line V3.

[0077] According to step S530, when the gate signal scans to the first gate signal line Sg1, so that the first gate signal line sg1 is low, the first row is scanned, and the first transistor T1, the fourth transistor T4, the seventh transistor T7 and the tenth transistor T10 are turned on. The first driving voltage v1 reaches the first arrangement mode column DL1 and the third arrangement mode column DL3 through the first transistor T1 and the seventh transistor T7 respectively. The third driving voltage v3 reaches the second arrangement mode column DL2 and the fourth arrangement mode column DL4 through the fourth transistor T4 and the tenth transistor T10 respectively. The first arrangement mode column DL1 and the third arrangement mode column DL3 do not light up the green sub-pixel because the obtained first driving voltage v1 is the high voltage end voltage VGMP. The second arrangement mode column DL2 and the fourth arrangement mode column DL4 do not light up the blue sub-pixel because the obtained third driving voltage v3 is the high voltage end voltage VGMP.

[0078] When the selected signal scans to the second selected signal line Sg2, so that the second selected signal line Sg2 is low, the second row is scanned, and the transistors T2, T5, T8 and T11 are turned on. The second driving voltage v2 reaches the first arrangement column DL1 and the third arrangement column DL3 through the transistors T2 and T8 respectively. The first driving voltage v1 reaches the second arrangement column DL2 and the fourth arrangement column DL4 through the transistors T5 and T11 respectively. The first arrangement column DL1 and the third arrangement column DL3 are lit by the second driving voltage v2. The second arrangement column DL2 and the fourth arrangement column DL4 are not lit because the first driving voltage v1 is the high voltage VGMP.

[0079] When the selected signal scans to the third selected signal line Sg3, so that the third selected signal line Sg3 is low, the third row is scanned, and the transistors T3, T6, T9 and T12 are turned on. The third driving voltage v3 reaches the first arrangement column DL1 and the third arrangement column DL3 through the transistors T3 and T9 respectively. The second driving voltage v2 reaches the second arrangement column DL2 and the fourth arrangement column DL4 through the transistors T6 and T12 respectively. The first arrangement column DL1 and the third arrangement column DL3 are not lit because the third driving voltage v3 is the high voltage VGMP. The second arrangement column DL2 and the fourth arrangement column DL4 are lit by the second driving voltage v2.

[0080] When the selected signal scans to the fourth row, the signal transmission process of the first row sub-pixel is repeated; when the selected signal scans to the fifth row, the signal transmission process of the second row sub-pixel is repeated; when the selected signal scans to the sixth row, the signal transmission process of the third row sub-pixel is repeated, and so on, so that all the red sub-pixels on the screen are lit in a frame time.

[0081] According to step S540, the luminance LA of the first display area and the luminance LB of the second display area are detected by the photoelectric probe.

[0082] According to step S550, LA=LB by adjusting the resistance values of the first adjustable resistor R1 and the sixth adjustable resistor R6. The gray scale voltage of the red sub-pixel, the resistance value of the first adjustable resistor R1 and the resistance value of the sixth adjustable resistor R6 at this time are recorded.

[0083] A plurality of red binding point gray scales are preset, and the above process is performed for all the red binding point gray scales to obtain a corresponding relationship of the driving voltage, the resistance value of the first adjustable resistor R1, and the resistance value of the sixth adjustable resistor R6 corresponding to each red binding point gray scale. Then, the corresponding relationship of the gray scale, the resistance value of the first adjustable resistor R1, and the resistance value of the sixth adjustable resistor R6 corresponding to the red sub-pixel is obtained by interpolation. Subsequently, the resistance value of the adjustable resistor module 242 is set by using the corresponding relationship, so that the brightness of the red sub-pixel on the entire screen body can be consistent.

[0084] The debugging process of the blue sub-pixel includes:

[0085] According to step S510, the gray scale voltage signal of the blue image frame to be displayed and the gate signal are obtained. The gray scale voltage signal includes the driving voltage corresponding to each color sub-pixel. The third driving voltage v3 of the blue sub-pixel is the gray scale voltage corresponding to the blue pixel gray scale binding point, and the selection range of the gray scale voltage is any one of the high voltage end voltage VGMP when displaying a black picture and the low voltage end voltage VGSP when displaying a white picture W255. When a blue picture needs to be displayed, the second driving voltage v2 of the red sub-pixel and the first driving voltage v1 of the green sub-pixel are both the high voltage end voltage VGMP, so that the sub-pixel obtaining the high voltage end voltage VGMP is not lit. The timing of the gate signal is the same as that of the row scanning signal of the sub-pixel array.

[0086] According to step S520, the first driving voltage v1 is provided to the first data signal line V1, the second driving voltage v2 is provided to the second data signal line V2, and the third driving voltage v3 is provided to the third data signal line V3.

[0087] According to step S530, when the gate signal scans to the first gate signal line Sg1, so that the first gate signal line sg1 is low, the first row is scanned, and the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the tenth transistor T10 are turned on. The first driving voltage v1 reaches the first arrangement mode column DL1 and the third arrangement mode column DL3 through the first transistor T1 and the seventh transistor T7, respectively. The third driving voltage v3 reaches the second arrangement mode column DL2 and the fourth arrangement mode column DL4 through the fourth transistor T4 and the tenth transistor T10, respectively. The first arrangement mode column DL1 and the third arrangement mode column DL3 do not light up the green sub-pixel because the obtained first driving voltage v1 is the high voltage end voltage VGMP. The second arrangement mode column DL2 and the fourth arrangement mode column DL4 light up the blue sub-pixel because of the obtained third driving voltage v3.

[0088] When the selection signal scans to the second selection signal line Sg2, so that the second selection signal line Sg2 is low, the second row is scanned, and the transistors T2, T5, T8 and T11 are turned on. The second driving voltage v2 reaches the first arrangement column DL1 and the third arrangement column DL3 through the transistors T2 and T8 respectively. The first driving voltage v1 reaches the second arrangement column DL2 and the fourth arrangement column DL4 through the transistors T5 and T11 respectively. The first arrangement column DL1 and the third arrangement column DL3 are high voltage VGMP due to the second driving voltage v2, so the red sub-pixel is not bright. The second arrangement column DL2 and the fourth arrangement column DL4 are high voltage VGMP due to the first driving voltage v1, so the green sub-pixel is not bright.

[0089] When the selection signal scans to the third selection signal line Sg3, so that the third selection signal line Sg3 is low, the third row is scanned, and the transistors T3, T6, T9 and T12 are turned on. The third driving voltage v3 reaches the first arrangement column DL1 and the third arrangement column DL3 through the transistors T3 and T9 respectively. The second driving voltage v2 reaches the second arrangement column DL2 and the fourth arrangement column DL4 through the transistors T6 and T12 respectively. The first arrangement column DL1 and the third arrangement column DL3 are blue sub-pixel due to the third driving voltage v3. The second arrangement column DL2 and the fourth arrangement column DL4 are high voltage VGMP due to the second driving voltage v2, so the red sub-pixel is not bright.

[0090] When the selection signal scans to the fourth row, the signal transmission process of the first row sub-pixel is repeated; when the selection signal scans to the fifth row, the signal transmission process of the second row sub-pixel is repeated; when the selection signal scans to the sixth row, the signal transmission process of the third row sub-pixel is repeated, and so on, so that all the blue sub-pixels on the screen are bright in a frame time.

[0091] According to step S540, the luminance LA of the first display area and the luminance LB of the second display area are detected by the photoelectric probe.

[0092] According to step S550, LA=LB by adjusting the resistance values of the second adjustable resistor R2 and the fifth adjustable resistor R5. The gray scale voltage of the blue sub-pixel, the resistance values of the third adjustable resistor R3 and the fourth adjustable resistor R4 at this time are recorded.

[0093] Multiple blue bound point grayscale values ​​are preset. The above process is performed on all blue bound point grayscale values ​​to obtain the corresponding driving voltage, resistance value of the third adjustable resistor R3, and resistance value of the fourth adjustable resistor R4 for each blue bound point grayscale value. Then, the correspondence between the grayscale value of the blue sub-pixel and the resistance values ​​of the third adjustable resistor R3 and the fourth adjustable resistor R4 is obtained through interpolation. Subsequently, using this correspondence, the resistance value of the adjustable resistor module 242 can be set to achieve consistent brightness of the blue sub-pixels across the entire screen.

[0094] for Figure 4 Regarding the display panel shown, based on the above... Figure 2 Based on the same debugging principle as the display panel shown, adjusting the value of the first adjustable resistor R1 can adjust the brightness of the green sub-pixels to make the brightness of the green sub-pixels in the main screen area and the sub-screen area consistent. Adjusting the value of the second adjustable resistor R2 can adjust the brightness of the red sub-pixels to make the brightness of the red sub-pixels in the main screen area and the sub-screen area consistent. Adjusting the value of the third adjustable resistor R3 can adjust the brightness of the blue sub-pixels to make the brightness of the blue sub-pixels in the main screen area and the sub-screen area consistent.

[0095] Based on the above debugging principles, Figure 5 The driving method shown is used for Figure 4 When the display panel is shown, the specific execution process and Figure 5 The driving method shown is used for Figure 2 The difference in the display panel shown lies in steps S530-S550.

[0096] For the debugging process of the green sub-pixel, step S530 specifically includes:

[0097] When the strobe signal scans to the first strobe signal line Sg1, causing sg1 to be at a low level, the first row is scanned, and the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned on. The first driving voltage v1 reaches the two first arrangement columns DL1 in the main screen area and the one third arrangement column DL3 in the sub-screen area through the first transistor T1 and the seventh transistor T7, respectively. The third driving voltage v3 reaches the two second arrangement columns DL2 in the main screen area through the fourth transistor T4. Since the first driving voltage v1 is any voltage value between the high voltage VGMP and the low voltage VGSP, the green sub-pixels in the main screen area that receive the first driving voltage v1 are lit. The pixel circuit in the sub-screen area that connects to the four green sub-pixels receives the first driving voltage v1, and this green pixel circuit simultaneously drives the four green sub-pixels, so the green sub-pixels in the first row and the green sub-pixels in the second row of the sub-screen area are lit simultaneously. The third driving voltage v3 is the high voltage VGMP, so the blue sub-pixels in the main screen area that receive the third driving voltage v3 are not lit.

[0098] When the selection signal scans to the second selection signal line Sg2, so that the second selection signal line Sg2 is low, the second row is scanned, and the transistor T2, the transistor T5 and the transistor T8 are turned on. The second driving voltage v2 reaches the first arrangement column DL1 and the third arrangement column DL3 through the transistor T2 and the transistor T8 respectively. The first driving voltage v1 reaches the second arrangement column DL2 through the transistor T5. Since the second driving voltage v2 is the high voltage terminal voltage VGMP, the red sub-pixel of the main screen area which obtains the second driving voltage v2 is not lightened, and the pixel circuit which connects four red sub-pixels of the auxiliary screen area obtains the second driving voltage v2, so that the red sub-pixel of the auxiliary screen area is not lightened. Since the first driving voltage v1 is any voltage value between the high voltage terminal voltage VGMP and the low voltage terminal voltage VGSP, the green sub-pixel of the main screen area which obtains the first driving voltage v1 is lightened.

[0099] When the selection signal scans to the third selection signal line Sg3, so that the third selection signal line Sg3 is low, the third row is scanned, and the transistor T3, the transistor T6 and the transistor T9 are turned on. The third driving voltage v3 reaches the first arrangement column DL1 and the third arrangement column DL3 through the transistor T3 and the transistor T9 respectively. The second driving voltage v2 reaches the second arrangement column DL2 through the transistor T6. Since the third driving voltage v3 is the high voltage terminal voltage VGMP, the blue sub-pixel of the main screen area which obtains the third driving voltage v3 is not lightened, and the pixel circuit which connects four blue sub-pixels of the auxiliary screen area obtains the third driving voltage v3, so that the four blue sub-pixels are not lightened. Since the second driving voltage v2 is also the high voltage terminal voltage VGMP, the red sub-pixel of the main screen area which obtains the second driving voltage v2 is not lightened.

[0100] When the selection signal scans to the fourth row, the signal transmission process of the first row sub-pixel is repeated; when the selection signal scans to the fifth row, the signal transmission process of the second row sub-pixel is repeated; when the selection signal scans to the sixth row, the signal transmission process of the third row sub-pixel is repeated, and so on, so that all the green sub-pixels on the screen body are lightened in a frame time.

[0101] According to step S540, the luminance LA of the first display area and the luminance LB of the second display area are detected by using the photoelectric probe.

[0102] According to step S550, the LA=LB is realized by adjusting the resistance value of the first adjustable resistor R1. The gray scale voltage of the green sub-pixel and the resistance value of the first adjustable resistor R1 at this time are recorded.

[0103] The preset multiple green binding point gray scales are respectively executed with the above process to obtain the corresponding relationship of the driving voltage and the resistance value of the first adjustable resistor R1 corresponding to each green binding point gray scale. Further, the corresponding relationship of the gray scale and the resistance value of the first adjustable resistor R1 corresponding to the green sub-pixel is obtained by interpolation method. Subsequently, the resistance value of the adjustable resistor module 242 is set by using the corresponding relationship, so that the brightness of the green sub-pixel on the entire screen body can be consistent.

[0104] For the debugging process of the red sub-pixel, step S530 specifically includes:

[0105] When the selection signal scans to the first selection signal line Sg1, so that the first selection signal line Sg1 is low, the first row is scanned, and the first transistor T1, the fourth transistor T4 and the seventh transistor T7 are turned on. The first driving voltage v1 reaches the first arrangement mode column DL1 and the third arrangement mode column DL3 through the first transistor T1 and the seventh transistor T7, respectively. The third driving voltage v3 reaches the second arrangement mode column DL2 through the fourth transistor T4. Since the first driving voltage v1 is the high voltage end voltage VGMP, the green sub-pixel of the main screen area obtaining the first driving voltage v1 is not bright, and the pixel point circuit of the four green sub-pixels connected by the auxiliary screen area obtains the first driving voltage v1, and the four green sub-pixels are not bright. Since the third driving voltage v3 is the high voltage end voltage VGMP, the blue sub-pixel of the main screen area obtaining the third driving voltage v3 is not bright.

[0106] When the selection signal scans to the second selection signal line Sg2, so that the second selection signal line Sg2 is low, the second row is scanned, and the transistor T2, the transistor T5 and the transistor T8 are turned on. The second driving voltage v2 reaches the first arrangement mode column DL1 and the third arrangement mode column DL3 through the transistor T2 and the transistor T8, respectively. The first driving voltage v1 reaches the second arrangement mode column DL2 through the transistor T5. Since the second driving voltage v2 is any voltage value between the high voltage end voltage VGMP and the low voltage end voltage VGSP, the red sub-pixel of the main screen area obtaining the second driving voltage v2 is bright, and the pixel circuit of the four red sub-pixels connected by the auxiliary screen area obtains the second driving voltage v2, and the four red sub-pixels are bright. Since the first driving voltage v1 is the high voltage end voltage VGMP, the green sub-pixel of the main screen area obtaining the first driving voltage v1 is not bright.

[0107] When the selected signal scans to the third selected signal line Sg3, so that the third selected signal line Sg3 is low, the third row is scanned, and the transistor T3, the transistor T6 and the transistor T9 are turned on. The third driving voltage v3 reaches the first arrangement column DL1 and the third arrangement column DL3 through the transistor T3 and the transistor T9 respectively. The second driving voltage v2 reaches the second arrangement column DL2 through the transistor T6. Since the third driving voltage v3 is the high voltage terminal voltage VGMP, the blue sub-pixel of the main screen area which obtains the third driving voltage v3 is not bright, and the pixel circuit connected with four blue sub-pixels of the auxiliary screen area obtains the third driving voltage v3, and the four blue sub-pixels are not bright. Since the second driving voltage v2 is any voltage value between the high voltage terminal voltage VGMP and the low voltage terminal voltage VGSP, the red sub-pixel of the main screen area which obtains the second driving voltage v2 is bright.

[0108] When the selected signal scans to the fourth row, the signal transmission process of the first row sub-pixel is repeated; when the selected signal scans to the fifth row, the signal transmission process of the second row sub-pixel is repeated; when the selected signal scans to the sixth row, the signal transmission process of the third row sub-pixel is repeated, and so on, so that all the red sub-pixels on the screen body are bright in a frame time.

[0109] According to step S540, the luminance LA of the first display area and the luminance LB of the second display area are detected by using the photoelectric probe.

[0110] According to step S550, LA=LB is achieved by adjusting the resistance value of the second adjustable resistor R2. The gray scale voltage of the red sub-pixel and the resistance value of the second adjustable resistor R2 at this time are recorded.

[0111] A plurality of red binding point gray scales are preset, and the above process is performed for all the red binding point gray scales to obtain the corresponding relationship between the driving voltage corresponding to each red binding point gray scale and the resistance value of the second adjustable resistor R2. Further, the corresponding relationship between the gray scale corresponding to the red sub-pixel and the resistance value of the second adjustable resistor R2 is obtained by interpolation method. Subsequently, the resistance value of the adjustable resistor module 242 is set by using the corresponding relationship, so that the luminance of the red sub-pixel on the entire screen body is consistent.

[0112] For the debugging process of the blue sub-pixel, step S530 specifically includes:

[0113] When the selection signal scans to the first selection signal line Sgl, the first selection signal line Sgl is low, the first row is scanned, the first transistor Tl, the fourth transistor T4 and the seventh transistor T7 are turned on. The first drive voltage vl reaches the first arrangement column DLl and the third arrangement column DL3 through the first transistor Tl and the seventh transistor T7 respectively. The third drive voltage v3 reaches the second arrangement column DL2 through the fourth transistor T4. Since the first drive voltage vl is the high voltage terminal voltage VGMP, the green sub-pixel of the main screen area which obtains the first drive voltage vl is not bright, the pixel circuit connected with four green sub-pixels of the auxiliary screen area obtains the first drive voltage vl, and the four green sub-pixels are not bright. Since the third drive voltage v3 is any voltage value between the high voltage terminal voltage VGMP and the low voltage terminal voltage VGSP, the blue sub-pixel of the main screen area which obtains the third drive voltage v3 is bright.

[0114] When the selection signal scans to the second selection signal line Sg2, the second selection signal line Sg2 is low, the second row is scanned, the transistor T2, the transistor T5 and the transistor T8 are turned on. The second drive voltage v2 reaches the first arrangement column DLl and the third arrangement column DL3 through the transistor T2 and the transistor T8 respectively. The first drive voltage vl reaches the second arrangement column DL2 through the transistor T5. Since the second drive voltage v2 is the high voltage terminal voltage VGMP, the red sub-pixel of the main screen area which obtains the second drive voltage v2 is not bright, the pixel circuit connected with four red sub-pixels of the auxiliary screen area obtains the second drive voltage v2, and the four red sub-pixels are not bright. Since the first drive voltage vl is the high voltage terminal voltage VGMP, the green sub-pixel of the main screen area which obtains the first drive voltage vl is not bright.

[0115] When the selection signal scans to the third selection signal line Sg3, the third selection signal line Sg3 is low, the third row is scanned, the transistor T3, the transistor T6 and the transistor T9 are turned on. The third drive voltage v3 reaches the first arrangement column DLl and the third arrangement column DL3 through the transistor T3 and the transistor T9 respectively. The second drive voltage v2 reaches the second arrangement column DL2 through the transistor T6. Since the third drive voltage v3 is any voltage value between the high voltage terminal voltage VGMP and the low voltage terminal voltage VGSP, the blue sub-pixel of the main screen area which obtains the third drive voltage v3 is bright, the pixel circuit connected with four blue sub-pixels of the auxiliary screen area obtains the third drive voltage v3, and the four blue sub-pixels are bright. Since the second drive voltage v2 is the high voltage terminal voltage VGMP, the red sub-pixel of the main screen area which obtains the second drive voltage v2 is not bright.

[0116] When the strobe signal scans to the fourth row, the signal transmission process of the first row of sub-pixels is repeated; when the strobe signal scans to the fifth row, the signal transmission process of the second row of sub-pixels is repeated; when the strobe signal scans to the sixth row, the signal transmission process of the third row of sub-pixels is repeated, and so on, so that all blue sub-pixels on the screen are lit up within one frame.

[0117] According to step S540, the brightness LA of the first display area and the brightness LB of the second display area are detected using a photoelectric probe.

[0118] According to step 550, adjust the value of the third adjustable resistor R3 until LA = LB. Record the grayscale voltage of the blue sub-pixel and the value of the third adjustable resistor R3 at this point.

[0119] Multiple blue bound point grayscale levels are preset. The above process is performed on all blue bound point grayscale levels to obtain the correspondence between the driving voltage and the resistance value of the third adjustable resistor R3 for each blue bound point grayscale level. Then, the correspondence between the grayscale level of the blue sub-pixel and the resistance value of the third adjustable resistor R3 is obtained by interpolation. Subsequently, using this correspondence, the resistance value of the adjustable resistor module 242 is set, so that the brightness of the blue sub-pixels on the entire screen can be made consistent.

[0120] Figure 6 This is a flowchart illustrating the driving method for a display panel provided in the second embodiment of this application. This driving method can be used in the display driving process of the display panel provided in any of the above embodiments. The driving chip pre-stores the correspondence between the driving voltage and the resistance value of the adjustable resistor module. Figure 2 Taking the display panel shown as an example, the correspondence between the driving voltage and the resistance values ​​of the adjustable resistor modules includes, for example, the correspondence between the grayscale corresponding to the green sub-pixel, the resistance value of the second adjustable resistor R2, and the resistance value of the fifth adjustable resistor R5; the correspondence between the grayscale corresponding to the red sub-pixel, the resistance value of the first adjustable resistor R1, and the resistance value of the sixth adjustable resistor R6; and the correspondence between the grayscale corresponding to the blue sub-pixel, the resistance value of the third adjustable resistor R3, and the resistance value of the fourth adjustable resistor R4. Figure 6 As shown, the driving method 600 includes:

[0121] Step S510: Obtain the grayscale voltage signal and gating signal of the image frame to be displayed. The timing of the gating signal and the row scanning signal of the sub-pixel array are the same.

[0122] Step S610: Based on the correspondence between driving voltage and resistance value, determine the resistance value of the adjustable resistor module corresponding to the driving voltage.

[0123] Specifically, the driving voltage of each color sub-pixel is matched with the pre-stored grayscale and the resistance value of the adjustable resistor module to obtain the resistance value of the adjustable resistor module corresponding to each color sub-pixel.

[0124] In step S620, the adjustable resistance module is controlled to match the resistance value. The adjustable resistance in the adjustable resistance module is, for example, a precision adjustable resistance. The driving chip line precision adjustable resistance sends a resistance adjustment signal, so that the resistance value can be adjusted to a preset value.

[0125] In step S520, the driving voltages of the sub-pixels of different colors are respectively provided to the at least one data signal line.

[0126] In step S530, the gate signals are sequentially provided to the at least one gate signal line, so that the display panel displays the to-be-displayed image frame.

[0127] The embodiments of the present application also provide a display device, which comprises the display panel provided by any of the above embodiments.

[0128] The above description has been given for the purpose of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although a plurality of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A display panel, characterized by, The display panel has a first display area and a second display area, and includes a sub-pixel array, the sub-pixel array includes a plurality of first sub-pixel columns in the first display area and a plurality of second sub-pixel columns in the second display area, the aperture ratio of the sub-pixels in the first sub-pixel columns is greater than the aperture ratio of the sub-pixels in the second sub-pixel columns; The display panel further includes: at least one selection signal line; at least one data signal line; a selection module, the input end of the selection module is connected with the at least one selection signal line and the at least one data signal line, and the output end of the selection module is connected with the plurality of first sub-pixel columns and an adjustable resistance module; and the adjustable resistance module, the output end of the adjustable resistance module is connected with the plurality of second sub-pixel columns, the adjustable resistance module includes at least one adjustable resistance group, the number of the adjustable resistance module is a plurality, a plurality of the adjustable resistance groups are connected with the plurality of second sub-pixel columns in a one-to-one correspondence, or the at least one adjustable resistance group is connected with the plurality of second sub-pixel columns in a one-to-many manner; a driving chip, and the driving chip is connected with the adjustable resistance module, the driving chip pre-stores a corresponding relationship between a driving voltage and a resistance value, and the driving chip is used for controlling the adjustable resistance module to adjust the resistance value according to at least one driving voltage and the corresponding relationship, so that the luminance of the second sub-pixel column is consistent with the luminance of the first sub-pixel column; wherein, the selection module is used for selecting one data signal line in the at least one data signal line based on the selection signal received by the at least one selection signal line in sequence, and outputting the driving voltage on the selected data signal line, and the adjustable resistance module is used for outputting the driving voltage after voltage reduction to the plurality of second sub-pixel columns. The selection module includes a plurality of selection units; part of the selection units are connected with the plurality of first sub-pixel columns in a one-to-one correspondence, and the remaining part of the selection units are connected with the at least one adjustable resistance group in a one-to-one correspondence.

2. The display panel of claim 1, wherein, The circuit structures of the selection units corresponding to the first sub-pixel columns and the second sub-pixel columns are the same.

3. The display panel of claim 2, wherein, When the at least one adjustable resistance group is connected with the plurality of second sub-pixel columns in a one-to-many manner, the plurality of second sub-pixel columns include a plurality of pixel arrangement repeating units, the plurality of pixel arrangement repeating units include an M*N second sub-pixel array, the sub-pixels of the same color in the M*N second sub-pixel array are connected with the same pixel circuit, and the sub-pixels of different colors are connected with a plurality of pixel circuits, and each of the plurality of pixel circuits is connected with one adjustable resistance group.

4. The display panel of claim 2, wherein, Wherein, the plurality of second sub-pixel columns include a plurality of pixel units, the pixel units include a plurality of sub-pixels of different colors; the value of M depends on the number of rows occupied by the plurality of sub-pixels included in the pixel unit, and N is any positive integer. The selection unit includes a plurality of transistors, the gate of each transistor is connected with a selection signal line, and the drain is connected with a data signal line; different selection signal lines are connected with different transistors, and different data signal lines are connected with different transistors.

5. The display panel of any of claims 2-4, wherein, The adjustable resistance group includes a plurality of adjustable resistors, and each adjustable resistor is connected with the source or drain of one transistor.

6. The display panel of claim 5, wherein, ​ 7. The display panel of any one of claims 1-4, wherein, The corresponding relationship between the driving voltage and the resistance value is obtained by debugging the adjustable resistance module.

8. A driving method of a display panel, characterized by, The driving method comprises: obtaining a gray scale voltage signal and a gate signal of an image frame to be displayed, the timing of the gate signal being the same as that of a row scanning signal of the sub-pixel array; providing the driving voltage of each color sub-pixel in the gray scale voltage signal to the at least one data signal line respectively; providing the gate signal to the at least one gate signal line in sequence, so that the display panel displays the image frame to be displayed.

9. The driving method according to claim 8, wherein The display panel further comprises a driving chip electrically connected with the adjustable resistance module, and the driving chip pre-stores the corresponding relationship between the driving voltage and the resistance value. Before the driving voltage of each color sub-pixel is provided to the at least one data signal line respectively, the method further comprises: determining the resistance value of the adjustable resistance module corresponding to the driving voltage based on the corresponding relationship; controlling the adjustable resistance module to have the resistance value.

10. A display device comprising the display panel of any one of claims 1-7.

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