Chip packaging structure and chip packaging method

Abstract

The present application relates to a chip packaging structure and a chip packaging method, wherein the chip packaging structure includes a packaging substrate, a plurality of chip dies, an adhesive layer and a thickness limiting structure. A plurality of chip fixing positions are provided on the packaging substrate; a plurality of chip dies are provided on the packaging substrate, and the number of chip dies is equal to the number of chip fixing positions and is arranged one by one; the adhesive layer is provided between the chip dies and the packaging substrate; the thickness limiting structure is provided in the adhesive layer; wherein the elastic modulus of the thickness limiting structure is greater than the elastic modulus of the adhesive layer, so that the thickness limiting structure can limit a first preset thickness in the adhesive layer, so that the adhesive layer can be deformed under the action of an external force to a uniform thickness in each region thereof. The chip packaging structure can solve the problem of poor height uniformity of the chip dies after the chip dies are bonded and fixed to the packaging substrate.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure and a chip packaging method. Background Art

[0002] The chip packaging process involves bonding and fixing the chip die to the packaging substrate. However, due to the uncertainty of the morphology of the bonding layer between the chip die and the packaging substrate, the height uniformity of the chip die is poor after the chip die is bonded and fixed to the packaging substrate, which has an adverse effect on the quality of the final product. Summary of the invention

[0003] Based on this, it is necessary to provide a chip packaging structure and a chip packaging method to address the problem of poor height uniformity of the chip bare die after the chip bare die is bonded and fixed to the packaging substrate.

[0004] According to one aspect of the present application, a chip packaging structure is provided, including: a packaging substrate, on which a plurality of chip fixing positions are provided; a plurality of chip dies, which are arranged on the packaging substrate, and the number of the chip dies is equal to the number of the chip fixing positions and are arranged one by one; a bonding layer, which is arranged between the chip dies and the packaging substrate; and a thickness limiting structure, which is arranged in the bonding layer; wherein the elastic modulus of the thickness limiting structure is greater than the elastic modulus of the bonding layer, so that the thickness limiting structure can limit a first preset thickness in the bonding layer, so that the bonding layer can be deformed under the action of an external force to a uniform thickness in each region thereof.

[0005] In some embodiments, the thickness defining structure comprises a plurality of particles dispersed within the bonding layer.

[0006] Optionally, the particles are spherical, rugby-shaped or polyhedral in shape.

[0007] In some embodiments, the thickness limiting structure includes several sub-limiting layers; the centers of the multiple particles in the same sub-limiting layer are located in the same plane, and the plane is parallel to the surface of the bonding layer on one side that is bonded to the packaging substrate; each sub-limiting layer can limit a second preset thickness in the bonding layer; wherein the first preset thickness is greater than or equal to the second preset thickness.

[0008] In some embodiments, the bonding layer has an initial state before deformation and a preset state in which thickness of each region thereof is uniform after deformation; in the preset state, the thickness limiting structure includes one of the sub-limiting layers.

[0009] Optionally, the equivalent particle size D of the particles is smaller than the thickness T of the bonding layer in an initial state.

[0010] Optionally, the equivalent particle size D of the particles and the thickness T of the bonding layer in an initial state satisfy the condition: 50%T≤D≤90%T.

[0011] Optionally, the equivalent particle size of each of the particles is equal.

[0012] In some embodiments, the thermal conductivity of the material of the particles is higher than the thermal conductivity of the bonding layer.

[0013] Optionally, the bonding layer is made of an organic polymer.

[0014] Optionally, the bonding layer is made of epoxy resin.

[0015] Optionally, the particles are made of metal.

[0016] Optionally, the particles are made of gold, silver or copper.

[0017] In some embodiments, the particles are configured as hollow structures.

[0018] In some embodiments, the packaging substrate is provided with a plurality of the fixing positions arranged at intervals; the bonding layer includes a plurality of bonding portions arranged in one-to-one correspondence with the fixing positions.

[0019] Optionally, the number of particles in each bonding portion is equal.

[0020] In some embodiments, a groove is provided on the packaging substrate corresponding to the chip fixing position, and the adhesive layer is disposed in the groove.

[0021] Optionally, the chip die is at least partially disposed in the groove.

[0022] Optionally, a portion of the chip die is disposed in the groove, and another portion protrudes out of the groove.

[0023] In some embodiments, the width of the groove is greater than the width of the chip die.

[0024] Optionally, the bonding layer has an initial state before deformation; the width of the bonding layer in the initial state is smaller than the width of the groove.

[0025] According to another aspect of the present application, a chip packaging method is also provided, the method comprising the following steps: providing a packaging substrate and a plurality of chip dies; wherein a plurality of chip fixing positions are provided on the packaging substrate; arranging an adhesive layer on the packaging substrate, and arranging a thickness limiting structure in the adhesive layer; wherein the elastic modulus of the thickness limiting structure is greater than the elastic modulus of the adhesive layer, so that the thickness limiting structure can limit a first preset thickness in the adhesive layer; arranging the plurality of chip dies on a surface of the adhesive layer facing away from the packaging substrate; wherein the plurality of chip dies are arranged in a one-to-one correspondence with the plurality of chip fixing positions; and pressing the chip dies along the thickness direction of the adhesive layer, so that the adhesive layer is deformed until the thickness of each region thereof is uniform.

[0026] The chip packaging structure provided by the present application has an adhesive layer between the packaging substrate and the chip die, so that the chip die is bonded and fixed to the packaging substrate, and a thickness limiting structure is provided in the adhesive layer. The elastic modulus of the thickness limiting structure is greater than the elastic modulus of the adhesive layer, so that when the adhesive layer is deformed under the extrusion force of the chip die or the packaging substrate, the deformation amount of the thickness limiting structure is small, so that the thickness limiting structure can limit the first preset thickness in the adhesive layer. In this way, the combined structure of the adhesive layer and the thickness limiting structure can have a relatively stable shape, and after the chip die is bonded and fixed to the packaging substrate, the thickness uniformity of the combined structure of the adhesive layer and the thickness limiting structure is good, so that the heights of different sides of the same chip die and the heights of different chip die have good uniformity, thereby improving the quality of the final product. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram showing a chip packaging structure in the related art is shown;

[0028] Figure 2 A schematic diagram of a chip packaging structure in an embodiment of the present application is shown;

[0029] Figure 3 A schematic diagram of the structure of the bonding layer before deformation in one embodiment of the present application is shown;

[0030] Figure 4 A schematic diagram of the structure after the adhesive layer is deformed in one embodiment of the present application is shown;

[0031] Figure 5 A schematic diagram showing a chip packaging structure in another embodiment of the present application is shown;

[0032] Figure 6 A schematic diagram showing a chip packaging structure in another embodiment of the present application is shown;

[0033] Figure 7A schematic diagram of the structure after the adhesive layer is deformed in another embodiment of the present application is shown.

[0034] Description of Figure Numbers:

[0035] 10. packaging substrate; 11. groove;

[0036] 12. Bare chip;

[0037] 13. Adhesive layer;

[0038] 14. Particles; 141. Sub-defining layer. DETAILED DESCRIPTION

[0039] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0040] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0042] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0043] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0044] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0045] Chip packaging is a post-processing technology in the semiconductor chip manufacturing process, which can provide physical protection for the chip core structure, realize signal interconnection, enhance heat dissipation and fixation effects, etc. Embedded packaging technology is one of many advanced packaging technologies. It is widely used because it can shorten the length of the connection line between chips, improve electrical characteristics, enhance the protection effect of chips, and has a simple process.

[0046] Figure 1 A schematic diagram of a chip packaging structure in the related art is shown.

[0047] See also Figure 1In the embedded packaging process, the chip die 12 needs to be embedded in the packaging substrate 10, and in order to prevent the chip die 12 from moving in the subsequent packaging process or reduce the distance that the chip die 12 moves in the subsequent packaging process, an adhesive layer 13 (DAF, Die Attach Film) is usually set on one side of the chip die 12, and the chip die 12 and the packaging substrate 10 are fixed by the adhesive layer 13. However, since it is difficult to ensure the uniform thickness of the adhesive layer, and the adhesive layer 13 is easily deformed under the action of external force, after the chip die 12 and the packaging substrate 10 are fixed by the adhesive layer 13, the heights of different chip die 12 may be different, and the heights of different sides of the same chip die 12 may also be different, which has an adverse effect on the quality of the final product. At the same time, the addition of the adhesive layer 13 affects the diffusion of heat, resulting in poor heat dissipation of the final product.

[0048] To solve the above problems, the present application provides a chip packaging structure, in which an adhesive layer is arranged between the chip die and the packaging substrate, and microspheres with uniform particle size are arranged in the adhesive layer. In this way, when the chip die or the packaging substrate squeezes the adhesive layer, the microspheres will be more evenly dispersed in the adhesive layer, so that the thickness of the adhesive layer corresponding to the same chip die is more uniform, thereby improving the height uniformity of different sides of the same chip die; and, under the support of the microspheres in the adhesive layer, the thickness of the adhesive layer corresponding to different chip die is also more uniform, thereby improving the height uniformity of different chip die.

[0049] Figure 2 A schematic diagram of a chip packaging structure in an embodiment of the present application is shown.

[0050] See also Figure 2 , a chip packaging structure provided by an embodiment of the present application includes a packaging substrate 10, a plurality of chip dies 12, an adhesive layer 13 and a thickness limiting structure. A plurality of chip fixing positions are provided on the packaging substrate 10; a plurality of chip dies 12 are provided on the packaging substrate 10, and the number of chip dies 12 is equal to the number of chip fixing positions and is arranged one-to-one. Exemplarily, a plurality of array-arranged chip fixing positions are provided on the packaging substrate 10, and a plurality of chip dies 12 are fixed one-to-one to the plurality of chip fixing positions in the same array arrangement. The adhesive layer 13 is provided between the chip dies 12 and the packaging substrate 10 to fix the chip dies 12 on the packaging substrate 10. The thickness limiting structure is arranged in the bonding layer 13, wherein the elastic modulus of the thickness limiting structure is greater than the elastic modulus of the bonding layer 13, so that the thickness limiting structure can limit a first preset thickness in the bonding layer 13, thereby enabling the bonding layer 13 to be deformed under the action of an external force until the thickness of each region thereof is uniform, that is, the bonding layer 13 can be deformed under the action of an external force until the thickness of each region thereof is equal or the thickness difference between different regions is less than a preset difference.

[0051] Based on this, when the adhesive layer 13 is deformed under the extrusion force of the chip die 12 or the package substrate 10, the deformation amount generated by the thickness limiting structure is small, so that the thickness limiting structure can limit the first preset thickness in the adhesive layer 13. In this way, the combination of the adhesive layer 13 and the thickness limiting structure has a relatively stable form, so that after the chip die 12 and the package substrate 10 are bonded and fixed, the thickness uniformity of the combination of the adhesive layer 13 and the thickness limiting structure is good, so that the heights of different sides of the same chip die 12 and the heights of different chip die 12 have good uniformity, thereby improving the quality of the final product.

[0052] Figure 3 A schematic diagram of the structure of the bonding layer before deformation in one embodiment of the present application is shown. Figure 4 A schematic diagram of the structure after the adhesive layer is deformed in one embodiment of the present application is shown. Figure 5 A schematic diagram of a chip packaging structure in another embodiment of the present application is shown. Figure 6 A schematic diagram of a chip packaging structure in another embodiment of the present application is shown. Figure 7 A schematic diagram of the structure after the adhesive layer is deformed in another embodiment of the present application is shown.

[0053] See also Figure 2 , Figure 3 and Figure 4 In some embodiments, the thickness defining structure includes a plurality of particles 14 dispersed in the bonding layer 13. Figure 2 , Figure 5 and Figure 6 , the shape of the particles 14 is spherical, rugby or polyhedral. When the bonding layer 13 is subjected to an external force, the particles 14 dispersed in the bonding layer 13 will be more evenly dispersed under the action of the external force, and spread into a single or multi-layer particle layer in the bonding layer 13. Exemplarily, the thickness limiting structure includes one or more sub-limiting layers 141, and the centers of the multiple particles 14 in the same sub-limiting layer 141 are located in the same plane, and the plane is parallel to the surface of one side of the bonding layer 13 that is bonded to the packaging substrate 10, that is, the multiple particles 14 located in the same layer are combined into a sub-limiting layer 141. Each sub-limiting layer 141 can define a second preset thickness in the bonding layer 13, wherein the first preset thickness is greater than or equal to the second preset thickness.

[0054] Please note, see Figure 7When the thickness limiting structure includes multiple sub-limiting layers 141, and the number of particles 14 in a single sub-limiting layer 141 is large enough to cover an entire layer in the bonding layer 13, after the bonding layer 13 is deformed under the action of external force, there are still multiple sub-limiting layers 141 in the bonding layer 13. At this time, the first preset thickness is greater than the second preset thickness, and the thickness of the bonding layer 13 is determined by the particle size of the particles 14 and the number of sub-limiting layers 141.

[0055] See also Figure 3 and Figure 4 , when the particles 14 in a single sub-defining layer 141 are not enough to cover a whole layer in the bonding layer 13, after the bonding layer 13 is deformed under the action of external force, the particles 14 in different sub-defining layers 141 may be mixed, so that the number of layers of the sub-defining layer 141 is reduced. When it can be reduced to only one layer of the sub-defining layer 141, the first preset thickness is equal to the second preset thickness. Based on this, the number of sub-defining layers 141 and the number of particles 14 in a single sub-defining layer 141 can be adjusted according to the packaging requirements, so as to adjust the thickness of the bonding layer 13 after deformation under the action of external force, and realize the adjustment of the height of the chip bare die 12.

[0056] See also Figure 7 It can be understood that when the particles 14 are spherical particles, since the upper particle layer can partially enter the gap of the lower particle layer, the distance between the planes where the centers of two adjacent particle layers are located may be smaller than the average particle size of the two particle layers. At this time, the first preset thickness is less than twice the second preset thickness. On this basis, after the bonding layer 13 is deformed by the external force, its thickness may be equal to a non-integer multiple of the average particle size of the particles 14.

[0057] In some embodiments, the bonding layer 13 has an initial state before deformation and a preset state in which the thickness of each region is uniform after deformation. In the preset state, the thickness limiting structure includes a sub-limiting layer 141, and the centers of the multiple particles 14 in the same sub-limiting layer 141 are located in the same plane, and the plane is parallel to the surface of the side of the bonding layer 13 that is bonded to the packaging substrate 10, that is, in the preset state, the multiple particles 14 of the thickness limiting structure are spread into a single layer of particles. In this way, after the bonding layer 13 is deformed under the action of external force, the bonding layer 13 and the multiple particles 14 in the bonding layer 13 can better maintain stability. In addition, because the thickness limiting structure includes a sub-limiting layer 141, the thickness of the bonding layer 13 is relatively small, which is beneficial to reduce the overall thickness of the chip packaging structure.

[0058] Further, see Figure 3, the equivalent particle size D of the particle 14 is less than the thickness T of the bonding layer 13 in the initial state. Optionally, the equivalent particle size D of the particle 14 and the thickness T of the bonding layer 13 in the initial state satisfy the condition: 50%T≤D≤90%T. Exemplarily, D=55%T, D=60%T, D=65%T, D=70%T, D=75%T, D=80%T, D=85%T. It can be understood that the size of the particle 14 is called the grain size, also known as the particle size or diameter. When a certain physical property or physical behavior of the measured particle 14 is closest to a homogeneous sphere of a certain diameter, the diameter of the sphere is taken as the equivalent particle size of the measured particle 14. In the present application, the bonding layer 13 is used for the chip packaging structure, and the size of the chip is very small, so the thickness of the bonding layer 13 is also correspondingly small. On this basis, the particle size of the particles 14 dispersed in the bonding layer 13 is also small. On this basis, it is difficult to ensure that the shape of each particle 14 is a regular sphere or regular polyhedron. Therefore, this embodiment limits the equivalent particle size of the multiple particles 14 so that the equivalent particle size is smaller than the thickness of the bonding layer 13 in the initial state, thereby better ensuring that the multiple particles 14 are hidden in the bonding layer 13 and do not directly contact the chip die 12 or the packaging substrate 10, so as to ensure a good bonding and fixing effect, and reduce the risk of the particles 14 causing wear or extrusion to the chip die 12.

[0059] Optionally, the equivalent particle size of each particle 14 is equal. In this way, the thickness uniformity of the bonding layer 13 can be further improved.

[0060] In some embodiments, the thermal conductivity of the material of the particles 14 is higher than the thermal conductivity of the bonding layer 13. Optionally, the material of the bonding layer 13 is an organic polymer, for example, the material of the bonding layer 13 is epoxy resin. Optionally, the material of the particles 14 is a metal, for example, the material of the particles 14 is gold, silver or copper. By providing the particles 14 with higher thermal conductivity in the bonding layer 13 to act as a thickness limiting structure, the uniformity of the thickness of the bonding layer 13 is improved, and the heat dissipation performance of the chip packaging structure is improved.

[0061] In some embodiments, the particles 14 are hollow structures. In this way, the particles 14 in the bonding layer 13 have a certain deformation ability, which can further reduce the extrusion of the chip bare die 12, so that the particles 14 play a supporting role in the bonding layer 13 to limit the thickness of the bonding layer 13 and improve its buffering capacity.

[0062] It is understandable that when the package substrate 10 is provided with a plurality of chip fixing positions, and the plurality of chip dies 12 are arranged one-to-one corresponding to the plurality of chip fixing positions, the adhesive layer 13 used to bond and fix the chip dies 12 to the package substrate 10 may be a whole piece of adhesive structure, or may be a plurality of dispersed adhesive structures corresponding one-to-one to the plurality of chip fixing positions (see Figure 2 In an optional embodiment, the package substrate 10 is provided with a plurality of fixed positions arranged at intervals, and the adhesive layer 13 includes a plurality of adhesive portions arranged one-to-one corresponding to the fixed positions, so that each chip die 12 can be fixed more accurately at a preset position.

[0063] Optionally, the number of particles 14 in each bonding portion is equal. Based on this, it can be better ensured that after the adhesive layer 13 is deformed under the action of external force, the thickness of each bonding portion can be maintained at a preset thickness, which is greater than or equal to the first preset thickness.

[0064] See also Figure 2 , Figure 5 or Figure 6 In some embodiments, a groove 11 is provided on the package substrate 10 corresponding to the chip fixing position, and the adhesive layer 13 is provided in the groove 11. In this way, the bonding and fixing of each chip die 12 is independent, which is conducive to improving the accuracy of chip packaging.

[0065] Optionally, the chip die 12 is at least partially disposed in the groove 11. Exemplarily, the chip die 12 is partially disposed in the groove 11, and the other part protrudes out of the groove 11. Based on this, the part of the chip die 12 disposed in the groove 11 will be limited by the groove 11, thereby preventing the chip die 12 from moving. When a part of the chip die 12 protrudes out of the groove 11, it is convenient to connect the signal line of the chip die 12.

[0066] Optionally, the width of the groove 11 is greater than the width of the chip die 12. Thus, when the chip die 12 is placed in the groove 11, it is possible to better avoid scratching between the chip die 12 and the groove wall or groove opening of the groove 11, thereby reducing the risk of the chip die 12 being worn.

[0067] Optionally, the adhesive layer 13 has an initial state before deformation, and the width of the adhesive layer 13 in the initial state is smaller than the width of the groove 11. It is understandable that when the adhesive layer 13 is deformed under the action of an external force, if the adhesive layer 13 is squeezed and thinned, the width of the adhesive layer 13 will increase. By setting the width of the adhesive layer 13 in the initial state to be smaller than the width of the groove 11, when the adhesive layer 13 is squeezed and deformed, there is a certain reserved space in the groove 11 for the widened part of the adhesive layer 13 to extend, thereby reducing the risk of the adhesive layer 13 overflowing from the groove 11 after being squeezed.

[0068] Based on the same invention purpose, the present application also provides a chip packaging method.

[0069] See also Figure 2 , Figure 3 and Figure 4 In one embodiment of the present application, the chip packaging method includes the following steps:

[0070] A packaging substrate 10 and a plurality of bare chips 12 are provided; wherein the packaging substrate 10 is provided with a plurality of chip fixing positions;

[0071] A bonding layer 13 is provided on the packaging substrate 10, and a thickness limiting structure is provided in the bonding layer 13; wherein the elastic modulus of the thickness limiting structure is greater than the elastic modulus of the bonding layer 13, so that the thickness limiting structure can limit a first preset thickness in the bonding layer 13;

[0072] A plurality of bare chip dies 12 are arranged on the surface of the adhesive layer 13 which is away from the package substrate 10; wherein the bare chip dies 12 are arranged in one-to-one correspondence with the plurality of chip fixing positions;

[0073] The chip die 12 is pressed along the thickness direction of the adhesive layer 13 to deform the adhesive layer 13 to make the thickness of each region uniform.

[0074] The chip packaging method provided by the present application is to set an adhesive layer 13 between the packaging substrate 10 and the chip die 12, so that the chip die 12 is bonded and fixed to the packaging substrate 10, and to set a thickness limiting structure in the adhesive layer 13. By utilizing the characteristic that the elastic modulus of the thickness limiting structure is greater than the elastic modulus of the adhesive layer 13, when the adhesive layer 13 is deformed under the extrusion force of the chip die 12 or the packaging substrate 10, the deformation amount of the thickness limiting structure is small, so that the thickness limiting structure can limit the first preset thickness in the adhesive layer 13. In this way, the combined structure of the adhesive layer 13 and the thickness limiting structure can have a relatively stable shape, so that after the chip die 12 is bonded and fixed to the packaging substrate 10, the combined structure of the adhesive layer 13 and the thickness limiting structure has good thickness uniformity, so that the heights of different sides of the same chip die 12 and the heights of different chip die 12 have good uniformity, thereby improving the quality of the final product.

[0075] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A chip packaging structure, characterized in that: include: A packaging substrate, wherein a plurality of chip fixing positions are provided on the packaging substrate; A plurality of bare chip dies, wherein the bare chip dies are arranged on the packaging substrate, and the number of the bare chip dies is equal to the number of the chip fixing positions and are arranged one-to-one; An adhesive layer, the adhesive layer is provided between the chip die and the packaging substrate; as well as a thickness limiting structure, the thickness limiting structure being disposed in the bonding layer; Among them, the elastic modulus of the thickness limiting structure is greater than the elastic modulus of the bonding layer, and the thickness limiting structure can limit a first preset thickness in the bonding layer, so that the bonding layer can be deformed to a uniform thickness in each region under the action of an external force, and the thickness limiting structure includes a plurality of particles dispersed in the bonding layer, and the particles are constructed as a hollow structure.

2. The chip packaging structure according to claim 1, characterized in that: The shape of the particles is spherical, rugby-shaped or polyhedral.

3. The chip packaging structure according to claim 2, characterized in that: The thickness limiting structure includes a plurality of sub-limiting layers; The centers of the plurality of particles in the same sub-limiting layer are located in the same plane, and the plane is parallel to the surface of the bonding layer on one side that is bonded to the packaging substrate; Each of the sub-defining layers can define a second preset thickness in the bonding layer; Wherein, the first preset thickness is greater than or equal to the second preset thickness.

4. The chip packaging structure according to claim 3, characterized in that: The bonding layer has an initial state before deformation and a preset state in which the thickness of each region thereof is uniform after deformation; In a preset state, the thickness limiting structure includes one sub-limiting layer.

5. The chip packaging structure according to claim 4, characterized in that: The equivalent particle size D of the particles is smaller than the thickness T of the bonding layer in the initial state.

6. The chip packaging structure according to claim 5, characterized in that: The equivalent particle size D of the particles and the thickness T of the bonding layer in the initial state satisfy the condition: 50%T≤D≤90%T.

7. The chip packaging structure according to claim 5, characterized in that: The equivalent particle size of each of the particles is equal.

8. The chip packaging structure according to any one of claims 2 to 7, characterized in that: The thermal conductivity of the material of the particles is higher than the thermal conductivity of the bonding layer.

9. The chip packaging structure according to claim 8, characterized in that: The material of the bonding layer is organic polymer.

10. The chip packaging structure according to claim 8, characterized in that: The material of the bonding layer is epoxy resin.

11. The chip packaging structure according to claim 8, characterized in that: The material of the particles is metal.

12. The chip packaging structure according to claim 8, characterized in that: The material of the particles is gold, silver or copper.

13. The chip packaging structure according to any one of claims 2 to 7, characterized in that: The packaging substrate is provided with a plurality of the fixing positions arranged at intervals; The adhesive layer includes a plurality of adhesive portions which are arranged in one-to-one correspondence with the fixing positions.

14. The chip packaging structure according to claim 13, characterized in that: The number of the particles in each bonding portion is equal.

15. The chip packaging structure according to any one of claims 1 to 7, characterized in that: A groove is arranged on the packaging substrate corresponding to the chip fixing position, and the adhesive layer is arranged in the groove.

16. The chip packaging structure according to claim 15, characterized in that: The chip die is at least partially disposed in the groove.

17. The chip packaging structure according to claim 15, characterized in that: A portion of the chip die is disposed in the groove, and another portion protrudes out of the groove.

18. The chip packaging structure according to claim 15, characterized in that: The width of the groove is greater than the width of the chip die.

19. The chip packaging structure according to claim 18, characterized in that: The bonding layer has an initial state before deformation; the width of the bonding layer in the initial state is smaller than the width of the groove.

20. A chip packaging method, characterized in that: The method comprises the following steps: A packaging substrate and a plurality of bare chips are provided; wherein the packaging substrate is provided with a plurality of chip fixing positions; A bonding layer is provided on the packaging substrate, and a thickness limiting structure is provided in the bonding layer; wherein the elastic modulus of the thickness limiting structure is greater than the elastic modulus of the bonding layer, so that the thickness limiting structure can limit a first preset thickness in the bonding layer, and the thickness limiting structure includes a plurality of particles dispersed in the bonding layer, and the particles are configured as a hollow structure; The plurality of bare chip dies are arranged on the surface of the adhesive layer on a side away from the packaging substrate; wherein the plurality of bare chip dies are arranged in one-to-one correspondence with the plurality of chip fixing positions; The chip die is pressed along the thickness direction of the adhesive layer to deform the adhesive layer to make the thickness of each region of the adhesive layer uniform.

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