Electrostatic discharge protection device

Abstract

The present disclosure relates to an electrostatic discharge protection device. The electrostatic discharge protection device is formed using only electrically connected transistors. The transistors include a first MOS type transistor forming a clamping circuit coupled between a first supply node and a second supply node, a second MOS type transistor coupled between the first supply node and a gate terminal of the first MOS type transistor, and a third MOS type transistor having a first gate terminal coupled to a gate terminal of the second MOS type transistor, a second gate terminal coupled to one of the first supply node and the second supply node, and first and second conduction terminals coupled to the second supply node.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the priority benefit of French Patent Application No. 2200347, filed January 17, 2022, the contents of which are incorporated herein in their entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic devices and circuits, and more particularly to electrostatic discharge protection devices. BACKGROUND

[0004] As components in electronic devices become smaller and smaller, problems related to electrostatic discharge are becoming more and more common. Protecting electronic circuits from electrostatic discharge is an important issue to ensure the reliability and durability of electronic devices.

[0005] Therefore, there is a need for high-performance electrostatic discharge protection devices that are easier to implement. SUMMARY

[0006] Embodiments overcome all or part of the drawbacks of known electrostatic discharge protection devices.

[0007] One embodiment provides an electrostatic discharge protection device comprising only transistors.

[0008] According to one embodiment, the device comprises a first clamping circuit between a first power supply node and a second reference node.

[0009] According to one embodiment, the first clamping circuit comprises a first MOS transistor having a first conduction terminal coupled to the first node and a second conduction terminal coupled to the second node.

[0010] According to one embodiment, the first clamping circuit further comprises a trigger module coupled to a gate terminal of the first MOS transistor.

[0011] According to one embodiment, the trigger module comprises: a second MOS transistor having a first conduction terminal coupled to the first power supply node and a second conduction terminal coupled to the gate terminal of the first MOS transistor; a third MOS transistor having its gate terminal coupled to the first power supply node and its two conduction terminals and its body contact terminal coupled to the gate terminal of the second transistor; and a fourth MOS transistor having a first gate terminal coupled to the gate of the second transistor and a second gate terminal coupled to the second reference node, its two conduction terminals and its body contact terminal.

[0012] According to one embodiment, the trigger module comprises: a fifth MOS transistor having a first conduction terminal coupled to the first supply node and a second conduction terminal coupled to a gate terminal of the first MOS transistor; a sixth MOS transistor having a first gate terminal coupled to the first supply node, a second gate terminal coupled to a gate terminal of the fifth transistor, and both of its conduction terminals and its body contact terminal coupled to the second reference node; a seventh MOS transistor having a first conduction terminal coupled to a gate terminal of the fifth transistor and a gate; and an eighth MOS transistor having a first conduction terminal coupled to a second conduction terminal of the seventh transistor and a gate, and a second conduction terminal coupled to the second reference node.

[0013] According to one embodiment, the first clamp circuit comprises a first BiMOS transistor having: a first conduction terminal coupled to the first node; a second conduction terminal coupled to the second node; and a body contact terminal coupled to a gate terminal of the first BiMOS transistor and to the second reference node.

[0014] According to one embodiment, the first clamp circuit comprises a second BiMOS transistor having: a first conduction terminal coupled to the first node; a second conduction terminal coupled to the second node; a first body contact terminal coupled to a gate terminal of the second BiMOS transistor; and a second body contact terminal coupled to the second reference node.

[0015] According to one embodiment, the device further comprises a first diode effect component between the first supply node and a third input / output node, and a second diode effect component between the third input / output node and the second reference node.

[0016] According to one embodiment, the first diode effect component is a ninth diode- assembled MOS transistor, and the second diode effect component is a twelfth diode- assembled MOS transistor.

[0017] According to one embodiment, the first diode-like component is a third BiMOS transistor having a first conduction terminal coupled to the first node, a second conduction terminal coupled to the third input / output node, and a body contact terminal coupled to a gate terminal of the third BiMOS transistor and coupled to the third input / output node. Further, the second diode-like component is a fourth BiMOS transistor having a first conduction terminal coupled to the third input / output node, a second conduction terminal coupled to the second node, and a body contact terminal coupled to a gate terminal of the fourth BiMOS transistor and coupled to the second reference node.

[0018] According to one embodiment, the first diode-like component is a fifth BiMOS transistor having a first conduction terminal coupled to the first node, a second conduction terminal coupled to the third input / output node, a first body contact terminal coupled to a gate terminal of the fifth BiMOS transistor, and a second body contact terminal coupled to the third input / output node. Further, the second diode-like component is a sixth BiMOS transistor having a first conduction terminal coupled to the third input / output node, a second conduction terminal coupled to the second node, a first body contact terminal coupled to a gate terminal of the sixth BiMOS transistor, and a second body contact terminal coupled to the second reference node.

[0019] According to one embodiment, the device further comprises a coupling circuit capable of coupling the electrostatic discharge protection circuit to another electrostatic discharge protection circuit.

[0020] According to one embodiment, the coupling circuit comprises an eleventh MOS transistor in diode assembly between the second reference node and a fourth coupling node, and a twelfth MOS transistor in diode assembly between the fourth coupling node and the second reference node, the eleventh and twelfth MOS transistors being assembled head-to-tail.

[0021] According to one embodiment, the coupling circuit comprises a seventh BiMOS transistor in diode assembly between the second reference node and a fourth coupling node, and an eighth BiMOS transistor in diode assembly between the fourth coupling node and the second reference node, the seventh and eighth BiMOS transistors being assembled head-to-tail.

[0022] According to one embodiment, all the BiMOS transistors are formed on the same substrate. BRIEF DESCRIPTION OF DRAWINGS

[0023] The foregoing features and advantages, as well as others, will be described in more detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0024] Figure 1 An embodiment of an electrostatic discharge protection device is shown very schematically in block form;

[0025] Figure 2 An embodiment of an electrical diagram of a portion of the device of Figure 1

[0026] Figure 3 An embodiment of a current-voltage characteristic of a portion of Figure 2

[0027] Figure 4 An embodiment of an electrical diagram of another portion of the device of Figure 1

[0028] An embodiment of another portion of the device of Figure 5 Figure 1 An embodiment of a circuit of

[0029] Figure 6 Figure 5 An embodiment of an example of a circuit of

[0030] Figure 7 A top view of a circuit component of Figure 6

[0031] Another example of an embodiment of a circuit of Figure 8 Figure 5 An embodiment of an electrical diagram of a portion of the device of

[0032] Figure 9 An embodiment of an electrical diagram of a portion of the device of Figure 1

[0033] An embodiment of an electrical diagram of a portion of the device of Figure 10 Figure 1 A top view of a circuit component of

[0034] Figure 11 Figure 10 A top view of a circuit component of

[0035] Figure 12 A top view of an embodiment example of a circuit structure of Figure 10 DETAILED DESCRIPTION

[0036] ​​​​​​​​In the various drawings, like features are designated by like reference numerals. In particular, structural and / or functional features common to various embodiments can have the same reference numerals and can be provided with the same structural, dimensional, and material properties.

[0037] For the sake of clarity, only the steps and elements necessary for an understanding of the embodiments described herein are illustrated and described. In particular, the application of electrostatic discharge protection devices is not detailed, usual applications being compatible with the embodiments described hereafter.

[0038] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate non-conductor element, and when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements.

[0039] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers such as the terms "front", "back", "top", "bottom", "left", "right", etc. or relative position qualifiers such as the terms "above", "below", "upper", "lower", etc. or orientation qualifiers such as "horizontal", "vertical", etc., reference is made to the orientation shown in the drawings.

[0040] Unless otherwise specified, the expressions "around", "approximately", "substantially", "about" and "approximately" mean within 10% and preferably within 5%.

[0041] Figure 1 One embodiment of an electrostatic discharge protection device 100 is very schematically shown in the form of a block.

[0042] The device 100 is intended to be positioned between one or more power supply devices and one or more electronic devices. The device 100 is able to attenuate or even suppress voltage peaks occurring at the level of one or more input / output nodes of one or more electronic devices, and to damage them, these voltage peaks generally being due to electrostatic discharges.

[0043] The device 100 comprises a power supply node VDD1 adapted to receive a power supply potential from a power supply device and a reference (supply) node VSS1 adapted to receive a reference potential from a power supply device (for example, ground). One or more (at least one) input / output nodes IO1,..., IOK (for example, K input / output nodes, K being an integer) are adapted to be coupled to one or more input or output terminals of one electronic device among a plurality of electronic devices to be protected. In addition, one or more coupling nodes VINT are adapted to be coupled to another electrostatic discharge protection device.

[0044] According to the example, the power node VDD1 and the reference node VSS1 can be coupled (preferably connected) to the power rail that transmits the power potential and the ground rail that transmits the reference potential (e.g., grounded), respectively.

[0045] It is assumed here that the power potential received at the level of power node VDD1 is positive and greater than the reference potential received at the level of reference node VSS1.

[0046] Device 100 is formed from various circuits and components, enabling it to implement electrostatic discharge (ESD) protection. Typically, ESD protection devices include assemblies of electronic components, among which different types of diodes are present. According to one embodiment, device 100 includes only transistors coupled together by electrical conductors as electronic components. In other words, device 100 does not include other types of electronic components, and specifically, device 100 does not include diodes. In this description, it is assumed that even if a non-ideal conductor has inherent impedance, i.e., inherent resistivity, inherent capacitance, and inherent inductance, the conductor is not considered a component.

[0047] Device 100 comprises: a clamping circuit 101 having behavior similar to that of an avalanche diode; a plurality of diode-effect components 102; and one or more coupling circuits 103, wherein a single coupling circuit 103 is in Figure 1 As shown in the image.

[0048] exist Figure 1 In the diagram, clamping circuit 101 is represented by a block containing the electronic symbol of a Zener diode. Clamping circuit 101 includes a terminal 101-VDD coupled (preferably connected) to power node VDD1 and a terminal 101-GND coupled (preferably connected) to reference node VSS1. For example, by directing this peak towards node VSS1, clamping circuit 101 (also referred to as clamping) is a circuit suitable for attenuating or even suppressing voltage peaks that may occur at the level of node VDD1. Clamping circuits can have behavior similar to that of avalanche diodes. As previously mentioned, clamping circuit 101 only includes transistors coupled together by conductors as electronic components.

[0049] exist Figure 1In the diagram, diode effect components 102 are represented by blocks containing electronic symbols including those of conventional diodes. Each diode effect component 102 is a component or electronic circuit that can be likened to a biased dipole, similar to a diode, conducting current in only one direction. Therefore, each diode effect component 102 includes two terminals 102K and 102A. The diode effect component 102 conducts current reaching its terminal 102A and flowing out through its terminal 102K, and prevents current from flowing to its terminal 102K. In other words, terminal 102K corresponds to the cathode of the diode, and terminal 102A corresponds to the anode of the diode. As previously mentioned, the diode effect component 102 is formed solely of transistors coupled together by conductors.

[0050] A diode-effect component 102 is positioned between an input / output (IO) node IOi (where i is an integer ranging from 1 to K) and a power supply node VDD1 or a reference node VSS1. More specifically, diode-effect component 102-VDD is positioned between node IOi and power supply node VDD1. Terminal 102K of component 102-VDD is coupled (preferably connected) to power supply node VDD1, and terminal 102A of component 102-VDD is coupled (preferably connected) to input / output node IOi. Diode-effect component 102-GND is positioned between node IOi and reference node VSS1. Terminal 102K of component 102-GND is coupled (preferably connected) to input / output node IOi, and terminal 102A of component 102-GND is coupled (preferably connected) to reference node VSS1.

[0051] exist Figure 1 In the diagram, the coupling circuit 103 is represented by a block of electronic symbols comprising two diodes coupled in parallel and arranged end-to-end. The coupling circuit 103 is a circuit that operates identically to the two diodes coupled in parallel and arranged end-to-end, and is capable of connecting device 100 to another electrostatic discharge protection device without requiring it to receive voltage peaks received by the other device. As previously mentioned, the coupling circuit 103 comprises only transistors coupled together by conductors as electronic components.

[0052] Figures 2 to 8 It shows about Figure 1 Examples of embodiments of the circuitry and components of the described device 100, wherein the circuitry and components are formed of MOS-type transistors.

[0053] In the rest of the disclosure, MOS type transistors or MOS transistors are metal-oxide-semiconductor field-effect transistors, more commonly referred to as MOSFETs. N-channel MOS type transistors are also referred to as NMOS transistors. P-channel MOS type transistors are also referred to as PMOS transistors. Hereafter, unless otherwise specified, NMOS or PMOS transistors are formed in a solid substrate and insulated, or on a silicon-on-insulator (SOI) type structure.

[0054] Figures 2 to 8 An example is shown more particularly for an embodiment using an NMOS transistor. The person skilled in the art will be able to adapt the examples of these figures to a PMOS transistor.

[0055] Figure 2 An example embodiment of a diode effect component 200 of one of the diode effect components 102 described with respect to Figure 1 An electrical diagram of an example embodiment of a diode effect component 200 of one of the diode effect components 102 described with respect to

[0056] The diode effect component 200 comprises a MOS transistor 201, for example an NMOS transistor, diode assembled between a node 200K (corresponding to the terminal 102K described with respect to Figure 1 Figure 1 More particularly, one of the conducting terminals of the transistor 201 is coupled, preferably connected, to the node 200K and the other of its conducting terminals is coupled, preferably connected, to the node 200A. The conducting terminal coupled to the node 200K is for example the source of the NMOS transistor 201 and the other conducting terminal coupled to the node 200A is for example the drain of the NMOS transistor 201. The gate terminal or gate of the NMOS transistor 201 is coupled, preferably connected, to the node 200A. The transistor 201 also comprises a channel contact or body contact terminal 201BC, making it possible to apply a potential direction to its channel region. Here, the terminal 201BC remains floating, or according to a variant, the terminal 201BC can receive a reference potential such as ground, or according to the circuit, if this can have an inactive potential, the terminal 201BC can receive a source.

[0057] As previously described, the diode effect component 200 comprises only a transistor.

[0058] Figure 3 An example is shown more particularly for an embodiment using an NMOS transistor. The person skilled in the art will be able to adapt the examples of these figures to a PMOS transistor. Figure 2 The current-voltage characteristic of the diode effect component 200 described with respect to

[0059] As previously described, the diode effect component 200 comprises only a transistor. Figure 3 ​As shown, the assembly 200 has current-voltage characteristics similar to those of a diode. The threshold voltage of the assembly 200 is determined according to the structural characteristics of the assembly, such as its structure, dimensions, materials forming the assembly, etc. The element that is particularly used to adjust the threshold voltage of the assembly 200 is the partial covering of the drain, source and gate layers with a silicide layer, and then the formation of contact areas on this layer.

[0060] Figure 4 An electrical diagram of an embodiment example of a coupling circuit 300 of the type of one of the coupling circuits 103 described is shown. Figure 1 An electrical diagram of an embodiment example of a coupling circuit 300 of the type of one of the coupling circuits 103 described is shown.

[0061] The coupling circuit 300 comprises two MOS transistors 301 and 302, for example NMOS transistors, diode assembled head to tail between two nodes 300A and 300B of the coupling circuit 300. The nodes 300A and 300B can be indifferently coupled, preferably connected, to the potentials VSS1 and VINT with respect to Figure 1 The nodes VSS1 and VINT described.

[0062] More particularly, one of the conducting terminals of the transistor 301 is coupled, preferably connected, to the node 300A and the other conducting terminal is coupled, preferably connected, to the node 300B. The conducting terminal coupled to the node 300A is for example the source of the NMOS transistor 301 and the other conducting terminal coupled to the node 300B is for example the drain of the NMOS transistor 301. The gate terminal or gate of the NMOS transistor 301 is coupled, preferably connected, to the node 300A. The body contact terminal 301BC of the transistor 301 remains floating, or according to a variant, the body contact terminal 301BC can receive a reference potential such as ground, or according to the circuit, if this can have an inactive potential, the body contact terminal 301BC can receive the source.

[0063] Further, one of the conducting terminals of the transistor 302 is coupled, preferably connected, to the node 300B and the other conducting terminal is coupled, preferably connected, to the node 300A. The transistor 302 is diode assembled head to tail with the transistor 301, the conducting terminal coupled to the node 300B is for example the source of the transistor 302 and the other conducting terminal coupled to the node 300A is for example the drain of the transistor 302. The gate terminal or gate of the NMOS transistor 302 is coupled, preferably connected, to the node 300A. The body contact terminal 302BC of the transistor 302 remains floating, or according to a variant, the body contact terminal 302BC can receive a reference potential such as ground, or according to the circuit, if this can have an inactive potential, the body contact terminal 302BC can receive the source.

[0064] As previously described, the coupling circuit 300 comprises only transistors.

[0065] Figure 5 The description of the coupling circuit 300 is illustrated in part in the form of a block diagram. Figure 1 An electrical diagram of an embodiment example of a clamping circuit 400 of the type of one of the clamping circuits 101 described is described.

[0066] The clamping circuit 400 comprises a component 401 suitable for conducting an electrostatic discharge from a node 400IN to a node 400OUT, and a module 402 (DEC) for triggering said component 401, assembled in parallel with the component 401 between an input node 400IN (corresponding to the terminal 101-VDD described with respect to Figure 1 the terminal 101-VSS described with respect to Figure 1 the terminal 101-VSS described with respect to

[0067] According to an embodiment, the component 401 is a MOS transistor 401, for example an NMOS transistor. One of the conduction terminals of the transistor 401 is coupled (preferably connected) to the node 400IN and the other conduction terminal is coupled (preferably connected) to the node 400OUT. The conduction terminal coupled to the node 400IN is for example the source of the transistor 401 and the conduction terminal coupled to the node 400OUT is for example the drain of the transistor 401. The gate terminal or gate 401G of the NMOS transistor 401 is coupled (preferably connected) to the triggering module 402. The body contact terminal 401BC of the transistor 401 remains floating, or according to a variant, the body contact terminal 401BC can receive a reference potential (such as ground), or according to the circuit, if this can have an inactive potential, the body contact terminal 401BC can receive the source. According to an embodiment, the transistor 401 is a transistor having dimensions that enable it to conduct an electrostatic discharge without being damaged. More precisely, the transistor 401 can be a large size transistor, i.e. a transistor having for example a gate width of the order of 1000 pm and a gate length of the order of 28 nm. According to an embodiment, the transistor 401 can be formed from a plurality of NMOS transistors coupled in parallel with each other, i.e. all their sources are coupled (preferably connected) to each other, their drains are coupled (preferably connected) to each other, and their gates are coupled (preferably connected) to each other.

[0068] The trigger module 402 is a circuit adapted to detect the presence of an electrostatic discharge between the nodes 400IN and 400OUT and to render conductive the component 401. To this end, the trigger module 402 comprises an input terminal 402IN coupled (preferably connected) to the node 400IN, an output terminal 402OUT coupled (preferably connected) to the node 400OUT, and a control terminal 402COMM coupled (preferably connected) to the component 401. According to an example, the control terminal 402COMM is coupled (preferably connected) to the gate of the transistor 401. According to an embodiment, the trigger module 402 is a circuit formed only of transistors. A detailed example of a trigger module 402 is described with respect to Figure 6 , Figure 7 and Figure 8 .

[0069] As previously described, the clamp circuit 400 comprises only transistors.

[0070] Figure 6 A detailed example of an embodiment of a clamp circuit 500 of the type of the clamp circuit 400 described with respect to Figure 5 is shown in an electrical diagram in a more detailed manner, in which the trigger module is detailed.

[0071] The clamp circuit 500 comprises elements common to the clamp circuit 400 of Figure 4 . In what follows, these common elements will not be detailed again and only the differences between the circuits 400 and 500 will be highlighted.

[0072] Thus, as for the circuit 400 described with respect to Figure 5 , the circuit 500 comprises: an input terminal 400IN; an output terminal 400OUT; and a transistor 401.

[0073] The circuit 500 further comprises a trigger module 502 of the type of the trigger module 402. The trigger module 502 is a circuit adapted to detect the presence of an electrostatic discharge between the nodes 400IN and 400OUT and to render conductive the component 401 (and more particularly adapted to detect the discharge in a "dynamic" manner). To this end, the trigger module 502 comprises an input terminal 502IN coupled (preferably connected) to the node 400IN, an output terminal 502OUT coupled (preferably connected) to the node 400OUT, and a control terminal 502COMM coupled (preferably connected) to the component 401. According to an example, the control terminal 502COMM is coupled (preferably connected) to the gate 401G of the transistor 401.

[0074] The trigger module 502 comprises a MOS transistor 503, for example an NMOS transistor, a MOS transistor 504, for example an NMOS transistor, assembled as a capacitor, and a MOS transistor 505, for example an NMOS transistor, assembled as a resistor.

[0075] One conduction terminal of the transistor 503 is coupled, preferably connected, to the input node 502IN, and the other conduction terminal is coupled, preferably connected, to the node 502COMM. The conduction terminal coupled to the node 502IN is for example the drain of the transistor 503, and the other conduction terminal coupled to the node 502COMM is for example the source of the transistor 503. The gate of the NMOS transistor 503 is coupled, preferably connected, to the node A. The body contact terminal 503BC of the transistor 503 is coupled, preferably connected, to the source of the transistor 503, i.e. to the terminal 502COMM.

[0076] The transistor 504 is assembled as a capacitor between the node 502IN and the node A. To this end, the gate of the transistor 504 is coupled, preferably connected, to the node 502IN, and the two conduction terminals and the body contact terminal of the transistor 504 are all three coupled to each other and to the node A. Thereby, the transistor 504 is equivalent to a capacitor having as a capacitance the internal capacitance of the transistor 504.

[0077] The transistor 505 is assembled as a resistor between the node A and the node 502OUT. To this end, the transistor 505 comprises two gate terminals, each corresponding to a contact area on the gate region of the transistor 505. This will be described in more detail with respect to Figure 7 The first gate terminal 505G1 is coupled, preferably connected, to the node A, and the second gate terminal 505G2 is coupled, preferably connected, to the node 502OUT. The two conduction terminals and the body contact terminal of the transistor 505 are all three coupled to each other and to the node 502OUT. Thereby, the transistor 505 is equivalent to a resistor, the resistance of which is the resistance of the part of the gate region of the transistor 505 located between the two contact areas corresponding to the terminals 505G1 and 505G2, as described with respect to Figure 7 .

[0078] The operation of the trigger module 502 is as follows. When an electrostatic discharge occurs at the level of the node 400IN, i.e. when a potential peak appears at the level of the node 400IN, and since the transistors 504 and 505 form an RC type circuit, the potential at the level of the node A increases enough to turn on the transistor 503. By turning on, the transistor 503 sends the potential peak to the gate of the transistor 401, which turns on the transistor 401 and enables it to conduct the potential peak all the way to the output node 400OUT.

[0079] As previously described, the trigger module 500 comprises only transistors.

[0080] Figure 7 is about Figure 6 A top view of an embodiment example of the transistor 505 is described.

[0081] For example, the transistor 505 can have an elongated shape and comprises source 601, drain 602 and gate 603 regions of substantially rectangular shape. Contacts are formed on the source 601 and drain 602 regions respectively, the source contact being coupled (preferably connected) to the node 505S and the drain contact being coupled (preferably connected) to the node 505D. A plurality of contacts can be formed on each of its regions and connected to each other.

[0082] At least one first gate contact coupled (preferably connected) to the node 505G1 and at least one second gate contact coupled (preferably connected) to the node 505G2 are formed on the gate region 603 of the transistor 505. These contacts are spaced apart from each other by a distance d and are not coupled to each other. When the transistor 505 is assembled as a resistor, its resistivity is a function of the distance d and of the presence or not of silicide on the gate of the transistor 505, typically made of polysilicon, among others, as previously described.

[0083] Figure 8 is about Figure 5 An electrical diagram of another example of an embodiment of a clamping circuit 700 of the type of the clamping circuit 400 described, in which the trigger module is detailed, is described.

[0084] The clamping circuit 700 comprises elements common to the clamping circuit 400 of Figure 4 . In the following, these common elements will not be detailed again and only the differences between the circuits 400 and 700 will be highlighted.

[0085] Thus, as the circuit 400 described in relation with Figure 5 , the circuit 700 comprises: an input terminal 400IN; an output terminal 400OUT; and a transistor 401.

[0086] The circuit 700 further comprises a trigger module 702 of the type of the trigger module 402. The trigger module 702 is a circuit adapted to detect the presence of an electrostatic discharge between the nodes 400IN and 400OUT and to make the component 401 conductive, and more specifically adapted to detect the discharge in a "static" manner. To this end, the trigger module 702 comprises an input terminal 702IN coupled, preferably connected, to the node 400IN, an output terminal 702OUT coupled, preferably connected, to the node 400OUT, and a control terminal 702COMM coupled, preferably connected, to the component 401. According to an example, the control terminal 702COMM is coupled, preferably connected, to the gate of the transistor 401.

[0087] The trigger module 702 comprises a MOS transistor 703, for example an NMOS transistor, a MOS transistor 704 assembled as a resistor, for example an NMOS transistor, a diode assembled MOS transistor 705, for example an NMOS transistor, and a diode assembled MOS transistor 706, for example an NMOS transistor.

[0088] One conductive terminal of the transistor 703 is coupled, preferably connected, to the input node 702IN and the other conductive terminal thereof is coupled, preferably connected, to the node 702COMM. The conductive terminal coupled to the node 702IN is for example the drain of the transistor 703 and the other conductive terminal coupled to the node 702COMM is for example the source of the transistor 703. The gate of the NMOS transistor 703 is coupled, preferably connected, to the node B. The body contact terminal 703BC of the transistor 302 is coupled, preferably connected, to the source of the transistor 703, i.e. to the terminal 702COMM.

[0089] The transistor 704 is assembled as a resistor between the node 702IN and the node B and is of the same type as the transistor 505 described with respect to Figure 6 and Figure 7 The transistor 704 comprises two gate terminals each corresponding to a contact area on the gate region of the transistor 704. The first gate terminal 704G1 is coupled, preferably connected, to the node 702IN and the second gate terminal 704G2 is coupled, preferably connected, to the node B. The two conductive terminals and the body contact terminal of the transistor 704 are all three coupled to each other and to the node 702OUT. The transistor 704 is thus equivalent to a resistor whose resistance is the resistance of the portion of the gate region of the transistor 704 located between the two contact areas corresponding to the terminals 704G1 and 704G2.

[0090] The transistors 705 and 706 are diode assembled in series between the node B and 702OUT.

[0091] More particularly, one conductive terminal of the transistor 705 is coupled, preferably connected, to the node C, and the other conductive terminal is coupled, preferably connected, to the node B. The conductive terminal coupled to the node C is for example the source of the NMOS transistor 705, and the other conductive terminal coupled to the node B is for example the drain of the NMOS transistor 705. The gate terminal or gate of the NMOS transistor 705 is coupled, preferably connected, to the node B. The body contact terminal 705BC of the transistor 705 remains floating, or according to a variant, the body contact terminal 705BC can receive a reference potential such as ground, or according to the circuit, the body contact terminal 705BC can receive the source if this can have an inactive potential.

[0092] Further, one conductive terminal of the transistor 706 is coupled, preferably connected, to the node 702OUT, and the other conductive terminal is coupled, preferably connected, to the node C. The conductive terminal coupled to the node 702OUT is for example the source of the NMOS transistor 706, and the other conductive terminal coupled to the node C is for example the drain of the NMOS transistor 706. The gate terminal or gate of the NMOS transistor 706 is coupled, preferably connected, to the node C. The body contact terminal 706BC of the transistor 706 remains floating, or according to a variant, the body contact terminal 706BC can receive a reference potential such as ground, or according to the circuit, the body contact terminal 706BC can receive the source if this can have an inactive potential.

[0093] The operation of the triggering module 702 is as follows. When an electrostatic discharge occurs at the level of the node 400IN, the potential at the level of the node B increases enough to make the transistor 703 conductive. The resistivity of the transistor 704 and the voltage drop of the diode assembly of the transistors 705 and 706 are adjusted so that if an electrostatic discharge occurs on the node 702IN, the potential at the level of the node B only makes the transistor 703 conductive. By conducting, the transistor 703 sends the potential peak onto the gate of the transistor 401 which makes the transistor 401 conductive and enables it to conduct the potential peak to the output node 400OUT.

[0094] As previously described, the triggering module 500 only comprises transistors.

[0095] Figures 9 to 12 An example is shown with respect to Figure 1 An example of an embodiment of the circuit and components of the device 100 is described, in which the circuit and components are formed from BiMOS type transistors.

[0096] In the remainder of the disclosure, BiMOS type transistors are referred to as transistors combining the features of bipolar transistors and MOS transistors. BiMOS transistors have the structure of MOS transistor type of structure, but also include a channel contact or a base contact or a body contact coupled to its channel region. For a transistor having the same structure as an NMOS transistor, an N-type BiMOS transistor will be evoked; and for a transistor having the same structure as a PMOS transistor, a P-type BiMOS transistor will be evoked.

[0097] Figures 9 to 12 An example of an embodiment using an N-type BiMOS transistor is shown more particularly. The person skilled in the art will be able to adapt the examples of these figures to a P-type BiMOS transistor.

[0098] Figure 9 An electrical diagram showing an example of an embodiment of a diode effect component 800 is shown.

[0099] The component 800 comprises an N-type BiMOS transistor 801. The transistor 801 is diode assembled between a node 800K and a node 800A. More particularly, one conduction terminal of the transistor 801 is coupled, preferably connected, to the node 800K and the other conduction terminal is coupled, preferably connected, to the node 800A. The conduction terminal coupled to the node 800K is for example the source of the NMOS transistor 801 and the other conduction terminal coupled to the node 800A is for example the drain of the NMOS transistor 801. The gate 801G of the NMOS transistor 801 is coupled, preferably connected, to the node 800A. For the following, the resistivity of the conductor coupling the gate 801G to the node 800A is represented by a resistor 802. By modifying the resistor 802, i.e. by modifying the quantity of conductor used to couple the terminals 801G and 800OUT, the breakdown voltage of the transistor 801 can be adjusted. Further, as mentioned previously, the transistor 801 comprises a body contact terminal 801BC. Here, the terminal 801BC is coupled, preferably connected, to the gate 801G of the transistor 801.

[0100] The diode effect component 800 has the same behavior as a Zener diode and can be used as a clamping circuit 101 and as a diode effect component 102 in the device 100 described with respect to Figure 1 The diode effect component 800 is described with respect to Figure 1 The diode effect component 800 is described with respect to Figure 1 The diode effect component 800 is described with respect to Figure 1The diode effect component 900 can be used as the clamp circuit 101 and as the diode effect component 102 in the device 100 described with respect to Figure 1 The diode effect component 900 can be used as the clamp circuit 101 and as the diode effect component 102 in the device 100 described with respect to Figure 1 The diode effect component 900 can be used as the clamp circuit 101 and as the diode effect component 102 in the device 100 described with respect to

[0101] As previously described, the diode effect component 900 comprises only a transistor.

[0102] Figure 10 An electrical diagram illustrating an embodiment example of a diode effect component 900 is shown.

[0103] The component 900 comprises an N-type BiMOS transistor 901. The transistor 901 is diode assembled between a node 900K and a node 900A. More specifically, one conducting terminal of the transistor 901 is coupled, preferably connected, to the node 900K and its other conducting terminal is coupled, preferably connected, to the node 900A. The conducting terminal coupled to the node 900K is for example the source of the NMOS transistor 901 and the other conducting terminal coupled to the node 900A is for example the drain of the NMOS transistor 901. The gate 901G of the NMOS transistor 901 is coupled, preferably connected, to the node 900A. As for the diode effect component 800 described with respect to Figure 9 Unlike the transistor 801 described with respect to Figure 6 the transistor 505 described with respect to or the two gate terminals of the transistor 704 described with respect to Figure 8 the transistor 505 described with respect to or the two gate terminals of the transistor 704 described with respect to Figure 11 are described with respect to

[0104] The diode effect component 900 can be used as the clamp circuit 101 and as the diode effect component 102 in the device 100 described with respect to Figure 1 The diode effect component 900 can be used as the clamp circuit 101 and as the diode effect component 102 in the device 100 described with respect to Figure 1 The diode effect component 900 can be used as the clamp circuit 101 and as the diode effect component 102 in the device 100 described with respect to Figure 1 The diode effect component 900 can be used as the clamp circuit 101 and as the diode effect component 102 in the device 100 described with respect to Figure 1 The diode effect component 900 can be used as the clamp circuit 101 and as the diode effect component 102 in the device 100 described with respect to Figure 1The terminal 102A described. By coupling head-to-tail with another identical component, the diode effect component 900 can be used in about Figure 1 The circuit 103 described is of the type of coupling circuit.

[0105] As previously described, the diode effect component 800 includes only a transistor.

[0106] Figure 11 is a top view of an embodiment of a BiMOS transistor 1000 formed on the interior and top of an SOI structure (more specifically, on the interior and top of an FDSOI structure). The BiMOS transistor 1000 is about Figure 10 An actual example of an embodiment of the transistor 901 described.

[0107] The transistor 1000 includes a very heavily doped N-type (N+) source region 1000S; a very heavily doped N-type (N+) drain region 1000D; a channel region (not shown in the middle), having a gate stack or gate region 1000G on top; a very heavily P-type doped (P+) substrate contact region 1000BG; and two very heavily P-type doped (P+) body contact regions 1000BC1 and 1000BC2. Figure 2

[0108] In general, the following terms are used: a lightly doped semiconductor layer designates a layer having a dopant atom concentration in the range of 1 x 1014 14 to 5 x 1015 17 atoms / cm 3 ; a heavily doped semiconductor layer designates a layer having a dopant atom concentration in the range of 5 x 1015 17 to 1 x 1017 18 atoms / cm 3 ; and a very heavily doped semiconductor layer designates a layer having a dopant atom concentration in the range of 1 x 1017 18 to 1 x 1018 21 atoms / cm 3 .

[0109] In the top view, the channel and gate region 1000G has a shape of, for example, an inert H. More specifically, the channel and gate region 1000G includes two parallel branches to a central branch perpendicular to the two branches. The central branch couples the two parallel branches. The thickness of the main branch corresponds to the gate length L. The length of the channel and gate region 1000G corresponds to the gate width W (see Figure 11 ).

[0110] ​The source region 1000S and the drain region 1000D are arranged on either side of the main branch of the channel region, between the parallel branches. The source region 1000S and the drain region 1000D have, in top view, for example, a rectangular shape.

[0111] The two body contact regions 1000BC1 and 1000BC2 are arranged on either side of the channel and gate region 1000G, more specifically, on the outside of the two parallel branches of the channel and gate region 1000G. In other words, each channel contact region is arranged at one end of the transistor 1000.

[0112] The substrate contact region 1000BG is arranged on one side of the transistor 1000 and is separated from the other regions by an insulating region 1000ISO. The regions 1000ISO and 1000BG have, in top view, one shape, for example, a rectangle, which extends alongside the other regions.

[0113] In the device 100 described with respect to Figure 1 The use of the transistor 1000 as a diode effect component or clamping circuit in the device 100 described can be performed as follows.

[0114] The drain region 1000D is coupled, preferably connected, to the input node 1000IN. The source region 1000S is coupled, preferably connected, to the output node OUT. The output node 1000OUT can for example be able to receive a reference potential, for example, ground. The body contact region 1000BC1 is coupled, preferably connected, to the gate region 1000G via one or more lines or vias 1000F. The channel contact region 1000BC2 is coupled, preferably connected, to the output node 1000OUT.

[0115] The transistor 1000 has the advantage that the triggering voltage of the transistor 1000, i.e. the voltage to be applied between the source region 1000S and the drain region 1000D to make the transistor 1000 conductive, can be adjusted simply by adjusting the internal resistance R of the channel region of the transistor 1000. In fact, the more the internal resistance of the channel region increases, the more the triggering voltage decreases.

[0116] In fact, the internal resistance R of the channel region of the transistor 1000 is defined by the following formula:

[0117]

[0118] wherein: p designates the resistivity of the material of the channel region; L designates the length of the channel region; W designates the width of the channel region; and T designates the thickness of the channel in a direction orthogonal to the plane of the drawing, in the case where the transistor 1000 is formed in an FDSOI type structure, but it can also be envisaged in the case where the transistor 1000 is formed (and insulated) on a bulk substrate.

[0119] Thus, four different parameters can be changed to adjust the triggering voltage of the transistor 1000.

[0120] As an example, the internal resistance R can be modified by forming an opening in the buried insulating layer of the FDSOI structure in which the transistor is formed. Thus, the resistance of the substrate of the structure has an influence on the resistance of the channel region.

[0121] The resistance of the channel region can also be modified by applying a positive or negative potential between the substrate region 1000BG and the output node 1000OUT. Indeed, the biasing of the substrate can modify the resistance of the channel region through the capacitive effect with the buried insulating layer of the SOI structure. In particular, a negative biasing of the channel region can enable to reduce the internal resistance of the channel region. This is only possible when the transistor is formed on the inside and on the top of the SOI structure.

[0122] As an example, the internal resistance R can be reduced by reducing the length L of the channel region.

[0123] As an example, the internal resistance R can be reduced by increasing the width W of the channel region. The modification of this parameter can also modify the thermal voltage of the transistor.

[0124] With regard to Figure 11 Another advantage of the transistor 1000 described is that the transistor 1000 also comprises a parasitic diode between the terminals 1000IN and 1000OUT, enabling to filter negative electrostatic discharges. More particularly, this diode is formed by the P-type doped body contact region 1000BC2 and the P-type doped channel region (anode of the parasitic diode), and by the N-type doped drain region 1000D (cathode of the parasitic diode).

[0125] Figure 12 is a top view of an embodiment of a structure 1100 comprising a plurality of BiMOS transistors of the type described with regard to Figure 11 The structure 1100 is an embodiment of a plurality of BiMOS transistors of the type described with regard to Figure 10 is another practical example of an embodiment of the assembly 900 described.

[0126] The structure 1100 comprises a plurality of BiMOS transistors of the type described with regard to Figure 11A plurality of BiMOS transistors of the type of the BiMOS transistor 1000 is described, which is formed on the SOI structure and for some of them has gate regions coupled to each other in the structure. More specifically, the transistors in the structure are arranged in rows and columns, the transistors of the same column having a "common" gate, in other words all their gate regions are formed in a single block.

[0127] The structure 1100 has the advantage that, by adapting the connections between the different BiMOS transistors, the structure 1100 can form on the same SOI or FDSOI type structure different types of devices, such as for example Figure 1 An electrostatic discharge protection device of the type of the device 100 is described.

[0128] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these various embodiments and variants can be combined and that other variants will occur to the person skilled in the art. In particular, the device can comprise different types of transistors to form different elements, which elements form the transistors, for example MOS transistors and BiMOS transistors.

[0129] Finally, the practical implementation of the described embodiments and variants is within the capabilities of the person skilled in the art, based on the functional indications given above.

Claims

1. An electrostatic discharge protection device, comprising a clamping circuit formed solely by electrically connected transistors, said transistors comprising: The first MOS transistor has a first conductive terminal coupled to a first supply node and a second conductive terminal coupled to a second supply node; The second MOS transistor has a first conductive terminal coupled to the first supply node and a second conductive terminal coupled to the gate terminal of the first MOS transistor; as well as The third MOS transistor has a first conductive terminal and a second conductive terminal coupled to the second supply node, a first gate terminal coupled to the gate terminal of the second MOS transistor, and a second gate terminal coupled to one of the first supply node and the second supply node.

2. The device according to claim 1, wherein the body contact terminal of the third MOS transistor is coupled to the second supply node.

3. The device of claim 1, wherein the second gate terminal of the third MOS transistor is coupled to the second supply node, and the device further comprises: The fourth MOS transistor has a first conductive terminal and a second conductive terminal coupled to the gate terminal of the second MOS transistor, and a gate terminal coupled to the first supply node.

4. The device according to claim 3, wherein the body contact terminal of the fourth MOS transistor is coupled to the gate terminal of the second MOS transistor.

5. The device of claim 3, wherein the second MOS transistor, the third MOS transistor, and the fourth MOS transistor form a trigger circuit, the trigger circuit being configured to generate a trigger signal, the trigger signal being applied to the gate terminal of the first MOS transistor to control the conduction of the first MOS transistor, wherein the trigger signal is generated by the trigger circuit in response to an electrostatic discharge event at one or more of the first and second supply nodes.

6. The device of claim 3, wherein the fourth MOS transistor comprises an N-type BiMOS transistor.

7. The device of claim 1, wherein the second gate terminal of the third MOS transistor is coupled to the first supply node, and the device further comprises: The fifth MOS transistor has a first conductive terminal and a gate coupled to the gate terminal of the second MOS transistor; as well as The sixth MOS transistor has a first conductive terminal and a gate coupled to the second conductive terminal of the fifth MOS transistor, and a second conductive terminal coupled to the second supply node.

8. The device according to claim 7, wherein the body contacts of the first MOS transistor and the sixth MOS transistor remain floating.

9. The device according to claim 7, wherein the body contacts of the first MOS transistor and the sixth MOS transistor are coupled to a reference potential.

10. The device according to claim 9, wherein the reference potential is a ground potential.

11. The device of claim 7, wherein each of the fifth and sixth MOS transistors is an N-type BiMOS transistor.

12. The device of claim 3, wherein the second MOS transistor, the third MOS transistor, the fifth MOS transistor, and the sixth MOS transistor form a trigger circuit, the trigger circuit being configured to generate a trigger signal, the trigger signal being applied to the gate terminal of the first MOS transistor to control the conduction of the first MOS transistor, wherein the trigger signal is generated by the trigger circuit in response to an electrostatic discharge event at one or more of the first supply node and the second supply node.

13. The device according to claim 1, further comprising: Input / output nodes; A first diode-effect component is coupled between the first supply node and the input / output node; as well as A second diode-effect component is coupled between the input / output node and the second supply node.

14. The device according to claim 13: The first diode effect component includes a MOS transistor assembled from a first diode; and The second diode effect component includes a MOS transistor assembled from a second diode.

15. The device of claim 14, wherein each of the first diode-assembled MOS transistor and the second diode-assembled MOS transistor is implemented as an n-type BiMOS transistor.

16. The device according to claim 1, further comprising: The coupling circuit is configured to couple the second supply node to another supply node of another electrostatic discharge protection device.

17. The device of claim 16, wherein the coupling circuit comprises: The MOS transistor assembled with the third diode and the MOS transistor assembled with the fourth diode are connected head-to-tail to ground between the second supply node and the other supply node.

18. The device of claim 1, wherein the first MOS transistor comprises an n-type BiMOS transistor.

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