A semiconductor structure and method of manufacture

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method. The semiconductor structure comprises: a substrate, the substrate has a bit line extending along a first direction; a semiconductor channel, the semiconductor channel is located on the bit line; a semiconductor doped layer, the semiconductor doped layer is located on the side of the bit line, and the top surface of the semiconductor doped layer is in contact with the semiconductor channel; a word line extending along a second direction, the word line surrounds part of the semiconductor channel, and the bottom surface of the word line is higher than the top surface of the bit line; a word line dielectric layer, the word line dielectric layer is located between the word line and the semiconductor channel; and an isolation layer, the isolation layer is located between the word line and the bit line and between the word line and the semiconductor doped layer. The semiconductor structure and the manufacturing method provided by the embodiment of the present disclosure at least have the advantage of solving the problem of weak conduction between the bit line structure and the active structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and manufacturing method. Background Technology

[0002] Semiconductor memory structures typically include word lines and bit lines. To improve the integration density of integrated circuits while increasing the operating speed and reducing power consumption of memory structures, embedded word line structures or GAA (Gate-All-Around) structures are increasingly being adopted. When using these word line structures, how to improve the weak conductivity between the bit line structure and the active structure, and enhance the stability of the semiconductor structure, has become a crucial problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] This disclosure provides a semiconductor structure and manufacturing method, which at least helps to solve the problem of weak conductivity between bit line structures and active structures.

[0004] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate having bit lines extending along a first direction; a semiconductor channel located on the bit lines; a semiconductor doped layer located on the side of the bit lines, with the top surface of the semiconductor doped layer contacting the semiconductor channel; a word line extending along a second direction, the word line surrounding a portion of the semiconductor channel, with the bottom surface of the word line higher than the top surface of the bit line; a word line dielectric layer located between the word lines and the semiconductor channel; and an isolation layer located between the word lines and the bit lines, and between the word lines and the semiconductor doped layer.

[0005] In addition, in the first direction, the bit line has at least two rows of spaced semiconductor channels, and the semiconductor doped layer is located on both sides of the bit line.

[0006] In addition, there are at least two bit lines, and the semiconductor doped layer is located on one side of the bit lines.

[0007] Furthermore, the semiconductor doped layers of the two adjacent bit lines are located on different sides.

[0008] In addition, the material of the bit line includes metal; the semiconductor structure further includes: a dielectric layer located on the top surface of the bit line, and the semiconductor doped layer is also located on the side of the dielectric layer, and the semiconductor channel is located on the surface of the dielectric layer.

[0009] In addition, the substrate is a semiconductor substrate; the semiconductor structure further includes: a barrier layer, the barrier layer being located within the substrate and protruding above the substrate, and the semiconductor channel being located on the top surface of a portion of the barrier layer.

[0010] In addition, the isolation layer is also located on the top surface of the barrier layer exposed by the semiconductor channel, and the isolation layer is located between the word line and the barrier layer.

[0011] Additionally, the word line is located on the top surface of the barrier layer exposed by the semiconductor channel.

[0012] In addition, in the direction parallel to the second direction, the width of the bit line is 2 to 3.5 times the maximum width of the semiconductor channel.

[0013] In addition, the maximum width of the semiconductor channel parallel to the second direction ranges from 10 nm to 20 nm.

[0014] In addition, the semiconductor doped layer has N-type ions or P-type ions; the semiconductor channel includes: a channel region, the region of the semiconductor channel directly opposite the word line is the channel region, the channel region is doped with N-type ions or P-type ions; and a doped region, the region of the semiconductor channel outside the channel region is the doped region, the type of doped ions in the doped region is the same as the type of doped ions in the semiconductor doped layer.

[0015] Furthermore, the type of doped ions in the channel region is different from the type of doped ions in the semiconductor doped layer.

[0016] In addition, the orthogonal projection area of ​​the bit line on the substrate is 0.5 to 0.8 times that of the orthogonal projection area of ​​the semiconductor channel on the substrate.

[0017] In addition, the material of the semiconductor channel is the same as the material of the semiconductor doped layer; the material of the semiconductor channel includes silicon, germanium, or silicon germanide.

[0018] In addition, the word lines include spaced word lines, and the semiconductor structure further includes: a first isolation layer located between adjacent word lines; and a second isolation layer located on the word lines and on the first isolation layer, and the second isolation layer is also located on the side of the semiconductor channel away from the word lines.

[0019] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate having bit lines extending along a first direction; forming a semiconductor doped layer and a semiconductor channel, the semiconductor channel being located on the bit lines, the semiconductor doped layer being located on the side of the bit lines, and the top surface of the semiconductor doped layer being in contact with the semiconductor channel; forming a word line extending along a second direction and a word line dielectric layer, the word lines surrounding a portion of the semiconductor channel, and the bottom surface of the word lines being higher than the top surface of the bit lines, the word line dielectric layer being located between the word lines and the semiconductor channel; and forming an isolation layer, the isolation layer being located between the word lines and the bit lines and between the word lines and the semiconductor doped layer.

[0020] In addition, the process steps for forming the semiconductor doped layer and the semiconductor channel include: providing an initial semiconductor substrate and a first doped layer stacked together, wherein the first doped layer is doped with N-type ions or P-type ions and has bit lines; forming a semiconductor layer on the top surface of the first doped layer and the bit lines; patterning the semiconductor layer and the first doped layer, wherein the remaining semiconductor layer serves as the semiconductor channel and the remaining first doped layer serves as the semiconductor doped layer.

[0021] Additionally, a second doped layer is formed using a selective epitaxial process, and the second doped layer has trenches; before patterning the semiconductor layer and the first doped layer, the process further includes: forming a sacrificial layer that fills the trenches; and after patterning the semiconductor layer and the first doped layer, removing the sacrificial layer.

[0022] In addition, after forming the word line, the process further includes: performing a doping process on the semiconductor channel above the top surface of the word line, wherein the type of dopant ions in the doping process is the same as the type of dopant ions in the semiconductor doped layer.

[0023] The technical solution provided in this disclosure has at least the following advantages:

[0024] In the semiconductor structure technical solution provided in this disclosure embodiment, the semiconductor channel located on the bit line and the semiconductor doped layer located on the side of the bit line increase the contact area between the bit line structure and the active structure, which is beneficial to improving the problem of weak conductivity between the bit line structure and the active structure, and thus improving the stability of the semiconductor structure; the word line surrounds part of the semiconductor channel, that is, the semiconductor structure is a GAA structure. The GAA structure can realize the gate wrapping around the channel region of the semiconductor on all four sides, which can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size, reduce the area occupied by the word line in the vertical direction, and is beneficial to enhance gate control performance and improve the integration of the semiconductor structure.

[0025] Furthermore, in the first direction, the bit line has at least two rows of spaced semiconductor channels, which is beneficial to enhance the bit line control performance. Since the word line surrounds part of the semiconductor channel, it is equivalent to two word lines being controlled by the same bit line, which can enhance the bit line's control over the word line and further improve the stability of the semiconductor structure. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the accompanying drawings are not to be limited in scale. To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0028] Figure 2 A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0029] Figure 3 A schematic diagram of a semiconductor structure provided in another embodiment of this disclosure;

[0030] Figures 4 to 14 A schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0031] Figures 15-24A top view of each step in a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0032] Figures 25-36 A schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure provided in another embodiment of this disclosure;

[0033] Figures 37-49 This is a top view of each step in a method for forming a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0034] As can be seen from the background technology, current semiconductor structures suffer from the problem of insufficient conductivity between bitline structures and active structures.

[0035] Analysis revealed that the main reasons for the above problems include: In order to improve the integration density of integrated circuits, while increasing the operating speed of DRAM and reducing its power consumption, current DRAM structures mainly adopt buried word line structures or GAA structures. In the GAA structure, the word line structure surrounds the active structure and is located on the bit line structure. This results in an excessively small contact area between the bit line structure and the active structure, leading to a problem of weak conductivity between the bit line structure and the active structure in the semiconductor structure.

[0036] This disclosure provides a semiconductor structure, including: a substrate having a bit line extending along a first direction; a semiconductor channel located on the bit line; a semiconductor doped layer located on the side of the bit line, with its top surface in contact with the semiconductor channel; a word line extending along a second direction, the word line surrounding a portion of the semiconductor channel, with its bottom surface higher than the top surface of the bit line; a word line dielectric layer located between the word line and the semiconductor channel; and an isolation layer located between the word line and the bit line, and between the word line and the semiconductor doped layer. The semiconductor channel and the semiconductor doped layer constitute an active structure, i.e., the semiconductor doped layer serves as the source of the semiconductor structure. With the drain and semiconductor channel located on the bit line and the semiconductor doped layer located on the side of the bit line, the contact area between the bit line structure and the active structure is increased, which helps to improve the problem of weak conductivity between the bit line structure and the active structure, and thus helps to improve the stability of the semiconductor structure. The word line surrounds part of the semiconductor channel, that is, the semiconductor structure is a GAA structure. The GAA structure can realize that the gate wraps around the channel region of the semiconductor on all four sides, which can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size. It reduces the area occupied by the word line in the vertical direction, which helps to enhance gate control performance and improve the integration of the semiconductor structure.

[0037] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0038] refer to Figure 1 as well as Figure 2 , Figure 1 This is a schematic diagram of a semiconductor structure provided in one embodiment of the present disclosure. Figure 2 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. The semiconductor structure includes: a substrate 100 having a bit line 104 extending along a first direction; a semiconductor channel 110 located on the bit line 104; a semiconductor doped layer 101 located on the side of the bit line 104, with its top surface in contact with the semiconductor channel 110; a word line 130 extending along a second direction, the word line 130 surrounding a portion of the semiconductor channel 110, with its bottom surface higher than the top surface of the bit line 104; a word line dielectric layer 131 located between the word line 130 and the semiconductor channel 110; and an isolation layer 120 located between the word line 130 and the bit line 104, and between the word line 130 and the semiconductor doped layer 101.

[0039] In some embodiments, the substrate 100 is a semiconductor substrate. Specifically, the semiconductor substrate may be any one of a silicon substrate, a germanium substrate, a germanium-silicon substrate, or a silicon carbide substrate, including but not limited to a silicon substrate, a germanium substrate, a germanium-silicon substrate, or a silicon carbide substrate.

[0040] In some embodiments, in the first direction, the bit line 104 has at least two rows of spaced semiconductor channels 110, the word line 130 surrounds a portion of the semiconductor channels 110, and the semiconductor doped layer 101 is located on both sides of the bit line 104, which increases the contact area between the bit line 104 and the semiconductor doped layer 101, which helps to improve the problem of weak conductivity between the bit line structure and the active structure, and thus helps to improve the stability of the semiconductor structure.

[0041] In some embodiments, the bit line 104 is made of a metal, specifically cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum. The metal itself has low resistance, reducing the contact resistance between the bit line 104 and the semiconductor doped layer 101, effectively avoiding leakage current problems and improving the conductivity of the bit line 104 and the semiconductor doped layer 101. The bit line 104 can be a single-layer structure or a stacked structure. In other embodiments, the bit line is made of the same material as the substrate, and contains dopant ions of the same type as those in the semiconductor doped layer. These dopant ions, acting as charge carriers, can improve migration and diffusion between the bit line and the semiconductor doped layer, further enhancing the conductivity of the bit line and the semiconductor doped layer. Since the bit line is made of the same material as the substrate, it can be considered an extension of the substrate, simplifying the process flow and avoiding interface defects caused by contact between different media.

[0042] In some embodiments, the semiconductor structure further includes a barrier layer 103, which is located within and protrudes above the substrate 100. A semiconductor channel 110 is located on a portion of the top surface of the barrier layer 103. The barrier layer 103 is used to block ion diffusion between the bit line 104 and the substrate 100. The ions include doped ions or metal ions. The barrier layer 103 is located within and protrudes above the substrate 100, which means that the bottom surface of the bit line 104 in contact with the barrier layer 103 is higher than the top surface of the substrate 100 in contact with the semiconductor doped layer 101. This effectively prevents metal ions or doped ions from the bit line 104 from diffusing into the substrate 100, which is beneficial for improving the conductivity of the bit line 104 and the semiconductor doped layer 101. The material of the barrier layer 103 is silicon nitride. In other embodiments, the material of the barrier layer can be silicon dioxide or other materials with high dielectric constants.

[0043] In some embodiments, the semiconductor structure further includes: a dielectric layer 105 located on the top surface of the bit line 104, and a semiconductor doped layer 101 located on the side of the dielectric layer 105; a semiconductor channel 110 located on the surface of the dielectric layer 105; the upper surface of the dielectric layer 105 in contact with the semiconductor channel 110 is not higher than the upper surface of the semiconductor doped layer 101 in contact with the semiconductor channel 110, which is beneficial to the formation of the semiconductor channel 110, thereby improving the integrity of the semiconductor channel 110 and thus improving the conductivity of the semiconductor channel 110.

[0044] In some embodiments, the upper surface of the dielectric layer 105 in contact with the semiconductor channel 110 is lower than the upper surface of the semiconductor doped layer 101 in contact with the semiconductor channel 110. The dielectric layer 105 is used to prevent the diffusion of metal ions within the bit line 104. The dielectric layer 105 can also be considered as part of the bit line 104. The material of the dielectric layer 105 can be any of titanium nitride or other nitrogen-containing metal materials, including but not limited to. In other embodiments, the upper surface of the dielectric layer in contact with the semiconductor channel is flush with the upper surface of the semiconductor doped layer in contact with the semiconductor channel.

[0045] In some embodiments, the width of the bit line 104 parallel to the second direction is 2 to 3.5 times the maximum width of the semiconductor channel 110, specifically 2, 2.8, 3.3, or 3.5 times. If the width of the bit line 104 is less than twice the maximum width of the semiconductor channel 110, the width of the word line 130 between adjacent semiconductor channels 110 is smaller. Since the word line 130 does not have enough area to play a role, the control capability of the word line 130 is reduced. If the width of the bit line 104 is greater than 3.5 times the maximum width of the semiconductor channel 110, it is equivalent to increasing the width of the semiconductor structure in the second direction, thereby reducing the integration density of the semiconductor device.

[0046] In some embodiments, the maximum width of the semiconductor channel 110 parallel to the second direction ranges from 10nm to 20nm, specifically 10nm, 13nm, 15nm, or 20nm; the projected area of ​​the bit line 104 on the substrate 100 ranges from 0.5 to 0.8 times the projected area of ​​the semiconductor channel 110 on the substrate 100, specifically 0.5, 0.6, 0.7, or 0.8 times, ensuring the contact area between the bit line 104 and the semiconductor channel 110, which helps to improve the problem of weak conductivity between the bit line structure and the active structure, thereby improving the stability of the semiconductor structure.

[0047] In some embodiments, the material of the semiconductor channel 110 and the semiconductor doped layer 101 may be the same, specifically silicon, germanium, or silicon germanide, thereby improving the interface performance between the semiconductor channel 110 and the semiconductor doped layer 101, which is beneficial for improving interface state defects and thus improving the electrical performance of the semiconductor structure. In other embodiments, the material of the semiconductor channel and the material of the semiconductor doped layer may be different.

[0048] In some embodiments, the semiconductor channel 110 may include: a channel region 111, the region of the semiconductor channel 110 opposite to the word line 130, wherein the channel region 111 is doped with N-type ions or P-type ions; and a doped region 112, the region of the semiconductor channel 110 other than the channel region 111, wherein the type of doped ions in the doped region 112 is the same as the type of doped ions in the semiconductor doped layer 101.

[0049] In some embodiments, the type of doped ions in the channel region 111 is different from the type of doped ions in the semiconductor doped layer 101, which is equivalent to a junction transistor. Here, "junction" refers to the presence of a PN junction, that is, the transistor formed by the semiconductor channel 110 has a PN junction. It is a device that uses majority carriers as conductors, thus avoiding the problem of minority carrier storage and diffusion. Moreover, the majority carrier velocity is high, which is beneficial to improving the conductivity of the semiconductor channel 110.

[0050] In other embodiments, the type of dopant ions in the channel region is the same as the type of dopant ions in the semiconductor doped layer, which is equivalent to a junctionless transistor. Here, "junctionless" refers to the absence of a PN junction, meaning that the transistor formed by the semiconductor channel does not have a PN junction. On the one hand, there is no need to perform additional doping on the doped region, thus avoiding the problem of difficult-to-control doping processes in the doped region, especially as transistor sizes further shrink, where additional doping of the doped region makes it even more difficult to control the doping concentration. On the other hand, since the device is a junctionless transistor, it is beneficial to avoid the phenomenon of creating ultra-steep PN junctions at the nanoscale using ultra-steep source-drain concentration gradient doping processes. Therefore, it can avoid problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes, which helps to suppress short-channel effects and allows it to still operate at the scale of a few nanometers, thus contributing to further improving the integration density and electrical performance of the semiconductor structure. It is understood that the additional doping here refers to doping performed to make the type of dopant ions in the doped region different from the type of dopant ions in the channel region.

[0051] In some embodiments, the dopant ion is an N-type ion or a P-type ion. Specifically, the N-type ion can be a phosphorus ion, an arsenic ion, or an antimony ion, and the P-type ion can be a boron ion, an indium ion, or a boron fluoride ion.

[0052] In some embodiments, the material of the semiconductor doped layer 101 may be the same as the material of the substrate 100, specifically silicon, germanium, or silicon germanide. The semiconductor doped layer 101 and the substrate 100 may be formed from the same initial substrate, forming a single integrated structure. This improves the interface performance between the substrate 100 and the semiconductor doped layer 101, which helps to mitigate interface state defects and further improves the electrical performance of the semiconductor structure. In other embodiments, the material of the semiconductor doped layer may be different from the material of the semiconductor channel.

[0053] In other embodiments, the materials of the semiconductor doped layer and the bit lines can be the same as the substrate material. In this way, the semiconductor doped layer, bit lines and substrate can be formed from the same initial substrate, and the semiconductor doped layer, bit lines and substrate are an integral structure, thereby improving the interface performance between the bit lines and the semiconductor doped layer, which is beneficial to improving interface state defects, and further improving the electrical performance of the semiconductor structure.

[0054] In some embodiments, the material of the isolation layer 120 includes, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride; the isolation layer 120 may be a single-layer structure or a multilayer structure.

[0055] In some embodiments, word lines 130 include spaced word lines; the material of word lines 130 includes, but is not limited to, one or more of polysilicon, titanium nitride, tantalum nitride, copper, tungsten, or aluminum; word lines 130 can be a single-layer structure or a multilayer structure; word line dielectric layer 131 is used to isolate word lines 130 from semiconductor channels 110 to form electrical insulation; the material of word line dielectric layer 131 includes, but is not limited to, one or more of silicon oxide, silicon nitride, or silicon oxynitride; word line dielectric layer 131 can be a single-layer structure or a multilayer structure.

[0056] In some embodiments, the bottom surface of word line 130 is higher than the top surface of bit line 104, that is, there is an isolation layer 120 between word line 130 and bit line 104, which can ensure that word line 130 and bit line 104 are electrically insulated, and at the same time avoid leakage current and capacitance effect, which is beneficial to improving the stability of semiconductor structure.

[0057] In some embodiments, the semiconductor structure further includes: a first isolation layer (not shown) located between adjacent word lines 130; and a second isolation layer 142 located on the word lines 130 and on the first isolation layer, and the second isolation layer 142 is also located on the side of the semiconductor channel 110 away from the word lines 130.

[0058] In some embodiments, the first isolation layer and the second isolation layer 142 are integrally formed, which can simplify the process flow and improve the interface performance between the first isolation layer 141 and the second isolation layer 142, thereby improving interface state defects and further improving the electrical performance of the semiconductor structure. The materials of the first isolation layer and the second isolation layer 142 include, but are not limited to, one or more of silicon oxide, silicon nitride, or silicon oxynitride. The first isolation layer and the second isolation layer 142 can be a single-layer structure or a stacked structure.

[0059] In the semiconductor structure technical solution provided in this disclosure embodiment, the semiconductor channel 110 is located on the bit line 104 and the semiconductor doped layer 101 is located on the side of the bit line 104, which increases the contact area between the bit line structure and the active structure. This is beneficial to improving the problem of weak conductivity between the bit line structure and the active structure, and thus improving the stability of the semiconductor structure. The word line 130 surrounds part of the semiconductor channel 110, that is, the semiconductor structure is a GAA structure. The GAA structure can realize the gate wrapping around the channel region of the semiconductor on all four sides. It can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size, reduce the area occupied by the word line 130 in the vertical direction, and is beneficial to enhance the gate control performance and improve the integration of the semiconductor structure.

[0060] Furthermore, in the first direction, the bit line 104 has at least two rows of spaced semiconductor channels 110, which helps to enhance the electrical contact performance between the bit line 104 and the semiconductor channels 110, and further improve the stability of the semiconductor structure.

[0061] Another embodiment of this disclosure also provides a semiconductor structure. The semiconductor structure provided in this other embodiment is substantially the same as the semiconductor structure provided in the foregoing embodiments, with the main difference being that there are at least two bit lines and the semiconductor doping layer is located on one side of the bit lines.

[0062] Figure 3 This is a schematic diagram of a semiconductor structure provided in another embodiment of the present disclosure, which will be described below in conjunction with... Figure 3 The semiconductor structure provided in another embodiment of this disclosure will be described in detail below. The parts that are the same as or corresponding to those in the above embodiments will not be described in detail below.

[0063] refer to Figure 3The semiconductor structure includes: a substrate 200 having a bit line 204 extending along a first direction; a semiconductor channel 210 located on the bit line 204; a semiconductor doped layer 201 located on the side of the bit line 204, with its top surface in contact with the semiconductor channel 210; a word line 230 extending along a second direction, the word line 230 surrounding a portion of the semiconductor channel 210, with its bottom surface higher than the top surface of the bit line 204; a word line dielectric layer 231 located between the word line 230 and the semiconductor channel 210; and an isolation layer 220 located between the word line 230 and the bit line 204, and between the word line 230 and the semiconductor doped layer 201.

[0064] In some embodiments, there are at least two bit lines 204, with a semiconductor doped layer 201 located on one side of the bit line 204, and the semiconductor doped layers 201 of two adjacent bit lines 204 located on different sides; an isolation layer 220 is also located on the top surface of the barrier layer 203 exposed by the semiconductor channel 210, and the isolation layer 220 is located between the word line 230 and the barrier layer 203; the word line 230 is located on the top surface of the barrier layer 203 exposed by the semiconductor channel 110.

[0065] In the semiconductor structure provided in this embodiment, the semiconductor channel 210 located on the bit line 204 and the semiconductor doped layer 201 located on the side of the bit line 204 increase the contact area between the bit line structure and the active structure, which helps to improve the problem of weak conductivity between the bit line structure and the active structure, and thus helps to improve the stability of the semiconductor structure. The word line 230 surrounds part of the semiconductor channel 210, that is, the semiconductor structure is a GAA structure. The GAA structure can realize the gate wrapping around the channel region of the semiconductor on all four sides, which can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size, reduce the area occupied by the word line 230 in the vertical direction, which helps to enhance the gate control performance and improve the integration of the semiconductor structure.

[0066] Accordingly, one embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.

[0067] Figures 4 to 14 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure manufacturing method provided in an embodiment of the present invention. Figures 15 to 24 This is a top view of each step in the manufacturing method of a semiconductor structure provided in an embodiment of the present invention. The manufacturing method of the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0068] refer to Figures 4 to 9 as well as Figures 15 to 19A substrate 100 is provided, on which a bit line 104 extends along a first direction is provided; a semiconductor doped layer 101 and a semiconductor channel 110 are formed, the semiconductor channel 110 is located on the bit line 104, the semiconductor doped layer 101 is located on the side of the bit line 104, and the top surface of the semiconductor doped layer 101 is in contact with the semiconductor channel 110.

[0069] Specifically, the process steps for forming the semiconductor doped layer 101 and the semiconductor channel 110 include: providing an initial semiconductor substrate 108 and a first doped layer 109 stacked together, wherein the first doped layer 109 is doped with N-type ions or P-type ions and has bit lines 104; forming a semiconductor layer on the top surface of the first doped layer 109 and the bit lines 104; patterning the semiconductor layer and the first doped layer 109, wherein the remaining semiconductor layer serves as the semiconductor channel 110 and the remaining first doped layer 109 serves as the semiconductor doped layer 101.

[0070] More specifically, see reference Figure 4 An initial semiconductor substrate is provided, and a portion of the initial semiconductor substrate is doped with N-type or P-type ions. The portion of the initial semiconductor substrate is then used as the first doped layer 109, and the initial semiconductor substrate outside the first doped layer 109 is used as the initial semiconductor substrate 108.

[0071] In some embodiments, the initial semiconductor substrate is made of a semiconductor material. Specifically, the semiconductor material can be any one of silicon, germanium, silicon germanium, or silicon carbide.

[0072] In some embodiments, the doping process involves ion implantation to introduce dopant ions into the first doped layer 109. The dopant ions are either N-type or P-type ions. Specifically, N-type ions can be phosphorus ions, arsenic ions, or antimony ions, and P-type ions can be boron ions, indium ions, or boron fluoride ions.

[0073] refer to Figure 5 as well as Figure 15 A first doped layer 109 and an initial semiconductor substrate 108 are patterned, and a first trench 102 is formed within the initial semiconductor substrate 108. The sidewalls of the first trench 102 expose a portion of the sidewalls of the initial semiconductor substrate 108. This serves two purposes: firstly, it prevents ions from diffusing into the initial semiconductor substrate 108 within subsequently formed bit lines, thereby reducing the ion concentration within the bit lines and further improving the conductivity of the bit lines; secondly, it ensures that the area of ​​the subsequently formed bit line structure is increased, thereby improving the conductivity of the bit lines. In other embodiments, the first doped layer is patterned to form the first trench, and the bottom of the first trench exposes the surface of the initial semiconductor substrate.

[0074] In some embodiments, in the extension direction parallel to the subsequently formed word lines, the width of the first trench 102 is 2 to 3.5 times the maximum width of the subsequently formed semiconductor channel, specifically 2, 2.8, 3.3, or 3.5 times. The subsequently formed bit lines are located within the first trench 102, which is equivalent to the width of the first trench 102 being equal to the width of the subsequently formed bit lines. In the subsequently formed semiconductor structure, if the width of the bit lines is less than twice the maximum width of the semiconductor channel, the width of the word lines between adjacent semiconductor channels is small. Since the word lines do not have sufficient area to function, the control capability of the word lines is reduced. If the width of the bit lines is greater than 3.5 times the maximum width of the semiconductor channel, it is equivalent to increasing the width of the semiconductor structure in the second direction, thereby reducing the integration density of the semiconductor device.

[0075] refer to Figure 6 as well as Figure 16 A barrier layer 103, a bit line 104, and a dielectric layer 105 are sequentially formed on an initial semiconductor substrate 108, and the stacked barrier layer 103, bit line 104, and dielectric layer 105 are also located within a first trench 102.

[0076] In some embodiments, the barrier layer 103 is used to block ion diffusion between the bit line 104 and the initial semiconductor substrate 108. The ions include doped ions or metal ions. The bottom surface of the bit line 104 in contact with the barrier layer 103 is higher than the top surface of the initial semiconductor substrate 108 in contact with the first doped layer 109. This effectively prevents metal ions or doped ions from the bit line 104 from diffusing into the initial semiconductor substrate 108, which is beneficial for improving the conductivity of the bit line 104 and the first doped layer 109. The barrier layer 103 is made of silicon nitride. In other embodiments, the bottom surface of the bit line in contact with the barrier layer is flush with the top surface of the initial semiconductor substrate in contact with the first doped layer. The barrier layer can be made of silicon dioxide or other materials with high dielectric constants.

[0077] In some embodiments, the opposite sides of the bit line 104 have a first doped layer 109 along the extension direction of the subsequent word line formation, which increases the contact area between the bit line 104 and the first doped layer 109, which helps to improve the problem of weak conductivity between the bit line structure and the active structure, and thus helps to improve the stability of the semiconductor structure.

[0078] In some embodiments, the material of the bit line 104 includes a metal, specifically cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum. The metal itself has low resistance, reducing the contact resistance between the bit line 104 and the first doped layer 109, effectively avoiding leakage current problems and improving the conductivity between the bit line 104 and the semiconductor doped layer 101. The bit line 104 can be a single-layer structure or a stacked structure. In other embodiments, the material of the bit line is the same as the substrate material, and the bit line contains dopant ions of the same type as the doped ions in the semiconductor doped layer. These doped ions, acting as charge carriers, can improve migration and diffusion between the bit line and the first doped layer, thus improving the conductivity between the bit line and the first doped layer. Furthermore, since the bit line material is the same as the substrate material, on the one hand, the first doped layer, the bit line, and the initial semiconductor substrate can be formed from the same initial substrate, forming a single structure. This improves the interface performance between the bit line and the first doped layer, helps improve interface state defects, and further improves the electrical performance of the semiconductor structure. On the other hand, it simplifies the process flow.

[0079] In some embodiments, the surface of the dielectric layer 105 is lower than the surface of the first doped layer 109, effectively avoiding lattice defects in the subsequently formed semiconductor channel, thereby improving the conductivity of the semiconductor channel. The dielectric layer 105 is used to prevent the diffusion of metal ions within the bit line 104. The dielectric layer 105 can also be considered as part of the bit line 104, and the material of the dielectric layer 105 can be any of titanium nitride or other nitrogen-containing metal materials, including but not limited to. In other embodiments, the surface of the dielectric layer is flush with the surface of the first doped layer. This increases the area of ​​the bit line and the contact area between the first doped layer and the bit line, which improves the conductivity of the bit line and further enhances the conductivity of the semiconductor structure.

[0080] refer to Figure 7 as well as Figure 17 A second doped layer 106 is formed using a selective epitaxial process, and the second doped layer 106 has trenches 122.

[0081] In some embodiments, the second doped layer 106 is a semiconductor layer containing doped ions. The type of doped ions in the second doped layer 106 is different from the type of doped ions in the first doped layer 109. That is, the semiconductor structure formed by the second doped layer 106 and the first doped layer 109 is a junction transistor. Here, "junction" refers to the presence of a PN junction, meaning that the transistor formed by the subsequent semiconductor channel has a PN junction. This is a majority carrier-based conductive device, thus avoiding the problem of minority carrier storage and diffusion. Moreover, the high velocity of majority carriers is beneficial for improving the conductivity of the semiconductor channel. In other embodiments, the type of doped ions in the second doped layer is the same as the type of doped ions in the first doped layer. That is, the semiconductor structure formed by the second doped layer and the first doped layer is a junctionless transistor. Here, "junctionless" refers to the absence of a PN junction, meaning that the transistor formed by the semiconductor channel does not have a PN junction. On the one hand, there is no need to perform additional doping on the doped region, thus avoiding the problem of difficulty in controlling the doping process of the doped region. Especially as the transistor size shrinks further, if additional doping is performed on the doped region, the doping concentration becomes even more difficult to control. On the other hand, since the device is a junctionless transistor, it is beneficial to avoid the phenomenon of creating an ultra-steep PN junction in the nanoscale range by using an ultra-steep source-drain concentration gradient doping process. Therefore, it can avoid problems such as threshold voltage drift and leakage current increase caused by doping abrupt changes, which is beneficial to suppressing short-channel effects. It can still work in the range of a few nanometers, thus helping to further improve the integration density and electrical performance of semiconductor structures.

[0082] In some embodiments, during the process step of forming the second doped layer 106, N-type ions are in-situ doped. In other embodiments, during the process step of forming the second doped layer, P-type ions are in-situ doped.

[0083] In some embodiments, the source materials used in the selective epitaxial growth process include a source gas, an etching gas (hydrogen chloride), and a dopant ion source gas. The dopant ion source gas is used to provide dopant ions. The source gas can be a silicon source gas, specifically silane, dichlorosilane, dichlorosilane, or trichlorosilane. In other embodiments, the source gas can also be a germanium source gas, specifically germanane.

[0084] In some embodiments, the doped ion source gas is an N-type ion source gas, which may specifically be phosphine, arsine, or antimony hydride. In other embodiments, the doped ion source gas is a P-type ion source gas, which may specifically be borane, boron trifluoride, or diborane.

[0085] In some embodiments, the material of the second doped layer 106 is the same as that of the initial semiconductor substrate 108, specifically silicon, germanium, or silicon germanide. This simplifies the manufacturing process; furthermore, using the same material results in a lattice mismatch factor of 0, effectively avoiding lattice defects and increased internal resistance within the second doped layer 106, thus improving its conductivity. In other embodiments, the material of the second doped layer may differ from that of the initial semiconductor substrate.

[0086] refer to Figure 8 as well as Figure 18 A sacrificial layer 107 is formed, which fills the trench 122.

[0087] refer to Figure 9 as well as Figure 19 The second doped layer 106, the first doped layer 109 and the initial semiconductor substrate 108 are patterned. The remaining second doped layer 106 serves as the semiconductor channel 110, the remaining first doped layer 109 serves as the semiconductor doped layer 101, and the remaining initial semiconductor substrate 108 serves as the substrate 100. The sacrificial layer 107 is removed.

[0088] In some embodiments, in the first direction, the bit line 104 has at least two rows of spaced semiconductor channels 110, and the subsequently formed word lines surround a portion of the semiconductor channels 110. The semiconductor doped layer 101 is located on both sides of the bit line 104, which increases the contact area between the bit line 104 and the semiconductor doped layer 101. This helps to improve the problem of weak conductivity between the bit line structure and the active structure, and thus helps to improve the stability of the semiconductor structure.

[0089] In some embodiments, the maximum width of the semiconductor channel 110 parallel to the second direction ranges from 10nm to 20nm, specifically 10nm, 13nm, 15nm, or 20nm; the projected area of ​​the bit line 104 on the substrate 100 ranges from 0.5 to 0.8 times the projected area of ​​the semiconductor channel 110 on the substrate 100, specifically 0.5, 0.6, 0.7, or 0.8 times, ensuring the contact area between the bit line 104 and the semiconductor channel 110, which helps to improve the problem of weak conductivity between the bit line structure and the active structure, thereby improving the stability of the semiconductor structure.

[0090] refer to Figure 10 as well as Figure 20 An isolation layer 120 is formed, which is located on the side of the bit line 104 and on the side of the semiconductor doped layer 101 away from the bit line 104.

[0091] In some embodiments, the material of the isolation layer 120 includes, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride; the isolation layer 120 may be a single-layer structure or a multilayer structure.

[0092] refer to Figure 11 , Figure 12 as well as Figure 21 , Figure 22 A word line 130 and a word line dielectric layer 131 extending along the second direction are formed. The word line 130 and the word line dielectric layer 131 are located on the isolation layer 120. The word line 130 surrounds a portion of the semiconductor channel 110, and the bottom surface of the word line 130 is higher than the top surface of the bit line 104. The word line dielectric layer 131 is located between the word line 130 and the semiconductor channel 110.

[0093] Specifically, refer to Figure 11 as well as Figure 21 A word line dielectric layer 131 and a gate conductive layer 132 are formed on the isolation layer 120. The word line dielectric layer 131 is located on the side of a semiconductor channel 110 of a certain thickness and surrounds the semiconductor channel 110. The gate conductive layer 132 is located on the side of the gate dielectric layer 131 corresponding to the semiconductor channel 110 of a certain thickness and surrounds the gate dielectric layer 131.

[0094] In some embodiments, the material of the gate conductive layer 132 includes, but is not limited to, one or more of polysilicon, titanium nitride, tantalum nitride, copper, tungsten, or aluminum; the gate conductive layer 132 can be a single-layer structure or a stacked structure; the word line dielectric layer 131 is used to isolate the word line 130 from the semiconductor channel 110 to form electrical insulation; the material of the word line dielectric layer 131 includes, but is not limited to, one or more of silicon oxide, silicon nitride, or silicon oxynitride; the word line dielectric layer 131 can be a single-layer structure or a stacked structure.

[0095] refer to Figure 12 as well as Figure 22 The patterned gate conductive layer 132 is used as the remaining gate conductive layer 132 as word lines 130.

[0096] In some embodiments, the bottom surface of word line 130 is higher than the top surface of bit line 104, that is, there is an isolation layer 120 between word line 130 and bit line 104, which can ensure that word line 130 and bit line 104 are electrically insulated, and at the same time avoid leakage current and capacitance effect, which is beneficial to improving the stability of semiconductor structure.

[0097] In other embodiments, a substrate is provided having bit lines extending along a first direction; a semiconductor doped layer and an isolation layer are sequentially formed on the substrate, the semiconductor doped layer being located on the side of the bit lines and the isolation layer also being located on the bit lines; a word line and a word line dielectric layer are formed extending along a second direction, the word line and the word line dielectric layer being located on the isolation layer, the word line surrounding the word line dielectric layer, and the bottom surface of the word line being higher than the top surface of the bit line; a second trench is formed, the sidewalls of the second trench exposing the word line dielectric layer and the isolation layer, and the bottom of the second trench exposing the semiconductor doped layer and the bit lines; a semiconductor channel is formed, the semiconductor channel being located within the second trench, the semiconductor channel being located on the bit lines, and the top surface of the semiconductor doped layer contacting the semiconductor channel.

[0098] refer to Figure 13 as well as Figure 23 A first isolation layer (not shown in the figure) and a second isolation layer 142 are formed. The first isolation layer is located between adjacent word lines 130. The second isolation layer 142 is located on the word lines 130 and on the first isolation layer, and the second isolation layer 142 is also located on the side of the semiconductor channel 110 away from the word lines 130.

[0099] In some embodiments, the first isolation layer and the second isolation layer 142 are integrally formed, which can simplify the process flow and improve the interface performance of the first isolation layer and the second isolation layer 142, which is beneficial to improve interface state defects and further improve the electrical performance of the semiconductor structure. The materials of the first isolation layer and the second isolation layer 142 include, but are not limited to, one or more of silicon oxide, silicon nitride or silicon oxynitride. The first isolation layer and the second isolation layer 142 can be a single-layer structure or a stacked structure.

[0100] refer to Figure 14 as well as Figure 24 The semiconductor channel 110 above the top surface of word line 130 is doped, and the type of dopant ions in the doping process is the same as the type of dopant ions in semiconductor doped layer 101.

[0101] In some embodiments, the semiconductor channel 110 includes: a channel region 111, the region of the semiconductor channel 110 opposite to the word line 130 is the channel region 111, and the channel region 111 is doped with N-type ions or P-type ions; and a doped region 112, the region of the semiconductor channel 110 other than the channel region 111 is the doped region 112, and the type of doped ions in the doped region 112 is the same as the type of doped ions in the semiconductor doped layer 101.

[0102] In some embodiments, the type of doped ions in the channel region 111 is different from the type of doped ions in the semiconductor doped layer 101, which is equivalent to a junction transistor. Here, "junction" refers to the presence of a PN junction, that is, the transistor formed by the semiconductor channel 110 has a PN junction. It is a device that uses majority carriers as conductors, thus avoiding the problem of minority carrier storage and diffusion. Moreover, the majority carrier velocity is high, which is beneficial to improving the conductivity of the semiconductor channel 110.

[0103] In other embodiments, the type of dopant ions in the channel region is the same as the type of dopant ions in the semiconductor doped layer, which is equivalent to a junctionless transistor. Here, "junctionless" refers to the absence of a PN junction, meaning that the transistor composed of semiconductor channels does not have a PN junction. On the one hand, there is no need to perform additional doping on the doped region, thus avoiding the problem of difficult-to-control doping processes in the doped region. Especially as the transistor size further shrinks, if additional doping is performed on the doped region, the doping concentration becomes even more difficult to control. On the other hand, since the device is a junctionless transistor, it is beneficial to avoid the phenomenon of creating ultra-steep PN junctions at the nanoscale using ultra-steep source-drain concentration gradient doping processes. Therefore, it can avoid problems such as threshold voltage drift and increased leakage current caused by doping abrupt changes, which is beneficial to suppressing short-channel effects. It can still operate at the scale of a few nanometers, thus helping to further improve the integration density and electrical performance of the semiconductor structure.

[0104] In some embodiments, the dopant ion is an N-type ion or a P-type ion. Specifically, the N-type ion can be a phosphorus ion, an arsenic ion, or an antimony ion, and the P-type ion can be a boron ion, an indium ion, or a boron fluoride ion.

[0105] In the semiconductor structure provided in this embodiment, the semiconductor channel 110 located on the bit line 104 and the semiconductor doped layer 101 located on the side of the bit line 104 increase the contact area between the bit line structure and the active structure, which helps to improve the problem of weak conductivity between the bit line structure and the active structure, and thus helps to improve the stability of the semiconductor structure. The word line 130 surrounds part of the semiconductor channel 110, that is, the semiconductor structure is a GAA structure. The GAA structure can realize the gate wrapping around the channel region of the semiconductor on all four sides, which can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size, reduce the area occupied by the word line 110 in the vertical direction, which helps to enhance the gate control performance and improve the integration of the semiconductor structure.

[0106] Furthermore, in the first direction, the bit line has at least two rows of spaced semiconductor channels, which is beneficial to enhance the bit line control performance. Since the word line surrounds part of the semiconductor channel, it is equivalent to two word lines being controlled by the same bit line, which can enhance the bit line's control over the word line and further improve the stability of the semiconductor structure.

[0107] Figures 25 to 36 This is a schematic diagram of the structure corresponding to each step in the method for fabricating a semiconductor structure according to another embodiment of this disclosure. Figures 37 to 49 The following is a top view of each step in the method for preparing a semiconductor structure according to another embodiment of this disclosure. The parts that are the same as or corresponding to those in the above embodiment will not be described in detail below.

[0108] refer to Figures 25 to 33 as well as Figures 37 to 44 A substrate 200 is provided, on which a bit line 204 extending along a first direction is formed, forming a semiconductor doped layer 201 and a semiconductor channel 210. The semiconductor channel 210 is located on the bit line 204, the semiconductor doped layer 201 is located on the side of the bit line 204, and the top surface of the semiconductor doped layer 201 is in contact with the semiconductor channel 210.

[0109] Specifically, the process steps for forming the semiconductor doped layer 201 and the semiconductor channel 210 include: providing an initial semiconductor substrate 208 and a first doped layer 209 stacked together, wherein the first doped layer 209 is doped with N-type ions or P-type ions and has bit lines 204; forming a semiconductor layer on the top surface of the first doped layer 209 and the bit lines 204; patterning the semiconductor layer and the first doped layer 209, wherein the remaining semiconductor layer serves as the semiconductor channel 210 and the remaining first doped layer 209 serves as the semiconductor doped layer 201.

[0110] refer to Figure 25 An initial semiconductor substrate is provided, and a portion of the initial semiconductor substrate is doped with N-type or P-type ions. The portion of the initial semiconductor substrate is then used as the first doped layer 209, and the initial semiconductor substrate outside the first doped layer 209 is used as the initial semiconductor substrate 208.

[0111] refer to Figure 26 as well as Figure 37 The first doped layer 209 and the initial semiconductor substrate 208 are patterned, and a first trench 202 is formed in the initial semiconductor substrate 208.

[0112] refer to Figure 27 as well as Figure 38 A first barrier layer 213, a conductive layer 214, and a dielectric layer 205 are sequentially formed on an initial semiconductor substrate 208, and the stacked first barrier layer 213, conductive layer 214, and dielectric layer 205 are also located within a first trench 202.

[0113] In some embodiments, the material of the conductive layer 214 includes a metal, specifically cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum. The metal itself has low resistance, which reduces the contact resistance between the conductive layer 214 and the first doped layer 209, effectively avoiding leakage current problems and improving the conductivity of the conductive layer 214 and the first doped layer 209. The conductive layer 214 can be a single-layer structure or a stacked structure.

[0114] In some embodiments, the first barrier layer 213 is used to block the diffusion of metal ions between the conductive layer 214 and the initial semiconductor substrate 208; the bottom surface of the conductive layer 214 in contact with the first barrier layer 213 is higher than the top surface of the initial semiconductor substrate 208 in contact with the first doped layer 209, which can effectively prevent metal ions of the conductive layer 214 from diffusing into the initial semiconductor substrate 208, and is beneficial to improving the conductivity of the conductive layer 214 and the first doped layer 209; the material of the first barrier layer 213 is silicon nitride. In other embodiments, the material of the first barrier layer can be silicon dioxide or other materials with high dielectric constant.

[0115] refer to Figure 28 as well as Figure 39 A third trench 252 is formed that penetrates the conductive layer 214 and the dielectric layer 205. The bottom of the third trench exposes the first barrier layer 213, and the remaining conductive layer 214 serves as the bit line 104.

[0116] In some embodiments, the third trench 252 is located within the first barrier layer 213 to create an open circuit in the conductive layer 214, thereby providing electrical insulation and preventing two adjacent bit lines from forming a path, which is equivalent to forming two transistors. In other embodiments, the bottom surface of the third trench is flush with the top surface of the first barrier layer.

[0117] refer to Figure 29 as well as Figure 40 A second barrier layer 223 is formed, which fills the third trench 252. The second barrier layer 223 and the first barrier layer 213 together constitute a barrier layer 203.

[0118] In some embodiments, the second barrier layer 223 is used to block the diffusion of metal ions between adjacent bit lines 204. The material of the second barrier layer 223 is the same as that of the first barrier layer 213, thereby improving the interface performance between the second barrier layer 223 and the first barrier layer 213, which is beneficial for improving interface state defects and thus improving the electrical performance of the semiconductor structure. In other embodiments, the material of the second barrier layer may be different from that of the first barrier layer.

[0119] In other embodiments, a third barrier layer is formed on the initial semiconductor substrate, and the third barrier layer is also located in the trench to form a fourth trench. The sidewalls of the fourth trench expose the surface of the first doped layer, and the bottom surface of the fourth trench is higher than the bottom surface of the first doped layer. A stacked bit line and a dielectric layer are sequentially formed on the initial semiconductor substrate, and the stacked bit line and dielectric layer are also located in the fourth trench. The remaining third barrier layer serves as a barrier layer.

[0120] In some embodiments, the subsequent semiconductor structure is as follows: Figures 30 to 36 The method for forming the structural diagrams corresponding to each step is the same as in the previous embodiment. Figures 7 to 14 The methods for forming the structural schematic diagrams corresponding to each step are the same or similar, therefore the subsequent semiconductor structures are as follows: Figures 30 to 36 The methods for forming the structural diagrams corresponding to each step are not described in detail.

[0121] In some embodiments, there are at least two bit lines 204, with a semiconductor doped layer 201 located on one side of the bit line 204, and the semiconductor doped layers 201 of two adjacent bit lines 204 located on different sides; an isolation layer 220 is also located on the top surface of the barrier layer 203 exposed by the semiconductor channel 210, and the isolation layer 220 is located between the word line 230 and the barrier layer 203; the word line 230 is located on the top surface of the barrier layer 203 exposed by the semiconductor channel 110.

[0122] In the semiconductor structure provided in this embodiment, the semiconductor channel 210 located on the bit line 204 and the semiconductor doped layer 201 located on the side of the bit line 204 increase the contact area between the bit line structure and the active structure, which helps to improve the problem of weak conductivity between the bit line structure and the active structure, and thus helps to improve the stability of the semiconductor structure. The word line 230 surrounds part of the semiconductor channel 210, that is, the semiconductor structure is a GAA structure. The GAA structure can realize the gate wrapping around the channel region of the semiconductor on all four sides, which can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size, reduce the area occupied by the word line 230 in the vertical direction, which helps to enhance the gate control performance and improve the integration of the semiconductor structure.

[0123] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having bit lines extending along a first direction; A semiconductor channel located on the bit line; A semiconductor doped layer is located on the side of the bit line, and the top surface of the semiconductor doped layer is in contact with the semiconductor channel; A word line extending in a second direction, the word line surrounding a portion of the semiconductor channel, and the bottom surface of the word line being higher than the top surface of the bit line; A word line dielectric layer, wherein the word line dielectric layer is located between the word line and the semiconductor channel; An isolation layer is located between the word line and the bit line, and between the word line and the semiconductor doped layer.

2. The semiconductor structure as described in claim 1, characterized in that, In the first direction, the bit line has at least two rows of spaced semiconductor channels, and the semiconductor doped layer is located on both sides of the bit line.

3. The semiconductor structure as described in claim 1, characterized in that, There are at least two bit lines, and the semiconductor doped layer is located on one side of the bit lines.

4. The semiconductor structure as described in claim 3, characterized in that, The semiconductor doped layers of the two adjacent bit lines are located on different sides.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the bit line includes metal; the semiconductor structure further includes a dielectric layer located on the top surface of the bit line, and the semiconductor doped layer is also located on the side of the dielectric layer, and the semiconductor channel is located on the surface of the dielectric layer.

6. The semiconductor structure as described in claim 1, characterized in that, The substrate is a semiconductor substrate; the semiconductor structure further includes: a barrier layer, the barrier layer being located within the substrate and protruding above the substrate, and the semiconductor channel being located on the top surface of a portion of the barrier layer.

7. The semiconductor structure as described in claim 6, characterized in that, The isolation layer is also located on the top surface of the barrier layer exposed by the semiconductor channel, and the isolation layer is located between the word line and the barrier layer.

8. The semiconductor structure as described in claim 6, characterized in that, The word line is located on the top surface of the barrier layer exposed by the semiconductor channel.

9. The semiconductor structure as described in claim 1, characterized in that, Parallel to the second direction, the width of the bit line is 2 to 3.5 times the maximum width of the semiconductor channel.

10. The semiconductor structure as described in claim 9, characterized in that, The maximum width of the semiconductor channel, parallel to the second direction, ranges from 10 nm to 20 nm.

11. The semiconductor structure as claimed in claim 1, characterized in that, The semiconductor doped layer has N-type or P-type ions; the semiconductor channel includes: The channel region is the area of ​​the semiconductor channel directly opposite the word line, and the channel region is doped with N-type ions or P-type ions. The doped region is the region of the semiconductor channel outside the channel region, and the type of dopant ions in the doped region is the same as the type of dopant ions in the semiconductor doped layer.

12. The semiconductor structure as claimed in claim 11, characterized in that, The type of doped ions in the channel region is different from the type of doped ions in the semiconductor doped layer.

13. The semiconductor structure as claimed in claim 1, characterized in that, The area of ​​the bit line projected onto the substrate is 0.5 to 0.8 times the area of ​​the semiconductor channel projected onto the substrate.

14. The semiconductor structure as claimed in claim 1, characterized in that, The material of the semiconductor channel is the same as the material of the semiconductor doped layer; the material of the semiconductor channel includes silicon, germanium, or silicon germanide.

15. The semiconductor structure as claimed in claim 1, characterized in that, The word lines include spaced word lines, and the semiconductor structure further includes: A first isolation layer is located between adjacent word lines; A second isolation layer is located on the word line and on the first isolation layer, and the second isolation layer is also located on the side of the semiconductor channel away from the word line.

16. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided having bit lines extending along a first direction; A semiconductor doped layer and a semiconductor channel are formed, wherein the semiconductor channel is located on the bit line, the semiconductor doped layer is located on the side of the bit line, and the top surface of the semiconductor doped layer is in contact with the semiconductor channel; A word line and a word line dielectric layer are formed extending along a second direction, the word line surrounding a portion of the semiconductor channel, and the bottom surface of the word line being higher than the top surface of the bit line, the word line dielectric layer being located between the word line and the semiconductor channel; An isolation layer is formed between the word line and the bit line, and between the word line and the semiconductor doped layer.

17. The method for manufacturing a semiconductor structure as described in claim 16, characterized in that, The process steps for forming the semiconductor doped layer and the semiconductor channel include: An initial semiconductor substrate and a first doped layer are provided in a stacked configuration. The first doped layer is doped with N-type ions or P-type ions and has bit lines. A semiconductor layer is formed on the top surface of the first doped layer and on the bit line; The semiconductor layer and the first doped layer are graphically represented, with the remaining semiconductor layer serving as the semiconductor channel and the remaining first doped layer serving as the semiconductor doped layer.

18. The method for manufacturing a semiconductor structure as described in claim 17, characterized in that, A second doped layer is formed using a selective epitaxial process, and the second doped layer has trenches; before patterning the semiconductor layer and the first doped layer, the method further includes: forming a sacrificial layer that fills the trenches; and after patterning the semiconductor layer and the first doped layer, removing the sacrificial layer.

19. The method for manufacturing a semiconductor structure as described in claim 16, characterized in that, After forming the word line, the method further includes: performing a doping process on the semiconductor channel above the top surface of the word line, wherein the type of dopant ions in the doping process is the same as the type of dopant ions in the semiconductor doped layer.

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