4F2 vertical access transistor with reduced buoyancy effect

Abstract

This technology includes a vertical-cell dynamic random-access memory (DRAM) array access transistor with improved hole distribution. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending orthogonally to the first and second horizontal directions, the plurality of bit lines intersecting the source / drain regions of the plurality of channels and the plurality of word lines intersecting the gate regions of the plurality of channels. Furthermore, the array includes a p-type doped bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, the first channel being spaced apart from the second channel of the second horizontally extending column.

Description

Technical Field

[0001] [Cross - reference to Related Applications] This application claims priority to U.S. Provisional Application No. 63 / 495,028, filed Apr. 7, 2023, by Chen et al., titled "4F 2 DRAM WITH REDUCED FLOATING BODY EFFECT", and claims priority to U.S. Provisional Application No. 63 / 601,064, filed Nov. 20, 2023, by Pesic et al., titled "4F 2 VERTICAL ACCESS TRANSISTOR WITH REDUCED FLOATING BODY EFFECT". The entire disclosures of these applications are hereby incorporated by reference herein for all purposes as if fully set forth herein.

[0002] This disclosure generally describes the design of 4F 2 vertical access transistor two - dimensional dynamic random - access memory arrays. More specifically, this disclosure describes 4F 2 memory arrays with reduced floating body effect.

Background Art

[0003] With the progress of computing technology, computing devices are becoming smaller and more powerful. Therefore, in order to meet the programming and computing needs of devices, it is necessary to increase storage and memory. The miniaturization of devices with increased storage capacity is achieved by increasing the number of storage units with a smaller form factor.

[0004] The dynamic random - access memory (DRAM) structure has been continuously shrinking over time. For example, the 1T - 1C (one transistor, one capacitor) DRAM cell structure has shrunk from an 8F 2 size to a 6F 2Successfully scaled down to a size (where F is the minimum feature size). 6F 2 to 4F 2 Further changes to the design scheme to 4F may help further improve the area density. 4F 2 In the DRAM scheme, the storage node (capacitor) and bit lines are arranged at the top and bottom of the vertical cell transistor, and the channel is completely insulated from the body. Due to this arrangement, the floating body effect that does not pose a problem in the current 8F 2 or 6F 2 DRAM cell structure becomes a major technical issue for 4F 2 DRAM. Therefore, improvements in this technical field are needed. SUMMARY OF THE INVENTION

[0005] Embodiments of the present technology generally relate to a vertical cell dynamic random access memory (DRAM) array with an improved hole distribution. The array includes a plurality of bit lines arranged in a first horizontal direction. The array includes a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels generally orthogonal to the first horizontal direction and the second horizontal direction, the plurality of bit lines intersect the source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels. The array includes a p-type doped bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, and the first channel is spaced from the second channel in a column extending in the second horizontal direction.

[0006] In embodiments, the p-type doped bridge has a doping level that is at least 1.6 times greater than the doping levels of the first and second channels. In more embodiments, the array further includes a shallow trench isolation defined between the first and second channels, the shallow trench isolation having a height extending from the first end to the second end. In further embodiments, the p-type doped bridge is located within the shallow trench isolation at a position approximately 20% to approximately 80% of the height of the shallow trench isolation. Additionally or alternatively, the array also includes at least a third channel of a plurality of channels spaced apart from the second channel in a second horizontally extending column, with a second p-type doped bridge extending between the second and third channels. In further embodiments, the array further includes a body contact electrically connected to the p-type doped bridge. Furthermore, in embodiments, the body contact is connected to a bias voltage source. In more embodiments, the array further includes bit line contacts electrically connected to one or more of a plurality of bit lines, the bit line contacts being electrically isolated from the body contacts. Furthermore, in embodiments, the device comprises a second p-type doped bridge extending between a first channel of a plurality of channels and a second channel of a plurality of channels.

[0007] Embodiments of this technology also generally relate to vertical-cell dynamic random-access memory (DRAM) arrays. The array includes a plurality of bit lines arranged in a first horizontal direction. The array includes a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of first channels spaced apart in a first column extending in a second horizontal direction. The array includes a plurality of second channels spaced apart in a second column extending in a second horizontal direction, the first column being spaced apart from the second column. The array comprises a plurality of p-type doped bridges extending between adjacent channels in the first column and between adjacent channels in the second column. The array includes the fact that each of the channels extends vertically, orthogonal to the first and second horizontal directions, the plurality of bit lines intersect the source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels.

[0008] In embodiments, the array further includes shallow trench isolations defined between adjacent channels in each row, the shallow trench isolations having a height extending from a first end to a second end. In more embodiments, the array also includes a second shallow trench isolation between adjacent channels in the first and second rows, and a gate formed along the outer surface of the second shallow trench isolation. In further embodiments, the array includes a conductive material covering each p-type doped bridge. Additionally or alternatively, in embodiments, the array includes at least one body contact in each row, each of which extends from the first end of the shallow trench isolation to the doped material within the respective shallow trench isolation.

[0009] The technology also includes a method for forming a vertical cell dynamic random access memory (DRAM) array. The method includes etching a substrate to form a plurality of shallow trench isolations and a plurality of vertically extending channels, each having a first source / drain region at a second end. The method includes forming a dielectric within one or more shallow trench isolations. The method includes recessing the dielectric to a certain height within one or more shallow trench isolations. The method also includes forming a protective liner within one or more shallow trench isolations and bottom punching the bottom surface of the protective liner. The method includes recessing the dielectric to a second height below a first height within one or more shallow trench isolations. The method involves forming a p-type doped bridge within one or more shallow trench isolations, wherein the p-type doped bridge is in contact with a first side wall and a second side wall of one or more shallow trench isolations that are exposed by recessing them to a second height.

[0010] Embodiments also include filling one or more shallow trench isolations on a p-type doped bridge with dielectric material. In more embodiments, the method includes forming a conductive material on top of the p-type doped bridge. Furthermore, in embodiments, the method includes forming the p-type doped bridge epitaxially and depositing the conductive material on top of the p-type doped bridge. In embodiments, the method includes etching a first opening from the exposed surface of a vertical cell dynamic random access memory (DRAM) array to the conductive material in one or more shallow trench isolations in at least a portion of the one or more shallow trench isolations. Embodiments include metallizing the top surface of the conductive material and forming a conductive metal shield within the opening and on the exposed surface of the vertical cell dynamic random access memory array. In an embodiment, the method includes forming an interlayer dielectric on a conductive metal shield, etching a second opening through the interlayer dielectric to a bit line formed on a second source / drain region formed at the first end of a vertically extending channel, and insulating the opening from the conductive metal shield.

[0011] Such technologies can offer numerous advantages over conventional systems and technologies. For example, the above process and system can reduce the hole accumulation effect by distributing holes across multiple channels. Furthermore, the above process and system is 4F 2 This has the potential to significantly reduce hole accumulation in the body of the DRAM device. The above embodiments and other embodiments, along with many of their advantages and features, are described in more detail below in connection with the description and accompanying figures. [Brief explanation of the drawing]

[0012] The nature and advantages of the disclosed technology can be better understood by referring to the rest of this specification and the drawings. [Figure 1A] This shows a top view of an exemplary processing chamber according to an embodiment of this technology. [Figure 1B] This shows a top view of a conventional 4F2 memory array. [Figure 1C] A perspective view of a conventional 4F2 memory array is shown. [Figure 2] The selected steps in the formation method according to the embodiment of this technology are shown. [Figure 3A] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, including filling of dielectric material after the formation of the first shallow trench isolation. [Figure 3B] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, in which the dielectric material is recessed. [Figure 3C] A perspective view of a semiconductor structure according to an embodiment of this technology, including a protective liner, is shown. [Figure 3D] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, with the protective liner bottom removed. [Figure 3E] A perspective view of a semiconductor structure according to an embodiment of this technology, in which the dielectric material has been etched back, is shown. [Figure 3F] This is a perspective view of a semiconductor structure according to an embodiment of this technology, where the exposed substrate has been cleaned. [Figure 3G] This shows a perspective view of a semiconductor structure according to an embodiment of this technology, in which a bridge is formed between adjacent channels. [Figure 3H] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, in which a filler is formed on a bridge. [Figure 4] The selected steps in the formation method according to an embodiment of this technology are shown. [Figure 5A] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, in which a conductive material is formed on a bridge. [Figure 5B] A perspective view of a semiconductor structure according to this technology, in which the conductive material has been etched back, is shown. [Figure 5C] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, in which a dielectric material is filled on top of a conductive material. [Figure 5D]A perspective view of a semiconductor structure according to an embodiment of this technology is shown, in which shallow trench isolation is formed in the direction of the word line. [Figure 5E] A perspective view of a semiconductor structure according to an embodiment of this technology, including a bridge contact aperture, is shown. [Figure 5F] A perspective view of a semiconductor structure according to an embodiment of this technology, including a bridge metallization contact, is shown. [Figure 5G] A perspective view of a semiconductor structure according to an embodiment of this technology, including body contacts, is shown. [Figure 5H] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, in which the bit line contact trench is insulated. [Figure 5I] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, in which the bit line contacts are insulated. [Figure 6A] A perspective view of the semiconductor structure according to this embodiment of the technology in which the first bridge is formed is shown. [Figure 6B] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, in which a doped layer is formed on the first bridge. [Figure 6C] This is a perspective view of a semiconductor structure according to an embodiment of the present technology, in which a second bridge is formed above a first bridge. [Modes for carrying out the invention]

[0013] Several diagrams are included as schematic representations. These diagrams are for illustrative purposes only and should not be considered to scale unless explicitly stated. Furthermore, as schematic representations, the diagrams are provided to aid understanding and may not include all aspects or information compared to a realistic depiction, and may include exaggerations for illustrative purposes.

[0014] In the accompanying drawings, similar components and / or features may be given the same reference label. Furthermore, various components of the same type can be distinguished by adding a letter after the reference number to distinguish similar components. Where only the first reference number is used herein, its description may apply to any similar component having the same first reference number, regardless of the aforementioned letter.

[0015] Historically, the bit density of DRAM chips has increased by approximately 25% between nodes. However, in more recent generations, the rate of increase in bit density between nodes tends to drop to around 20%, mainly due to challenges in scaling cell area. The cell design structure of the latest DRAM technology is 6F 2 It is based on geometry, where F is the minimum feature size of a given technology node. 6F 2 From 4th floor 2 Switching to a cell structure could potentially increase bit density by 33% on the same technology node. Furthermore, 6F 2 Compared to the 4th floor 2 The difficulty of patterning for DRAM is greatly reduced. This is because 4F 2 In the DRAM system, the capacitor and bit line are 6F 2 This is at least partly due to the fact that the transistors are located at both ends of a vertical cell, rather than being densely arranged on the same side like in DRAM.

[0016] However, 4F 2 Designing DRAM presents its own unique challenges. For example, 4F 2 In memory cells, transistor channels are located between the bit lines and the capacitor layer, and because there is no common substrate connecting these channels, a floating body effect occurs in these transistors. For example, in conventional 4F 2 In DRAM access devices, there is a problem with off-leakage current. Off-leakage current is caused by the isolation of the channels. 2This is due to the floating effect, such as hole accumulation within the body of the DRAM device. Electron-hole pairs can form within the semiconductor channel due to interband tunneling, potentially causing gate-induced drain leakage (GIDL). Electrons can flow into the n-type source or drain region of the transistor, but holes cannot. 4F where no substrate connection is provided. 2 In DRAM devices, holes have no way out of the channel and continue to accumulate. Therefore, the stray body effect may lead to channel activation without gate activation, which can ultimately lead to leakage current from the capacitor, i.e., the data storage side of the device, and a decrease in threshold voltage over time.

[0017] Attempts have been made to provide body connections using buried body contact methods. However, such attempts may result in gate overlap to the source / drain junction ends, potentially allowing undesirable gate-induced drain leakage (GIDL) or limiting scalability to smaller dimensions. Furthermore, such design methods can also create high aspect ratio structures that challenge existing doping techniques.

[0018] This technology overcomes the above and other problems by connecting two or more channels of transistors arranged vertically in each column of a cell with one or more p-type bridges located outside the source / drain regions of the transistors. Specifically, one or more p-type bridges between channels (extending, for example, along the gate or along the word line) provide a path for hole movement between channels when the gate is off, reducing the effects of gate-induced leakage current and / or stray body effects on the channels. Furthermore, sufficient doping levels prevent significant electron sharing between channels, so that when a channel along the word line is biased to ON, the on-current of the transistor is not affected and electrons continue to flow from source to drain. Thus, this technology is 4F 2 This reduces the flotation effect without interfering with the size or connectivity of the DRAM device. Furthermore, in embodiments, one or more bridges between adjacent channels in each row can also function as connection points for body contact. Thus, in embodiments, the technique results in adjacent channels being locally connected together to provide a shared flotation or biased to a desired body potential. That is, by utilizing one or more body contacts, it is possible to reduce or even eliminate the flotation effect without introducing unwanted gate overlap near the source / drain junction.

[0019] In the remaining disclosures, 4F 2While we will examine the specific deposition and etching processes used to form vertical-cell dynamic random-access memory (DRAM) arrays such as DRAM devices, it will be readily apparent that the systems and methods are equally applicable to other DRAM devices, other devices affected by the levitation effect, and their orientations, as well as the processes for forming such devices. Therefore, the technology should not be considered limited to use with these specific devices or systems alone. This disclosure describes one possible semiconductor device, which may include one or more components, utilizing one or more bridges according to embodiments of the technology, and then describes additional modifications and adjustments to the apparatus according to embodiments of the technology.

[0020] Figure 1A shows a top view of a multi-chamber processing system 100, which may be specifically configured to implement aspects or operations according to several embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on any number of individual substrates, such as semiconductor substrates, in order to form semiconductor devices. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112 (dual load locks may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 may include a heating element 113 and may be mounted on the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be mounted on the transfer chamber 106. The processing chambers 122 and 124 may be mounted on the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between robots 126 and 128. Platforms 102 and 104 may be open to the transfer chamber and the buffer chamber, or they may be selectively isolated or sealed from the chambers so that varying operating pressures are maintained between the transfer chamber 106 and the buffer chamber 108. Each of the transfer platforms 102 and 104 may include one or more tools 105 for positioning or measurement operations, etc.

[0021] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to perform the processes described below. Accordingly, the computer system 130 may be a controller or an array of controllers and / or a general-purpose computer comprising software stored in a non-transient computer-readable medium, the software being capable of performing the processes described in relation to the methods according to the embodiments of this technology when executed. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in the manufacture of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform several substrate processing steps, including, among any number of other substrate processes, dry etching, periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, and orientation.

[0022] Figures 1B and 1C show perspective and top views of a conventional 4F2 memory array 150. The memory array 150 may include a plurality of word lines 152 arranged in a first layer on the substrate. The word lines 152 may be conductive traces used to select the word lines of memory cells within the memory array 150. The memory array 150 may also include a plurality of bit lines 154 arranged in a second layer on the substrate. The bit lines may be conductive traces used to select the bit lines of memory cells within the memory array 150. By activating one of the bit lines 154 and one of the word lines 152, individual cells within the memory array 150 can be selected. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer containing the word lines 152 may be formed on top of the second layer containing the bit lines 154, such that these two layers do not intersect.

[0023] Multiple vertical memory cells may be arranged on the intersections between multiple word lines 152 and multiple bit lines 154. Each of the multiple vertical memory cells may include a vertical transistor, which may be referred to as a vertical pillar transistor or vertical column transistor. The channel material of the transistor may be formed from a single-crystal silicon pillar or any other substrate, as detailed below. This silicon channel may be formed by etching the substrate. Each of the multiple vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may operate by storing a charge in the vertical capacitor 156 that indicates the stored memory state. However, while Figures 1B and 1C show the arrangement of vertical transistors and vertical capacitors in a rectangular, generally orthogonal grid pattern (where "generally orthogonal" can be within approximately 10° of orthogonal, e.g., less than or equal to approximately 7.5°, e.g. less than or equal to approximately 5°, e.g. less than or equal to approximately 2.5°, e.g. less than or equal to approximately 1°, or any range or value in between, where the term "generally" can be similarly used to mean "vertical," "horizontal," etc.), it should be understood that other orientations are intended for use in this technology. For example, in embodiments, capacitors and vertical transistors may be spaced apart in alternating rows offset by half the distance between vertical transistors. That is, the first row of memory cells may be arranged in a row with regular spacing in a first direction, and the second row of memory cells may also be arranged in a row with regular spacing in the first direction. However, in this embodiment, the second row of memory cells may be offset from the first row of memory cells, for example, it may be aligned approximately midway between the vertical transistors and vertical capacitors of the first row. Such a pattern may be referred to as a "honeycomb" or "hexagonal pattern" in comparison to the rectangular pattern shown in Figures 1B and 1C. Therefore, it should be understood that any suitable orientation can be used in this technology.

[0024] It is useful to describe the dimensional characteristics of the unit cell area 166 of this conventional 4F2 memory array for comparison with the simplified memory array described below. For example, the capacitor footprint 158 ​​can be defined as the circular area surrounding each vertical capacitor 156. The capacitor footprint 158 ​​is the horizontal cross-sectional area of ​​the capacitor, which may include the cross-sectional area extended to contact with the capacitor area from the adjacent memory cell. Assume that the word line pitch 162 of multiple word lines 152 and the bit line pitch 164 of multiple bit lines 154 can be defined as 2F. Then the total cross-sectional area of ​​the unit cell area 166 is 4F2.

[0025] Figure 2 shows an exemplary step of Method 200 according to several embodiments of the present technology. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 200 may include several optional steps, which may or may not be particularly related to some embodiments of the method according to the present technology. For example, many steps are described to provide a broader range of structure formation, but may not be important to the technology or may be performed by alternative methods for ease of understanding. In addition, the method can describe a method of forming the structure from the word line side to the bit line side in the vertical direction, but it should be understood that other orientations from the bit line side to the word line side may be used.

[0026] Method 200 may include additional steps before commencing the enumerated steps. For example, additional processing steps may include forming a structure on a semiconductor substrate, which may include both forming and removing materials. The prior processing steps may be performed in the chamber in which Method 200 can be performed, or the processing may be performed in one or more other processing chambers before supplying the substrate into the semiconductor processing chamber in which Method 200 can be performed. In any case, Method 200 may optionally include supplying the semiconductor substrate to the processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or another chamber that may contain the components described above. The substrate may be placed on a substrate support / transfer platform, which may be a pedestal, such as a substrate support 104, and may be located within the processing area of ​​a processing chamber, such as the processing area of ​​the processing chamber 120 described above. Method 200 describes the steps schematically shown in Figures 3A to 3H, the illustrations of which will be explained in relation to the steps of Method 200. Figures 3A to 3H show only partial schematic diagrams, and it should be understood that the semiconductor substrate may include further and alternative components illustrated in the figures, in any size or configuration that still benefits from aspects of this technology.

[0027] Method 200 may or may not include optional steps for developing a semiconductor structure to a specific manufacturing process. It should be understood that Method 200 can be performed on any number of semiconductor structures 300 or substrates 302, including exemplary structures on which selectively deposited material can be formed, as shown in Figures 3A to 3H. As shown in Figure 3A, the substrate 302 can be any number of materials, such as silicon or silicon-containing material, germanium, other substrate materials, and a base wafer or substrate made from one or more materials that can be formed on the substrate during semiconductor processing.

[0028] In embodiments, the structure 300 may include a semiconductor substrate 302 comprising a bulk substrate, an epitaxial growth substrate, and / or an SOI (silicon on insulator) wafer. In this specification, the term “semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. The semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned substrates, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In one embodiment, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 includes a semiconductor material, for example, silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 302 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described, the idea and scope of this disclosure include any material that can function as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be built.

[0029] In embodiments, the semiconductor material is a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. In this specification, the term “n-type” refers to a semiconductor made by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. In this specification, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a higher hole concentration than electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0030] As shown in Figure 3A, a structure 300 including a substrate 302 is provided, on which the source / drain region 304 has already been formed, shallow trench isolation 308 has been formed, and the shallow trench isolation 308 has been filled with a first dielectric material 306. Furthermore, two or more walls 305 are formed between each shallow trench isolation 308, where, in this embodiment, the illustrated walls 305 are spaced apart in a row extending horizontally parallel to the word line direction. In this embodiment, the formation of the source / drain region 304 includes one or more ion implantations followed by an annealing activation process. The implantation process may be a single implantation or may include a series of multiple implantations. If multiple implantations are used, each implantation may utilize the same ion or a variety of ions. However, it should be understood that the source / drain region 304 can be formed from any suitable process. The method may include providing a semiconductor structure having a first source / drain region 304 for multiple vertical channels, and forming multiple word lines in contact with the first source / drain region. Overall, the process allows each stage of the transistor to be gradually formed on top of a previously completed stage.

[0031] Furthermore, various deposition and filling processes will be described, but in the embodiments, the semiconductor structure is to be transferred to and may be transferred between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or plasma-enhanced atomic layer deposition (PEALD). Therefore, unless otherwise specified, one or more of the above methods may be used as known in the art. Similarly, semiconductor structures may be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for inductively coupled plasma (ICP) etching, reactive ion etching (RIE), or capacitively coupled plasma (CCP) etching, and other etching processes known in the art.

[0032] However, in step 201, method 200 may include recessing the first dielectric material 306 to a first recessed height within one or more shallow trench isolations 308, as shown in Figure 3B. For example, in an embodiment, the substrate 302 may be loaded into load locks 110, 112 and transported via robots 126, 128 to a processing chamber (such as processing chamber 114), where the first dielectric material 306 is recessed. The substrate may be transported between each processing step, or it may be transported only in part of the processing steps, as some processing steps may be completed within the same processing chamber. In an embodiment, the dielectric material may be recessed to approximately the midpoint of each shallow trench isolation 308. However, it should be understood that the first dielectric material 306 is recessed to a height of approximately 20% to 80% of the height of each respective shallow trench isolation 308, for example, approximately 30% to 70%, approximately 40% to 60%, approximately 45% to 55%, or any range or value in between. That is, each shallow trench isolation 308 defined between adjacent channels has a first end 307 and a second end (shown more clearly in Figure 3H), and the trench height is defined between these ends. However, in embodiments including more than one p-type bridge, as will be detailed below, a larger recess height may be utilized. Furthermore, the recessing step 201 can be carried out by any method known in the art.

[0033] As shown in Figure 3C, after the recessing step 201, a protective liner 310 may be formed in step 202 on the recessed first dielectric material 306 and the exposed portions of the first sidewall 312 and second sidewall 314 (shown more clearly in Figure 3B) of each shallow trench isolation 308. The protective liner 310 can be formed from any dielectric material known in the art having a different etching rate from the first dielectric material 306, such as silicon nitride, silicon oxynitride, silicon dioxide, or other similar materials. Additionally or alternatively, in embodiments, the protective liner 310 can be formed from the same material as the first dielectric material 306, but with a thickness such that at least a portion of the protective liner 310 is retained after the second recessing step 204. However, as shown in Figure 3D, after the formation of the protective liner 310, in step 203, the bottom 316 of the protective liner 310 can be etched away to expose the first dielectric material 306. Such an etching process that selectively removes the bottom surface may be called "bottom punching" and may also be called anisotropic etching or directional etching. In embodiments, selective bottom etching or bottom punching can be performed by any etching process known in the art, such as reactive ion etching.

[0034] However, after bottom etching of the protective liner 310, the first dielectric material 306 may be subjected to a second recessing step in step 204, as shown in Figure 3E. The recessing step 204 can be selective for the first dielectric material 306, in which case the protective liner 310 is not removed from the first sidewall 312 and the second sidewall 314 of the shallow trench isolation 308. That is, at least a portion of the protective liner 310 remains on the first sidewall 312 and the second sidewall 314. In any case, the first dielectric material 306 is etched from a first height to a second height lower than the first height. By etching the first dielectric material 306 to a second height, exposed portions 322 of the first sidewall 312 and the opposing second sidewall 314 are formed between the first dielectric material 306 at the second height and the bottom surface 318 of the protective liner 310. In the embodiment, the second height is at a certain distance below the first height to provide a robust contact area for the bridge 320.

[0035] Accordingly, in embodiments, the height difference from the first height to the second height, and / or the length of the exposed portion of the first side wall 312 and the second side wall 314 may be about 2 nm or more, for example about 4 nm or more, for example about 6 nm or more, for example about 8 nm or more, for example about 10 nm or more, for example about 12 nm or more, for example about 14 nm or more, for example about 16 nm or more, for example about 18 nm or more, for example about 20 nm or more, for example about 50 nm or less, for example about 45 nm or less, for example about 40 nm or less, for example about 35 nm or less, for example about 30 nm or less, for example about 25 nm or less, or any range or value in between these. That is, in embodiments, the above distance and / or length may be selected so as to provide a sufficient contact area for a robust electrical connection without the bridge 320 becoming so long as to affect the overall doping level of each wall 305.

[0036] Regardless of the depth to which the dielectric material is etched, the exposed portions 322 of the first sidewall 312 and the opposing second sidewall 314 are optionally cleaned in step 205. The optional cleaning step 205 may include a pre-cleaning step and / or a surface damage removal step. That is, in order to effectively disperse holes between channels, each bridge 320 needs to have a strong electrical connection with each of the adjacent walls 305. However, surface oxidation, silicon damaged during the denting step 204, and other contaminants may interfere with the effective bonding of the bridge 320 to the first sidewall 312 and / or the second sidewall 314. Therefore, in embodiments, step 205 includes selectively removing surface damage (e.g., silicon damaged during the denting step, if any) from the exposed portions 322 of the first sidewall 312 and the second sidewall, such as by using an isotropic etching process, as shown in Figure 3F. Isotropic etching processes, such as vapor-phase etching, are available from Applied Materials, Inc. (Selectra®) and remove doped and undoped silicon while retaining the dielectric material. In embodiments, only one or more layers are removed, forming an exposed surface 322 or adjacent to the exposed surface 322. In embodiments, pre-cleaning, such as Siconi® cleaning, can remove any existing surface oxides. However, in embodiments, cleaning may not be necessary. That is, in embodiments, method 200 can be performed entirely within the processing system 100 without being removed from the vacuum, and the formation of oxides and other surface defects after oxide removal by the denting step 204 may be limited. Additionally or alternatively, there may be no damaged silicon after the denting step 204. Therefore, in embodiments, both pre-cleaning and surface damage removal steps may be used, only one of them may be used, or neither pre-cleaning nor surface damage removal steps may be used.

[0037] Method 200 further includes, as shown in Figure 3G, forming a p-type doped bridge 320 between two adjacent walls 305 extending along a single column in step 206 (for example, the bridge 320 is formed along or parallel to a gate, which will be described in more detail below). In embodiments, the p-type doped bridge 320 can be formed from the same material as two or more walls 305, or from different materials suitable for forming a p-type doped bridge between adjacent walls 305, such as any substrate material or other material. However, in embodiments, the p-type doped bridge 320 has a doping level higher than that of the wall 305 adjacent to each bridge 320. That is, by utilizing a higher doping level than that of the wall 305 adjacent to each bridge, it is possible that charge sharing between the walls 305 through the bridge 320 can be minimized or absent when the wall 305 is biased to turn on, because the voltage threshold is below the activation threshold of the bridge 320. However, the doping level must not significantly exceed the doping levels of two or more walls 305, because the dopant may diffuse into two or more walls 305, causing the channel threshold to exceed the bias voltage.

[0038] Accordingly, in the embodiment, each bridge 320 may have a doping level of about 1.6 times or more that of the wall 305 adjacent to each bridge 320, for example, about 1.8 times or more, for example about 2 times or more, for example about 2.2 times or more, for example about 2.4 times or more, for example about 2.6 times or more, for example about 2.8 times or more, for example about 3 times or more, for example about 5 times or less that of the doping level of the wall 305, for example about 4.8 times or less, for example about 4.6 times or less, for example about 4.4 times or less, for example about 4.2 times or less, for example about 4 times or less, for example about 3.8 times or less, for example about 3.6 times or less, for example about 3.4 times or less that, or a doping level of any range or value in between these.

[0039] In other words, in the embodiment, the doping concentration of one or more p-type doped bridges 320 is approximately 5 × 10⁻¹⁰ 16 cm -3 The above is sufficient, for example, approximately 6 × 10 16 cm -3 For example, approximately 7 x 10 16 cm -3 For example, approximately 8 x 10 16 cm -3 For example, approximately 9 x 10 16 cm -3 For example, approximately 1 × 10 17 cm -3 For example, approximately 2 × 10 17 cm -3 For example, approximately 4 x 10 17 cm -3 For example, approximately 6 x 10 17 cm -3 For example, approximately 8 x 10 17 cm -3 For example, approximately 1 × 10 18 cm- 3 For example, approximately 2 × 10 18 cm -3 For example, approximately 4 x 10 18 cm -3 For example, approximately 6 x 10 18 cm -3 For example, approximately 8 x 10 18 cm -3 For example, approximately 1 × 10 19 cm -3 For example, approximately 2 × 10 19 cm -3 For example, approximately 1 × 10 20 cm -3 For example, approximately 2 × 10 20 cm -3 For example, approximately 5 x 10 20 cm -3 For example, approximately 1 × 10 22 cm -3 Below, approximately 1×10 21 cm -3 The following may be, or any range or value between these.

[0040] That is, as described above, each bridge 320 may have a doping level sufficient to prevent significant charge sharing, for example, a doping level sufficient to provide a Vt above the gate threshold of the wall 305 adjacent to each bridge. However, since each bridge 320 has a higher level of dopant than the adjacent wall 305, each bridge 320 may diffuse the dopant from the center of each bridge 320 into the adjacent wall 305. Consequently, this diffusion may create a dopant gradient from the wall 305 toward the center of each bridge 320. This phenomenon may improve hole attraction and reduce the buoyancy effect. This is because holes may move from the problematic region of one or more walls 305 into each bridge 320, and the holes may be dispersed across the bridges 320, or they may move completely along the bridged column between the connected bridges 320 and the wall 305, causing the buoyancy effect to disappear. However, if the doping level in one or more bridges 320 is too high compared to the adjacent walls 305, dopant diffusion may cause the doping level of one or more walls 305 to rise above the threshold level of the walls 305. Therefore, in the embodiment, the doping level of each bridge compared to the adjacent walls 305 is carefully selected. Nevertheless, surprisingly, in this technology it has been found that the bridges 320 dramatically reduce the stray body effect, for example by suppressing the rise in channel potential and reducing off-leak current.

[0041] However, in embodiments, several different materials can be used for one or more bridges 320. For example, one or more bridges may include crystalline semiconductors such as silicon, germanium, silicon-germanium, and / or other similar materials. In embodiments, the bridges may be formed from crystalline silicon, such as single-crystal silicon in embodiments, or one or more of the semiconductor materials described above. These materials may also be used in the form of polycrystalline semiconductors. In embodiments, one or more bridges 320 can be formed by epitaxially growing epitaxial silicon on a recessed first dielectric material 306 within a shallow trench isolation 308 and bonding the epitaxial layers until good contact with both the first sidewall 312 and the second sidewall 314 is achieved. Thus, in embodiments, such a process may be referred to as a selective epi-deposition process. Alternatively, one or more bridges 320 may be formed by conformally filling the shallow trench isolation 308 with one or more polycrystalline semiconductor layers, or by depositing one or more polycrystalline semiconductor layers using other deposition methods known in the art. Regardless of the method used, it will be evident that the material used for one or more bridges 320 is deposited or grown in such a way as to provide good electrical contact with both exposed portions 322 of the first sidewall 312 and the second sidewall 314. However, in embodiments, one or more bridges 320 may not be fully coupled or in contact with the first dielectric material 306, insofar as strong electrical hole contact is formed between them and the first sidewall 312 and the second sidewall 314.

[0042] Furthermore, in the embodiment, a metal oxide may be used as one or more bridges 320. In such an embodiment, the metal oxide may be physically connected to an adjacent channel but not electrically connected. In this form, holes can still be attracted to the metal oxide without electrical connection to the adjacent channel.

[0043] In embodiments, one or more bridges 320 are formed only in a portion of the shallow trench isolation 308. For example, as shown in Figure 3G, one or more bridges 320 have a height slightly greater than the height of the exposed portion 322 and can therefore extend into the protective liner 310. However, in embodiments, one or more bridges 320 may have a height approximately the same as the height of the exposed portion 322. That is, the shallow trench isolation 308 can be completely filled with bridge 320 material above the first dielectric material 306, but in such embodiments, if the protective liner 310 is not formed completely or uniformly, an undesirable high electric field may be generated in the upper region of the shallow trench isolation 308, such as within the source / drain region.

[0044] Accordingly, in embodiments, the thickness of one or more bridges 320 (from the bridge bottom 324 to the bridge top 326) may be about 2 nm or more, for example about 4 nm or more, for example about 6 nm or more, for example about 8 nm or more, for example about 10 nm or more, for example about 12 nm or more, for example about 14 nm or more, for example about 16 nm or more, for example about 18 nm or more, for example about 20 nm or more, for example about 25 nm or more, for example about 30 nm or more, for example about 70 nm or less, for example about 60 nm or less, for example about 50 nm or less, for example about 40 nm or less, for example about 35 nm or less, or any range or value in between these. That is, in embodiments, the thickness can be selected to provide a sufficient contact area for a robust connection. However, in embodiments such as when two or more bridges are used, as will be described in more detail below, it may not be necessary to form a direct connection between one or more bridges and an adjacent wall. In such embodiments, the cleaning step 205 and / or the recessing step 204 can be omitted. In other words, while we do not wish to be bound by theory, doping can be finely tuned so that a suitable hole distribution is achieved without directly connecting the bridge to one or more channel walls.

[0045] Furthermore, as described above, in the embodiment, one or more bridges are formed at the approximate center of two or more walls 305 (and therefore shallow trench isolation 308). That is, by utilizing bridges located at the approximate center of two or more walls 305, holes can be dispersed between adjacent channels. However, in the embodiment, more than one bridge 320 can be utilized between each of the two walls 305, as will be described in more detail below with respect to Figures 6A to 6C, and it should be understood that none or one of such bridges 320 have to be located at the approximate center. For example, a first bridge 320 located near the source / drain region 304 of the semiconductor structure 300, and a second bridge 320 formed near the second source / drain region (clearly shown by Figures 5A to 5I). However, regardless of the number of bridges used between each of the two channels, at least one of the bridges 320 may be formed within the shallow trench isolation 308 at a height of approximately 20% to approximately 80% of the height of each of the shallow trench isolations 308, for example, approximately 30% to approximately 70%, for example, approximately 40% to approximately 60%, for example, approximately 45% to approximately 55%, or at any range or value in between.

[0046] Following the formation of the p-type bridge in step 206, in step 207, the remainder of the shallow trench isolation 308 above the bridge 320 may be filled. Figure 3H shows how the filling is carried out using a second dielectric material 332, which may be the same dielectric material as the first dielectric material 306, or a different dielectric material from the dielectric material initially filled into the shallow trench isolation 308 in Figure 3A. In embodiments, the first dielectric material and / or the second dielectric material 332 may be any one or more dielectric materials such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonite, a combination thereof, or other dielectric materials known in the art, and may be formed using any filling method known in the art as described above. In the following description, silicon oxide or silicon nitride is described as a dielectric material and / or spacer material as is customary; however, any number of dielectric materials may be used in embodiments of this technology, and it should be understood that this technology should not be limited to any specific dielectric material on which features can be formed. Nevertheless, it should be understood that other materials may be used in step 207, as will be described in more detail below.

[0047] In this embodiment, after the filling step 207, the semiconductor structure 300 is 4F 2 The semiconductor structure can then re-enter the normal processing flow of a vertical cell DRAM array, such as a DRAM array, and may be subjected to one or more further processing steps. For example, the semiconductor structure 300 may be planarized by utilizing polishing. Furthermore, the semiconductor structure may be subjected to one or more additional masking, etching, deposition, and / or filling steps to form a second set of columns orthogonal to the columns of channels described above, and to form bit lines and a second source / drain region, which will be described in more detail below. However, in embodiments where more than one p-type bridge is utilized, as will be described in more detail below, steps 204-207 may be repeated as necessary to form additional p-type bridges.

[0048] In vertical cell DRAM arrays such as 4F2 DRAM arrays, it may be beneficial to further reduce or even eliminate the floating effect. Therefore, in embodiments, step 207 may include filling the shallow trench isolations 308 above the bridges 320 with one or more conductive materials 440, as shown in Figure 5A (for example, step 207 shown in Figure 5A follows step 206 shown in Figure 3G). In embodiments, filling with a conductive material (which may be a doped material such as the same material as the bridges 320 or other conductive materials known in the art) may be carried out by epitaxially growing a conductive material, such as crystalline silicon in embodiments, on the bridges 320 within the shallow trench isolations 308. Alternatively, filling on one or more bridges 320 may be formed by conformally filling the shallow trench isolations 308 with one or more conductive materials, or by depositing one or more conductive material layers using other deposition methods known in the art. However, in the embodiments, step 207 should be understood as optional, because instead of utilizing an additional filling step, the bridge 320 itself can be extended to the top surface 330 of the semiconductor structure. Regardless of the formation method, it has been found that, surprisingly, the formation of the bridge 320 and the conductive material 440 can be carried out in the same chamber, such as one of the processing chambers 114, 116, 118, 120, 122, and 124 described above. Thus, in the embodiments, the epitaxial growth process and / or filling process of the bridge 320 can be carried out in the same processing chamber as the epitaxial growth process and / or filling process of the conductive material 440.

[0049] For example, Figure 4 shows an exemplary step of Method 400 according to several embodiments of the present technology. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 400 may include several optional steps, which may or may not be particularly related to certain embodiments of the method relating to the present technology. For example, many of the steps are described to provide a broader range of structure formation, but may not be critical to the technology or may be performed by alternative methods for ease of understanding. Method 400 describes the steps schematically shown in Figures 5A to 5I, but the examples are described in conjunction with the steps of Method 400. Figures 5A to 5I are only partial schematic diagrams, and it should be understood that the semiconductor substrate may include further components as illustrated in the figures, and alternative components, of any size or configuration from which the present technology can still be beneficial.

[0050] For example, as described above, in embodiments, step 207 may include filling the bridge 320 with a conductive material different from the bridge 320 material, or filling the shallow trench isolation 308 with the bridge 320 material. However, in embodiments, the term “different” should be understood to include polycrystalline versions of a single crystalline material and vice versa (e.g., a bridge 320 formed from crystalline silicon and a doped material layer formed from polycrystalline silicon). Nevertheless, step 406 includes etch-backing the conductive material 440 illustrated in Figure 5B and filling the conductive material 440 in Figure 5C with a shallow trench isolation 308 of a second dielectric material 332. Etching back the conductive material 440 may be done by the methods described above or by methods known in the art. However, in embodiments, the conductive material 440 is etched to a height below the uppermost surface 442 of the wall 305. That is, as described above, in the embodiment, there is a risk that the conductive material 440 (and / or the material of the bridge 320) may interact with the wall 305 through gaps or holes in the protective liner 310, where defects are more likely to occur at the uppermost surface 442 of the wall 305. Therefore, in the embodiment, in order to reduce the possibility of a short circuit between the wall 305 and the conductive material 440 / bridge 320 material, the conductive material 440 / bridge 320 material is etched back to a height below the uppermost surface 442 of the wall 305.

[0051] Accordingly, Figure 5C shows the filling process 406 being carried out using a second dielectric material 332, which may be the same dielectric material as the first dielectric material 306, or a different dielectric material from the dielectric material initially contained in the shallow trench isolation 308 in Figure 3A. In embodiments, the second dielectric material 332 may be any one or more dielectric materials such as silicon oxide, and may be formed using any filling method known in the art as described above. As shown, the semiconductor structure 500 may be planarized, such as by polishing, after the etch-back and refilling process 406.

[0052] Next, step 407 is 4F which utilizes any method and technique known in the art. 2 Includes a standard processing flow for DRAM arrays.

[0053] For example, Figure 5D shows the etching of a second horizontally extending shallow trench isolation 446, the formation of channels 448, and the deposition of a third dielectric material 450. That is, as described above for the formation of shallow trench isolations 308 between walls 305, a pattern or mask defining the second shallow trench isolation 446 can be used to form isolations between channels 448, which are formed by an etching process and, in this embodiment, extend in columns parallel to or coplanar with the word lines. The resulting channels 448 may have uniform or non-uniform widths and / or widths approximately equal to those of the walls 305. The second shallow trench isolation 446 may serve to isolate adjacent channels 448.

[0054] Furthermore, Figure 5D shows the formation of a third dielectric material 450 along adjacent walls 305 and bridges 320 in a first horizontally extending column, such that the third dielectric material 450 is substantially parallel to the word line direction. The third dielectric material 450 may be formed from a material such as SiO2 or other similar material. For example, SiO may be oxidized from walls 305 and / or 448 and used as the dielectric material 450, or it may be deposited as is known in the art. Notwithstanding this method, the third dielectric material extends along the substantially outer circumference of each shallow trench isolation 446. The thickness of the dielectric material may be about 1 nm to about 10 nm.

[0055] Figure 5E shows the 4F with the components formed on top. 2The diagram shows a semiconductor structure 500 having various vertical cell DRAM arrays, such as a DRAM array. For example, after the formation of a third dielectric material 450, a gate metal 452 is formed on the third dielectric material 450, generally along the outer circumference of the shallow trench isolation 446. In the embodiment, the gate metal may be a low-resistance metal such as tungsten, titanium nitride, titanium, ruthenium, cobalt, molybdenum, or a combination thereof. As shown in the diagram, in the embodiment, the gate metal 452 may be etched back below the second source / drain region 456 of the first wall 305 and / or channel 448.

[0056] A spacer 454 is formed within a second shallow trench isolation 446 between adjacent channels 448. The spacer layer 454 may be formed from any insulating material 443, such as SiO, SiN, a dielectric, or other similar material. In embodiments, the spacer layer 454 may be filled and then etched back using any method known in the art. For example, in embodiments, the spacer layer 454 may be filled and etched back to a level below the second source / drain region 456 of the first wall 305 and / or channel 448 to provide a recess for the gate metal 452, followed by a second filling of the same or a different insulating material. In some embodiments, a planarization process may be performed to produce a flat surface at the top of the stack for the formation of a subsequent layer.

[0057] For example, as shown in the figure, source / drain formation is performed on a portion of the wall 305 and / or 448, forming a second source / drain region 456 adjacent to the uppermost part 442 of each channel. As described above for the source / drain region 304, in this embodiment, the formation of the second source / drain 456 may include one or more ion implantations followed by an annealing process. The implantation process may be a single implantation or may include a series of multiple implantations. If multiple implantations are used, each implantation may utilize the same ions or different ions. However, it should be understood that the second source / drain region 456 can be formed from any suitable process.

[0058] Furthermore, the second source / drain region 456 may be subjected to a metallization process, such as silicideization, to form the cap 458. For example, a metal layer may be applied to the second source / drain region 456 and subjected to a silicideization process. In embodiments, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal-containing species of these, alloys of these, or combinations thereof. Thus, the resulting cap 458 may be a metallized layer of one or more of the above metals and a channel material such as silicon. Only in such examples may the cap 458 layer be titanium silicide, molybdenum silicide, or a combination thereof.

[0059] However, one or more layers of the barrier layer 460 and bit line 462 material may be formed on a completely exposed top surface (for example, the surface of the planar semiconductor structure 500 by the top surface 442, which in this processing step functions as the top surface or exposed surface). The barrier layer 460 and bit line layer 462 can then be etched during bit line formation, removing the barrier layer 460 material and bit line layer 463 material on the shallow trench isolation 308, while leaving enough material to cover and connect the respective caps 458, the third dielectric material 450, and the spacer layer 454 of the wall 305.

[0060] In some embodiments, the barrier layer 460 may be a nitride, oxynitride, carbonitride, and / or oxycarbonite of cobalt (Co), copper (Cu), nickel (Ni), ruthenium (Ru), manganese (Mn), silver (Ag), gold (Au), platinum (Pt), iron (Fe), molybdenum (Mo), rhodium (Rh), titanium (Ti), tantalum (Ta), silicon (Si), or tungsten (W), or a combination thereof. Furthermore, the bit wire 462 may be a material deposited by any suitable technique known in the art, such as one or more of the deposition or filling techniques described above. In some embodiments, the bit wire 462 includes one or more of tungsten (W), ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), or molybdenum (Mo). In this embodiment, the material of the bit wire 462 is one or more of ruthenium or tungsten.

[0061] As shown in the figure, spacers 464 may be included along each bit line layer 462. The spacers 464 may be the same material as the protective liner 310. However, in embodiments, the spacers 464 may be any of the insulating materials described with respect to spacers 454 and may be applied according to any of the methods described, regardless of the material of the protective liner 310. In embodiments, the spacers 464 may be applied as a conformal layer on the exposed surface of the semiconductor structure 500. In addition, a further dielectric material 466 may be filled between the spacers 464. The further dielectric material 466 may be one or more of the dielectric materials described above and may be filled according to any of the techniques described above.

[0062] However, the interlayer dielectric 468 is formed on a further dielectric material 466 and a spacer 464, and the further dielectric material 466 and the spacer may be planarized before formation. The interlayer dielectric 468 can be formed from one or more of the above-mentioned dielectric materials using any applicable technique. For example, the interlayer insulator 468 may be called silicon nitride.

[0063] Regardless of the material and formation method of the interlayer dielectric 468, one or more openings 470 are etched through the interlayer dielectric 468, dielectric material 466, spacer layer 464, and dielectric material 332 in step 408 to expose the conductive material 440 (and / or bridge 320 material (if the bridge 320 material is expanded during the bridge formation step 206 and / or refill step 207 as described above)). The openings 470 may be aligned with one or more bridges 320 and positioned vertically above the one or more bridges 320. Although one opening 470 is shown for each bridge 320 (for example, 12 bridges in this example), it should be understood that only one opening may be required for each bridge-connected word line row (for example, WR1, WR2, WR3, WR4, and WR5 in the illustrated embodiment, but more or fewer rows may exist) due to the hole-sharing properties of the bridges 320 and walls 305 in each row.

[0064] Accordingly, in the embodiment, each bridge connection row includes at least one opening. In addition or alternatively, in the embodiment, each bridge connection row may include fewer than or equal to the number of bridges 320, and insofar as each bridge connection row includes at least one opening 470, this could be, for example, a number of openings equal to about 90% or less of the bridges in each row, for example, about 80% or less, for example, about 70% or less, about 60% or less, about 50% or less, about 40% or less, about 30% or less, about 20% or less, about 10% or less, or any range of openings in between.

[0065] Furthermore, in embodiments where the number of apertures 470 is less than the number of bridges 320, the apertures may be aligned in a series of bit lines (e.g., BR1, BR2, BR3, BR4, or BR5), or spaced apart in one or more of the series BR1-BR5 and WR1-WR5. For example, the first aperture 470 may be located between WR5-BR1, the second between WR4-BR2, the third between WR3-BR3, the fourth between WR2-BR4, the fifth between WR1-BR5, and so on. However, as you can see, any pattern or position may be used, such as a zigzag pattern between only two WR series or BR series, or any other combination.

[0066] However, in the embodiment, in order to minimize the occurrence of short circuits, it may be desirable to leave a gap between adjacent openings 470 in two or more BR rows or WR rows, as described in the example above. However, in the embodiment, in order to further control hole dissipation, it may be desirable to include one opening per bridge 320.

[0067] In embodiments, the opening 470 may self-align between adjacent second source / drain regions 456 of each bridged column. As shown in the figure, the second source / drain regions 456 may be used to align the opening 470 with the bridge 320. However, it should be understood that in embodiments, other methods for forming the opening 470 may be used as known in the art. For example, the opening 470 may be formed by utilizing one or more methods for forming storage node contacts. That is, in embodiments, for example, an opening larger than required for the contact may be formed, and an additional liner may be formed outside this opening.

[0068] Although the opening is shown having a circular cross-section, it should be understood that other cross-sectional shapes are also possible. In embodiments, the cross-sectional shape of the opening 470 may be selected based on the shape of the shallow trench isolation 308. However, in embodiments, the size and shape of the opening may be selected to remove all or most of the second dielectric material 332 from each shallow trench isolation 308 over the bridge 320, while leaving the protective liner 310 intact, or to remove only a portion of the second dielectric material 332. Regardless of the shape and size of the opening in the horizontal direction, the opening should have sufficient height to expose the conductive material 440.

[0069] However, after etching the opening 470, the exposed conductive material 440 and / or bridge 320 material are subjected to a metallization process in step 409. In embodiments, the metallization step 409 may be a silicide process, forming the body contact cap 472 as shown in Figure 5F. For example, a metal layer may be applied to the conductive material 440 and / or bridge 320 and subjected to a silicide process. In embodiments, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal-containing species of these, alloys of these, or combinations thereof. Thus, the resulting body contact cap 472 may be a metallized layer of one or more of the above metals and a channel material such as silicon. Only in such examples may the cap 478 layer be titanium silicide, molybdenum silicide, or a combination thereof.

[0070] After the formation of the body contact cap 472, in step 410, a conductive metal shield 474 is formed in the opening 470 and on the interlayer dielectric 468, as shown in Figure 5G. In embodiments, the conductive metal shield 474 may be one or more of the following, or a combination thereof: cobalt (Co), copper (Cu), nickel (Ni), ruthenium (Ru), manganese (Mn), silver (Ag), gold (Au), platinum (Pt), iron (Fe), molybdenum (Mo), rhodium (Rh), titanium (Ti), tantalum (Ta), silicon (Si), tungsten (W). In one or more embodiments, the conductive metal shield 474 is one or more of titanium (Ti), copper (Cu), cobalt (Co), tungsten (W), or ruthenium (Ru).

[0071] That is, by including a conductive metal shield 474 in the opening 470 that contacts the body contact cap 472, and the conductive metal shield 474 on the surface of the interlayer dielectric 468, one or more bridges 320 can now be positioned in electrical contact with the body of the semiconductor structure 500. Thus, because the conductive metal shield 474 functions as a body contact, one or more walls 305 / 448 are no longer floating, and the float effect is reduced and / or completely eliminated. For example, in an embodiment, a bias potential such as zero voltage or a slightly negative voltage can be applied to the conductive metal shield 474, and in an embodiment, any existing holes can be attracted to the uppermost plate 476 of the conductive metal shield 474 and moved out of two or more walls 305, if not completely, at least partially.

[0072] However, because a conductive material (e.g., a conductive metal shield layer 474) is present, the bit line contacts need to be insulated from the conductive metal shield layer 474. Therefore, the step 411 for forming the bit line contacts includes isolating the bit line contacts from the metal shield layer 474 as shown in Figure 5H. That is, as illustrated, step 411 may include applying a second interlayer dielectric 478 on top of the conductive metal shield layer 474. The second interlayer dielectric 478 may include one or more of the dielectric materials described above. As shown in Figure 5H, the second interlayer insulator 478 may be recessed to access at least one bit line 462. After the recess is formed, the conductive metal shield layer 474 may be recessed horizontally and filled with plug dielectric material 482 so that the recess 481 is electrically isolated from the conductive metal shield 474. The plug dielectric material 482 can be formed from one or more of the dielectric materials and / or liner materials described above using any applicable technique. However, in some embodiments, the plug dielectric material 482 may be conformally filled into the recess. Nevertheless, as shown, the bottom of the plug 482 is removed (e.g., "punched out"), exposing the top 480 of one or more bit wires 462, while the rest of the recess is insulated from the conductive metal shield layer 474.

[0073] Referring to Figure 5I, after the formation of the plug 482 and the etching removal of the bottom of the plug 482, the bit wire contact 484 may be formed by filling the recess 481 with one or more conductive materials. In embodiments, the bit wire contact 484 may be formed from the same material as the bit wire 462 or a different material. Thus, in embodiments, the conductive material may be deposited by any suitable technique known in the art, such as one or more deposition or filling techniques described above. In some embodiments, the bit wire contact 484 includes one or more of tungsten (W), ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), or molybdenum (Mo). In embodiments, the material of the bit wire 462 is one or more of ruthenium or tungsten.

[0074] After the formation of the bit line contact 484, the semiconductor structure 500 is 4F 2 The semiconductor structure can then re-enter the normal processing flow of a vertical cell DRAM array, such as a DRAM array, and be subjected to one or more further processing steps. For example, the semiconductor structure 500 may undergo contact reallocation, bonding pad formation, and / or copper contact formation. However, the semiconductor structure can dramatically reduce or even eliminate the stray body effect by sharing holes between channels in each row (e.g., rows WR1 to WR5 parallel to or coplanar with the word lines) and / or connecting each row to the substrate body.

[0075] Regardless of whether body contacts are used, the technology can also provide the formation of more than one p-type bridge. For example, Figure 6A may show an embodiment similar to Figure 3G (for example, after step 206). However, Figure 6A shows a case where the first recessing step 201 and / or the second recessing step 204 include etching the first dielectric material 306 to a height of about 50% or less of the trench height, for example, to a height of about 45% or less, for example, about 40% or less, for example, about 35% or less, for example, about 30% or less, for example, about 25% or less, for example, about 20% or less, for example, about 15% or less, for example, about 20% or less, or to any range or value in between. However, in embodiments, the above height may be greater than 0% of the trench height, for example, about 5% or more, for example, about 10% or more, or any range or value in between, so as to prevent overlap and short circuits with the source / drain region described above.

[0076] In other words, surprisingly, this technology has shown that by using more than one p-type bridge 320, it is possible to prevent holes, such as those formed from interband tunneling, from accumulating at the center of the channel, thereby reducing channel polarity and on-current. To put it another way, by using more than one p-type bridge, such as one or more bridges adjacent to each source / drain region, a further reduction of GIDL (gate-induced drain leakage) at least partially at locations adjacent to the source / drain contacts can be demonstrated. Therefore, in embodiments where a further reduction of word line voltage is desired, more than one p-type bridge may be used in addition to any of the other factors mentioned above. However, in embodiments, it will be clear that one or more of the methods and apparatus described herein are suitable for reducing gate-induced leakage current and stray body effects.

[0077] However, as shown in Figure 6B, in the embodiment, step 207 may optionally include filling the p-type bridge 320 with a conductive material 340. The conductive material may be any of the materials described above with respect to the conductive material 440, and may be incorporated using one or more of the methods described in step 406. Regardless of the conductive material 340 and / or method used, the remaining portion of the shallow trench isolation may be filled with a dielectric material which may be the same as or different from the first dielectric material 306.

[0078] As shown in Figure 6C, the dielectric material 306 may then be etched back to a second height lower than the first height, as described in relation to step 204, similar to Figure 3G. The exposed sidewall 322 may optionally be cleaned as described above in relation to step 205 and shown in Figure 3F. Similar to Figure 3G, Figure 6C shows the formation of a second p-type bridge 321. The second p-type bridge 321 may be formed from the same material as the p-type bridge 320 or a different material, according to one or more of the material and doping levels described above. Furthermore, although two p-type bridges are shown in Figure 6A, it will be apparent that three or more p-type bridges can be formed by repeating steps 204-207.

[0079] Nevertheless, in embodiments, a p-type bridge, such as a second p-type bridge 321, may be formed adjacent to the first end 307 so as to be adjacent to a second source / drain region. Thus, in embodiments, at least the second p-type bridge is formed in the shallow trench isolation 308 at a height of about 60% or more of the trench height, for example, at a height of about 65% or more, for example, about 70% or more, for example, about 75% or more, for example, about 80% or more, for example, about 85% or more, for example, about 90% or more, or at a height that is any range or value in between. However, in embodiments, the above height may be less than 100% of the trench height, for example, at about 95% or less, for example, at about 90% or less, or at any range or value in between, so as to prevent overlap and short circuits with the source / drain region described above.

[0080] Regardless of the selected height, a conductive material which may be the same as or different from the conductive material 340 and / or 440 may be formed on the second p-type bridge 321. Furthermore, similar to step 207, the remainder of the shallow trench isolation 308 may be filled with a dielectric material which may be the same as or different from the first dielectric material 306. After filling, the semiconductor structure 300 may be subjected to body contact formation as described above, or 4F 2 The semiconductor structure can then re-enter the normal processing flow of a vertical cell DRAM array, such as a DRAM array, and be subjected to one or more further processing steps. For example, the semiconductor structure 300 may undergo contact reallocation, bonding pad formation, and / or copper contact formation. However, the semiconductor structure may demonstrate a dramatic reduction or elimination of the stray effect due to hole sharing between channels in each column.

[0081] The specific step shown in the figure corresponds to 4F in various embodiments. 2This should be understood as providing a specific method for forming a DRAM memory array. Steps in other sequences may also be performed according to alternative embodiments. For example, in alternative embodiments, the steps described above may be performed in a different order. Furthermore, each step shown in the figure may include multiple substeps, which may be performed in various sequences depending on the individual step. In addition, additional steps may be added or omitted according to a particular application. Numerous variations, modifications, and alternatives are also included in the scope of this disclosure.

[0082] In this specification, the terms “about,” “approximately,” or “substantially” may be interpreted as being within the range expected by a person skilled in the art in light of this specification.

[0083] In the preceding explanation, for the sake of clarity, numerous specific details were included to provide a complete understanding of various embodiments. However, it will be apparent that some embodiments can be implemented without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0084] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the prior description of various embodiments provides a feasible disclosure for realizing at least one embodiment. It should be understood that various modifications can be made to the function and arrangement of the components without departing from the idea and scope of some of the embodiments described in the appended claims.

[0085] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be found that embodiments can be implemented without the above-mentioned specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0086] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe steps as sequential processes, many of these steps can be executed in parallel or simultaneously. Moreover, the order of steps can be changed. A process terminates when its steps are completed, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination corresponds to the function's return value to the calling function or the main function.

[0087] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment, or machine-executable instruction, may represent any combination of a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or instruction, data structure, or program statement. A code segment may be connected to other code segments or hardware circuits by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0088] Furthermore, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. When implemented by software, firmware, middleware, or microcode, the program code or code segments for performing the required tasks may be stored in a machine-readable medium. The processor can then perform the required tasks.

[0089] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments can be used individually or in combination. Furthermore, embodiments can be used in any number of environments and applications beyond those described herein without departing from the broader idea and scope of this specification. Accordingly, this specification and the drawings are intended to be illustrative, not limiting.

[0090] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described herein may be performed by hardware components or embodied by a sequence of machine-executable instructions, such instructions may be used to cause a machine, such as a general-purpose or special-purpose processor or a logic circuit programmed with the instructions, to perform the method. The machine-executable instructions may be stored in one or more machine-readable media, such as a CD-ROM or other type of optical disc, floppy disk, ROM, RAM, EPROM, EEPROM, magnetic card or optical card, flash memory, or other type of machine-readable media suitable for storing electronic instructions. Alternatively, the method may be performed by a combination of hardware and software.

Claims

1. A vertical cell dynamic random access memory (DRAM) array, A first set of horizontally arranged bit lines, A second set of horizontally arranged word lines, A plurality of channels extending in a first horizontal direction and a vertical direction substantially orthogonal to the second horizontal direction, wherein the plurality of bit lines intersect the source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels, A p-type doped bridge extending between a first channel and a second channel among the plurality of channels, wherein the first channel is spaced apart from the second channel of the second horizontally extending column, A vertical-cell dynamic random-access memory (DRAM) array equipped with [a specific feature].

2. The vertical cellular dynamic random access memory (DRAM) array according to claim 1, wherein the doping level of the p-type doped bridge is at least 1.6 times greater than the doping levels of the first channel and the second channel.

3. The vertical cell dynamic random access memory (DRAM) array according to claim 1, further comprising a shallow trench isolation defined between the first channel and the second channel, wherein the shallow trench isolation has a height extending from a first end to a second end.

4. The vertical cellular dynamic random access memory (DRAM) array according to claim 3, wherein the p-type doped bridge is located within the shallow trench isolation at a position approximately 20% to approximately 80% of the height of the shallow trench isolation.

5. The vertical cellular dynamic random access memory (DRAM) array according to claim 1, wherein the p-type doped bridge is formed from crystalline silicon.

6. A vertical cell dynamic random access memory (DRAM) array according to claim 1, further comprising at least a third channel of the plurality of channels, spaced apart from the second channel in the second horizontally extending column, wherein a second p-type doped bridge extends between the second channel and the third channel.

7. The vertical cell dynamic random access memory (DRAM) array according to claim 3, further comprising a body contact electrically connected to the p-type doped bridge.

8. The vertical cell dynamic random access memory (DRAM) array according to claim 7, further comprising a bit line contact, the body contact being connected to a bias voltage source and / or electrically connected to one or more of the plurality of bit lines, wherein the bit line contact is electrically isolated from the body contact.

9. The vertical cellular dynamic random access memory (DRAM) array according to claim 1, further comprising a second p-type doped bridge extending between the first channel of the plurality of channels and the second channel of the plurality of channels.

10. A vertical cell dynamic random access memory (DRAM) array, A first set of horizontally arranged bit lines, A second set of horizontally arranged word lines, The first row extending horizontally in the second row, comprising a plurality of first channels spaced apart, A second row extending horizontally and spaced apart from the first row, comprising a second set of spaced channels, A plurality of p-type doped bridges extending between adjacent channels in the first column and between adjacent channels in the second column, Equipped with, Each of the channels extends in a vertical direction substantially perpendicular to the first horizontal direction and the second horizontal direction, the plurality of bit lines intersect the source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels. Vertical cell dynamic random access memory (DRAM) array.

11. The vertical cell dynamic random access memory (DRAM) array according to claim 10, further comprising shallow trench isolation defined between adjacent channels in each row, wherein the shallow trench isolation has a height extending from a first end to a second end.

12. A vertical cell dynamic random access memory (DRAM) array according to claim 10, further comprising: a second shallow trench isolation between adjacent channels of the first and second columns; and a gate formed along the outer surface of the second shallow trench isolation.

13. The vertical cell dynamic random access memory (DRAM) array according to claim 11, further comprising a conductive material covering each p-type doped bridge.

14. The vertical cell dynamic random access memory (DRAM) array according to claim 13, further comprising at least a second plurality of p-type doped bridges extending between adjacent channels in the first column and between adjacent channels in the second column.

15. A method for forming a vertical cell dynamic random access memory (DRAM) array, Etching the substrate to form one or more shallow trench isolations and a plurality of vertically extending channels, each having a first source / drain region at its second end, Forming a dielectric material within one or more shallow trench isolations, The dielectric material is recessed to a first height within one or more shallow trench isolations, Forming a protective liner within one or more shallow trench isolations, The protective liner is given a bottom opening (bottom punching), The dielectric material is recessed in one or more shallow trench isolations to a second height below the first height, The method involves forming a p-type doped bridge within one or more shallow trench isolations, wherein the p-type doped bridge is in contact with the first and second side walls of the one or more shallow trench isolations, which are exposed by recessing them to the second height. A method for forming a vertical cell dynamic random access memory (DRAM) array, including the following:

16. The method according to claim 15, further comprising filling the one or more shallow trench isolations on the p-type doped bridge with dielectric material.

17. The method according to claim 15, further comprising forming a conductive material on the p-type doped bridge.

18. The method according to claim 17, comprising forming the p-type doped bridge epitaxially and depositing the conductive material on the p-type doped bridge.

19. The method according to claim 17, comprising etching a first opening from the exposed surface of the vertical cellular dynamic random access memory (DRAM) array to the conductive material in one or more shallow trench isolations in at least a portion of the one or more shallow trench isolations; metallizing the uppermost surface of the conductive material; and forming a conductive metal shield in the opening and on the exposed surface of the vertical cellular dynamic random access memory (DRAM) array.

20. The method according to claim 19, further comprising forming an interlayer dielectric on the conductive metal shield, etching a second opening through the interlayer dielectric to a bit line formed on a second source / drain region formed at the first end of the vertically extending channel, and insulating the opening from the conductive metal shield.

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