Ternary memory cell-based single bit line TCAM cell and TCAM array
The single-bit line TCAM cell with a ternary memory cell design addresses the inefficiencies of conventional TCAM by reducing transistor count to 8 or 9, achieving ultra-low power consumption and high area efficiency for advanced memory address searches.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- UNIST (ULSAN NAT INST OF SCI & TECH)
- Filing Date
- 2024-12-20
- Publication Date
- 2026-06-25
AI Technical Summary
Conventional TCAM technologies require 16 transistors per memory cell, leading to increased area and power consumption due to leakage current, especially in high-density CMOS integration.
A single-bit line TCAM cell based on a ternary memory cell design using a T-CMOS device, comprising specific transistor configurations and cross-connected inverters, reduces the number of transistors to 8 or 9, utilizing ultra-low power consumption.
The design achieves significant power reduction and improved area efficiency, supporting high-performance memory address lookup for complex data in next-generation routers and switches, with a 44% reduction in transistor count.
Smart Images
Figure KR2024020785_25062026_PF_FP_ABST
Abstract
Description
Single-bit line TCAM cell and TCAM array based on ternary memory cell
[0001] The present invention relates to a memory device including a ternary memory cell. Specifically, it relates to a TCAM cell and a TCAM array having a single bit line based on a ternary memory cell.
[0002] Generally, memory cells typically stored and read only two values: the first value, 0, and the second value, 1.
[0003] Meanwhile, Korean registered patent No. 10-1689159 disclosed a T-CMOS capable of ternary logic circuits. This T-CMOS includes a pull-up element and a pull-down element connected in series between power supply voltages (VDD and GND). When both are turned off by an input voltage (VIN), the pull-up element and the pull-down element operate as simple resistors that are affected only by the output voltage (VOUT), and form a third binary number ("1" state) through voltage division. When only one of the pull-up element or the pull-down element is turned on to allow current to flow, VDD ("2" state) or GND ("0" state) is output as the output voltage (VOUT). A ternary logic circuit is disclosed having a current (ICON) component that is not affected by the input voltage (VIN) but is affected only by the output voltage (VOUT), and a current (IEXT) component that is affected by the input voltage (VIN) but not by the output voltage (VOUT).
[0004] Korean registered patent No. 10-2206020, based on a T-CMOS capable of such ternary logic circuits, provides a logic-in-memory structure that can store ternary logic values and provide ternary logic operations thereon by implementing an SRAM cell using a ternary memory cell.
[0005] Meanwhile, CAM is a circuit that performs the function of searching for the memory address where the data to be searched is located within a specific memory space at high speed. The basic form, Binary CAM (BCAM), utilizes a single memory cell as a component and performs memory address search by determining whether the search data matches binary information consisting of 0s and 1s. As an advanced technique, TCAM was designed to enable faster processing of searches across a wider range by storing three pieces of information—X (don't care)—in addition to 0s and 1s. However, since it was designed using two memory cells to store ternary information, it required 16 transistors, resulting in a problem where the area and power consumption increased by more than double. Moreover, the biggest problem with these existing methods using 16 transistors is that serious standby power consumption occurs, fundamentally stemming from increased leakage current due to the improvement in CMOS integration density.
[0006] The objective of the present invention to achieve the above objectives is to provide a TCAM that can drastically reduce the number of transistors in a memory cell based on an ultra-low power T-CMOS device.
[0007] In addition, the present invention aims to provide a TCAM structure that can significantly reduce power consumption along with superior area efficiency compared to conventional CAM technology.
[0008] A single-bit line TCAM cell based on a ternary memory cell according to one embodiment of the present invention comprises: a first inverter and a second inverter that are cross-connected at a first node and a second node; a first access transistor (M1) connected between a fourth node and ground, with a third node connected to the gate; a second access transistor (M2) connected between the first node and a fifth node, with a word line (WL) connected to the gate; a third access transistor (M3) connected between the fifth node and a third node, with the first node connected to the gate; a fourth access transistor (M4) connected between the fifth node and the third node, with the second node connected to the gate; a fifth access transistor (M5) connected between the third node and the first node, with the fifth node connected to the gate; and a sixth access transistor (M6) connected between the third node and the second node, with the fifth node connected to the gate.
[0009] In one embodiment, the first access transistor (M1), the second access transistor (M2), the fourth access transistor (M4), and the sixth access transistor (M6) are NMOS, and the third access transistor (M3) and the fifth access transistor (M5) are PMOS.
[0010] In one embodiment, the first node is a Q node, the second node is a QB node, the fourth node is a node to which a match line (ML) is connected, and the fifth node is a node to which a bit line (BL) and a search line (SL) are connected.
[0011]
[0012] According to another embodiment of the present invention, a ternary memory cell-based single-bit line TCAM array comprises: a plurality of ternary memory cell-based single-bit line TCAM cells arranged in a matrix of size nxm; m match lines, each connected to n TCAM cells in the same row; m word lines, each connected to n TCAM cells in the same row; n bit lines and search lines, each connected to m TCAM cells in the same column; and at least a word line and search string driving driver for driving the word lines and match lines. The ternary memory cell-based single-bit line TCAM cell comprises: a first inverter and a second inverter cross-connected at a first node and a second node; a first access transistor (M1) connected between a fourth node and ground, with a third node connected to its gate; and a second access transistor (M2) connected between the first node and a fifth node, with a word line (WL) connected to its gate. It includes a third access transistor (M3) connected between the fifth node and the third node and connected to the gate of the first node; a fourth access transistor (M4) connected between the fifth node and the third node and connected to the gate of the second node; a fifth access transistor (M5) connected between the third node and the first node and connected to the gate of the fifth node; and a sixth access transistor (M6) connected between the third node and the second node and connected to the gate of the fifth node.
[0013] According to another embodiment of the present invention, a single bit line TCAM cell based on a ternary memory cell comprises: a first inverter and a second inverter that are cross-connected at a first node and a second node; a first access transistor (M1) that is connected between a fourth node and ground and has a third node connected to its gate; a second access transistor (M2) that is connected between the first node and a fifth node and has a word line (WL) connected to its gate; a third access transistor (M3) that is connected between the first node and the third node and has the fifth node connected to its gate; a fourth access transistor (M4) that is connected between the fifth node and the third node and has the second node connected to its gate; and a fifth access transistor (M5) that is connected between the second node and the third node and has the fifth node connected to its gate.
[0014] In one embodiment, the first access transistor (M1), the second access transistor (M2), the fourth access transistor (M4), and the fifth access transistor (M5) are NMOS, and the third access transistor (M3) is PMOS.
[0015] In one embodiment, the first node is a Q node, the second node is a QB node, the fourth node is a node to which a match line (ML) is connected, and the fifth node is a node to which a bit line (BL) and a search line (SL) are connected.
[0016] According to another embodiment of the present invention, a ternary memory cell-based single-bit line TCAM array comprises: a plurality of ternary memory cell-based single-bit line TCAM cells arranged in a matrix of size nxm; m match lines, each connected to n TCAM cells in the same row; m word lines, each connected to n TCAM cells in the same row; n bit lines and search lines, each connected to m TCAM cells in the same column; and at least a word line and search string driving driver for driving the word lines and match lines; wherein the ternary memory cell-based single-bit line TCAM cell comprises: a first inverter and a second inverter cross-connected at a first node and a second node; a first access transistor (M1) connected between a fourth node and ground, with a third node connected to its gate; and a second access transistor (M2) connected between the first node and a fifth node, with a word line (WL) connected to its gate. It includes a third access transistor (M3) connected between the first node and the third node and connected to the gate of the fifth node; a fourth access transistor (M4) connected between the fifth node and the third node and connected to the gate of the second node; and a fifth access transistor (M5) connected between the second node and the third node and connected to the gate of the fifth node.
[0017] As such, according to the present invention, the following effects are achieved.
[0018] The single-bit line TCAM based on a ternary memory cell according to the present invention can drastically reduce power consumption along with excellent area efficiency compared to conventional CAM technology by designing a TCAM circuit based on an ultra-low power T-CMOS device and storing information using a very low current at the off-state level.
[0019] In addition, the TCAM based on the ternary memory cell according to the present invention can meet the demand for memory address lookup hardware capable of ultra-low power and high performance operation for more complex and large amounts of information in next-generation routers and switch devices, which is increasing with the recent advancements in meta-learning and few-shot learning.
[0020] In addition, the TCAM based on the ternary memory cell according to the present invention can significantly improve integration density by reducing the number of transistors by 50% or 44% to 8 or 9 transistors, compared to the existing TCAM structure that requires 16 transistors.
[0021] FIG. 1 schematically shows the configuration of a single-bit line TCAM cell based on a ternary memory cell according to one embodiment of the present invention.
[0022] Figure 2 shows the operation truth table of the TCAM cell illustrated in Figure 1.
[0023] FIG. 3 schematically illustrates the configuration of a single-bit line TCAM cell based on a ternary memory cell according to another embodiment of the present invention.
[0024] Figure 4 shows the operation truth table of the TCAM cell illustrated in Figure 3.
[0025] FIG. 5 shows a TCAM array using a single-bit line TCAM cell based on a ternary memory cell according to the present invention.
[0026] The following detailed description of the invention refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that various embodiments of the invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein with respect to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the invention. It should also be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the following detailed description is not intended to be limiting, and the scope of the invention is limited only by the appended claims, including all equivalents to those claimed therein, provided appropriately described. Similar reference numerals in the drawings refer to the same or similar functions across various aspects.
[0027] Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component.
[0028] When it is stated that a component is "connected" to another component, it should be understood that it may be directly connected to or joined to that other component, or that there may be other components in between.
[0029] The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, terms such as "comprising" or "having" are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.
[0030] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.
[0031] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are given the same reference numeral regardless of the drawing number, and redundant descriptions thereof will be omitted.
[0032] FIG. 1 schematically shows the configuration of a ternary CMOS-based TCAM cell according to one embodiment of the present invention.
[0033] Referring to FIG. 1, a single-bit line TCAM cell (100) based on a ternary memory cell according to one embodiment of the present invention has the major feature of being composed of a single-bit line.
[0034] A ternary CMOS-based single-bit line TCAM cell (100) according to an embodiment of the present invention illustrated in FIG. 1 comprises a first inverter (INV1) and a second inverter (INV2) that are cross-connected at a first node (N1) and a second node (N2); a first access transistor (M1) connected between a fourth node (N4) and ground, with a third node (N3) connected to its gate; a second access transistor (M2) connected between the first node (N1) and a fifth node (N5), with a word line (WL) connected to its gate; a third access transistor (M3) connected between the fifth node and the third node, with the first node connected to its gate; a fourth access transistor (M4) connected between the fifth node (N5) and the third node (N3), with the second node (N2) connected to its gate; and a fifth access transistor connected between the third node (N3) and the first node (N1), with the fifth node (N5) connected to its gate. It includes a transistor (M5) and a sixth access transistor (M6) connected between the third node (N3) and the second node (N2), with the fifth node (N5) connected to the gate.
[0035] At this time, the first access transistor (M1), the second access transistor (M2), the fourth access transistor (M4), and the sixth access transistor (M6) are NMOS, and the third access transistor (M3) and the fifth access transistor (M5) are preferably manufactured as PMOS.
[0036] And, referring again to FIG. 1, the first node (N1) is a Q node, the second node (N2) is a QB node, the third node (N3) is marked as X in the truth table, the fourth node (N4) is a node connected to a match line (ML), and the fifth node (N5) is a node connected to a bit line (BL) and a search line (SL).
[0037] The ternary CMOS-based TCAM cell (100) illustrated in FIG. 1 is a circuit diagram for a new single-bit line TCAM (Ternary Content-Addressable Memory) based on T-CMOS capable of writing and searching operations. For writing and reading operations, a word line (WL) voltage is applied to the gate of an access transistor and a bit line (BL) voltage is applied to the drain, and for searching operations, a search line (SL) is applied. At this time, Match and mismatch operations are performed according to changes in the value of the match line (ML).
[0038] When Q, QB=0.5 (VDD / 2), it operates like a Match regardless of the SL value and is called a don't care state.
[0039] To explain this in detail, the ternary memory cell (100) is configured to store a ternary value corresponding to a first state in which the pull-up elements and pull-down elements of the first inverter (INV1) and the second inverter (INV2) are all turned off, a second state in which the pull-up elements of the first inverter (INV1) and the pull-down elements of the second inverter (INV2) are turned on and the pull-down elements of the first inverter (INV1) and the pull-up elements of the second inverter (INV2) are turned off, and a third state in which the pull-up elements of the first inverter (INV1) and the pull-down elements of the second inverter (INV2) are turned off and the pull-down elements of the first inverter (INV1) and the pull-up elements of the second inverter (INV2) are turned on.
[0040] At this time, the first inverter and the second inverter of the ternary memory cell are cross-connected at the first node and the second node, and include a pull-up element configured to pass a first constant current when turned off and a pull-down element configured to pass a second constant current when turned off.
[0041] Accordingly, ternary information having three states is stored in each ternary memory cell, and a search line signal (SL) is applied to the access transistor to utilize it in search mode, thereby providing a memory address search function based on the corresponding information and the information of the line corresponding to the search line.
[0042] Meanwhile, in search mode, after writing the values (0, 0.5, 1) to Q and QB through a write operation, a voltage is applied to SL; if the values of Q(QB) and SL are the same, a match operation is performed, and if they are different, a mismatch operation is performed. When Q and QB are 0.5, the state becomes match (don't care state) regardless of the values of SL and SLB.
[0043] Figure 2 shows the operation truth table of the TCAM cell illustrated in Figure 1.
[0044] Referring to Fig. 2, after writing the values (0, 0.5, 1) to Q and QB through a write operation, a voltage is applied to the search line (SL). If the values of Q(QB) and SL are the same, a match operation is performed; if they are different, a mismatch operation is performed. When Q and QB are 0.5, the state becomes a match (don't care state) regardless of the search line (SL) value. At this time, VA and VB <VT,M1 이다.
[0045] FIG. 3 schematically illustrates the configuration of a single-bit line TCAM cell based on a ternary memory cell according to another embodiment of the present invention.
[0046] Referring to FIG. 3, a single-bit line TCAM cell (200) based on a ternary memory cell according to another embodiment of the present invention is a case in which, in addition to being composed of a single-bit line, the comparison circuitry is composed of three transistors and is a 9T cell.
[0047] A single-bit line TCAM cell (200) based on a ternary memory cell according to another embodiment of the present invention illustrated in FIG. 3 comprises a first inverter (INV1) and a second inverter (INV2) that are cross-connected at a first node (N1) and a second node (N2); a first access transistor (M1) connected between a fourth node (N4) and ground, with a third node (N3) connected to its gate; a second access transistor (M2) connected between the first node (N1) and a fifth node (N5), with a word line (WL) connected to its gate; a third access transistor (M3) connected between the first node (N1) and the third node (N3), with the fifth node (N5) connected to its gate; a fourth access transistor (M4) connected between the fifth node (N5) and the third node (N3), with the second node (N2) connected to its gate; and a fifth Node (N5) includes a fifth access transistor (M5) connected to a gate.
[0048] And at this time, the first access transistor (M1), the second access transistor (M2), the fourth access transistor (M4), and the fifth access transistor (M5) are NMOS, and the third access transistor (M3) is composed of PMOS.
[0049] In FIG. 3, the first node (N1) is a Q node, the second node (N2) is a QB node, the third node (N3) is marked as X in the truth table, the fourth node (N4) is a node connected to a match line (ML), and the fifth node (N5) is a node connected to a bit line (BL) and a search line (SL).
[0050] Figure 4 shows the operation truth table of the TCAM cell illustrated in Figure 3.
[0051] Referring to FIG. 4, after writing the values (0, 0.5, 1) to the first node (Q) and the second node (QB) through a write operation, a voltage is applied to the search line (SL). If the values of Q (QB) and SL are the same, a match operation is performed; if they are different, a mismatch operation is performed. When Q and QB are 0.5, the state becomes a match (don't care state) regardless of the search line (SL) value. At this time, VA and VB <VT,M1 이다.
[0052] FIG. 5 shows a TCAM array using a single-bit line TCAM cell based on a ternary memory cell according to the present invention.
[0053] Referring to FIG. 5, as an example of the operation of a single-bit line TCAM array based on a ternary memory cell according to the present invention illustrated in FIG. 1 and FIG. 3, the Q_1, ..., Q_m, of all high-density TCAM cells connected to ML_1 must each match the values SL_1, ..., SL_m, respectively, for the ML result to be 1. Therefore, the address of the matching data can be output.
[0054] To explain this in detail, the ternary memory cell-based single-bit line TCAM array (10) according to the present invention comprises a plurality of ternary memory cell-based single-bit line TCAM cells (100) arranged in a matrix of size nxm, m match lines (ML_1 to ML_m) each connected to n TCAM cells in the same row, m word lines (WL_1 to WL_m) each connected to n TCAM cells in the same row, n bit lines and search lines (BL_1 / SL_1 to BL_n / SL_n) each connected to m TCAM cells in the same column, and at least a word line and search string driving driver (11) for driving the word lines and match lines.
[0055] In FIG. 5, the TCAM cell according to the first embodiment, 100, is indicated as the reference numeral for the TCAM cell, but the TCAM cell (200) of the second embodiment may be used.
[0056] That is, as an example of array operation of a TCAM based on a ternary memory cell (T-CMOS) according to the present invention, the Q_1, QB_1, ... Q_m, QB_m of all ternary memory cells connected to BL_1 of FIG. 5 must each match the values of SL_1, ..., SL_m, respectively, so that the result of the AND gate coming out through BL_1 becomes 1. Therefore, the address of the matching data can be output.
[0057] Referring to FIG. 5, when the ternary memory cell operates in write and read mode, the wordline_search string driver (11) applies a voltage of 1 to the word line (WL) to connect the bit line (BL) to the second node (N2) to perform the write and read mode.
[0058] At this time, the ternary memory cell may have three different states and, accordingly, may store ternary logical values corresponding to the three different states, and thus may be referred to as ternary memory cells. The ternary logical values stored in the ternary memory cell may be referred to in various ways, such as '0', '1', '0.5' or '0', '1', '2' or 'first value', 'second value', 'third value' or 'first state', 'second state', 'third state', and may simply be referred to as ternary values.
[0059] As illustrated in FIG. 5, one word line (WL) of a plurality of word lines is connected to the gate of a third access transistor (AT3) in a ternary memory cell, and the ternary memory cell stores a ternary logic value provided through at least one bit line (BL).
[0060] A memory device (not shown) may have a logic-in-memory (LIM) structure. Logic-in-memory (LIM) may refer to a memory that outputs the result of a logical operation on a value stored in a memory element, or may refer to a logic operation circuit equipped with a memory function. A ternary memory cell may include a logic operation circuit (not shown) and may be connected to at least one input line (IL) among a plurality of input lines. The logic operation circuit may perform a logical operation on a ternary value stored in the ternary memory cell and a ternary value provided from a page buffer (not shown) through at least one input line (IL), and may provide the result of the logical operation to the page buffer. The page buffer may latch the value to be stored during a write operation, the value read during a read operation, as well as the result of the logical operation. In the present specification, a write operation may refer to an operation for storing data (or a value) in a ternary memory cell (110), a read operation may refer to an operation for outputting data stored in the ternary memory cell to the outside of the memory device, and a logical operation operation may refer to an operation for outputting the result of a logical operation on data stored in the ternary memory cell in the memory device to the outside of the memory device.
[0061] A page buffer may be connected to a cell array through a plurality of bit lines (BLs). The page buffer may include at least one latch and, during a write operation, may latch data to be written to the cell array, i.e., write data, while during a read operation, it may latch data read from the cell array, i.e., read data. The page buffer may include a write circuit, and the write circuit may apply voltages and / or currents based on the write data to the plurality of bit lines (BLs) during a write operation. Additionally, the page buffer may include a read circuit, and the read circuit may generate read data by detecting voltages and / or currents of the plurality of bit lines (BLs) during a read operation.
[0062] The following detailed description of the structure and operation of the ternary memory cell in write and read modes is omitted here because it is described in Korean Registered Patent No. 10-1689159 and Korean Registered Patent No. 10-2206020.
[0063] As such, according to the present invention, a high-density TCAM circuit composed of a T-CMOS-based T-SRAM structure can be provided. Furthermore, the T-SRAM constituting the high-density TCAM of the present invention can provide very low standby power consumption characteristics by storing ternary information based on a low current at the Off level.
[0064] In addition, the high-density TCAM of the present invention can store ternary information with only one memory cell configuration to provide 0, 1, and X operations with high area efficiency, and the high-density TCAM of the present invention can provide operation with high area efficiency by applying a WL voltage to the gate of the access transistor during read and write operations and applying a search line (SL) voltage during search operations.
[0065] Through this, the single-bit line TCAM cell based on a ternary memory cell according to the present invention can provide a TCAM circuit composed of a T-CMOS-based ternary memory, and the circuit can serve as a core component of ultra-low power, high-performance memory address search hardware.
[0066] The new TCAM according to the present invention can be composed of a T-CMOS-based T-SRAM cell in the same manner as a conventional SRAM, and WL is applied to the access transistor during read and write operations, and a search line (SL) voltage can be applied during search operations. The ML, whose voltage is raised through a pre-charge operation, can perform a memory address search function by maintaining the voltage as is or discharging it according to two search line signal values different from the stored value.
[0067] When SL and Q(QB) values are the same, Node A becomes 0 and outputs an ML value of 1, at which point it enters the Match state. When SL and Q(QB) values are different, it enters the Mismatch state. When Q and QB are in the Don't Care state, it enters the Match state regardless of the search line value.
[0068] In this way, the single-bit line TCAM cell based on a ternary memory cell (ternary CMOS) according to the present invention can realize ultra-low power, high-performance, and highly integrated memory address search hardware by providing a TCAM circuit composed of a T-CMOS-based T-SRAM cell and one element for address search.
[0069] Furthermore, by designing a TCAM circuit based on ultra-low power T-CMOS devices, information storage utilizing very low current at the off-state level enables significantly reduced power consumption along with superior area efficiency compared to conventional CAM technology. This can meet the growing demand for memory address lookup hardware capable of ultra-low power, high-performance operation for more complex and abundant information in next-generation routers and switch devices, driven by recent advancements in meta-learning and few-shot learning. Additionally, integration density can be significantly improved by reducing the number of transistors from 16 to 9, a 44% reduction from the existing TCAM structure.
[0070] Although the present invention has been described above with specific details such as specific components, limited embodiments, and drawings, this is provided only to aid in a more comprehensive understanding of the invention, and the invention is not limited to the above embodiments, and a person skilled in the art to which the invention belongs can make various modifications and variations from this description.
[0071] Accordingly, the scope of the present invention should not be limited to the embodiments described above, and all modifications equivalent to or equivalent to the claims set forth below, as well as the claims described below, shall be considered to fall within the scope of the concept of the present invention.
Claims
1. In a single-bit line TCAM cell based on a binary memory cell, A first inverter and a second inverter that are cross-connected at the first node and the second node; A first access transistor (M1) connected between the fourth node and ground, with the third node connected to the gate; A second access transistor (M2) connected between the first node and the fifth node, with a word line (WL) connected to the gate; A third access transistor (M3) connected between the fifth node and the third node, with the first node connected to the gate; A fourth access transistor (M4) connected between the fifth node and the third node, with the second node connected to the gate; A fifth access transistor (M5) connected between the third node and the first node and connected to the gate of the fifth node; and A sixth access transistor (M6) connected between the third node and the second node and connected to the gate of the fifth node A single-bit line TCAM cell based on a ternary memory cell, characterized by including 2. In Paragraph 1, The first access transistor (M1), the second access transistor (M2), the fourth access transistor (M4), and the sixth access transistor (M6) are NMOS transistors, and A single-bit line TCAM cell based on a ternary memory cell, characterized in that the third access transistor (M3) and the fifth access transistor (M5) are PMOS.
3. In Paragraph 2, The first node above is the Q node, and the second node above is the QB node, and The above-mentioned fourth node is a node to which a match line (ML) is connected, and A single bit line TCAM cell based on a ternary memory cell, characterized in that the above-mentioned fifth node is a node to which a bit line (BL) and a search line (SL) are connected. In a single-bit line TCAM array based on 4.3-bit memory cells, A single-bit line TCAM cell based on a plurality of ternary memory cells arranged in the form of an nxm matrix; m match lines, each connected to n TCAM cells in the same row; m word lines connected to each of the n TCAM cells in each of the same row; n bit lines and search lines connected to each of the m TCAM cells in each of the same column; and At least a word line and search string driving driver for driving the above word line and match line; Includes, The above-mentioned ternary memory cell-based single-bit line TCAM cell is, A first inverter and a second inverter that are cross-connected at the first node and the second node; A first access transistor (M1) connected between the fourth node and ground, with the third node connected to the gate; A second access transistor (M2) connected between the first node and the fifth node, with a word line (WL) connected to the gate; A third access transistor (M3) connected between the fifth node and the third node, with the first node connected to the gate; A fourth access transistor (M4) connected between the fifth node and the third node, with the second node connected to the gate; A fifth access transistor (M5) connected between the third node and the first node and connected to the gate of the fifth node; and A sixth access transistor (M6) connected between the third node and the second node and connected to the gate of the fifth node A single-bit line TCAM array based on a ternary memory cell, characterized by including 5. In Paragraph 4, The first access transistor (M1), the second access transistor (M2), the fourth access transistor (M4), and the sixth access transistor (M6) are NMOS transistors, and A ternary memory cell-based single-bit line TCAM array characterized in that the third access transistor (M3) and the fifth access transistor (M5) are PMOS.
6. In Paragraph 5, The first node above is the Q node, and the second node above is the QB node, and The above-mentioned fourth node is a node to which a match line (ML) is connected, and A ternary memory cell-based single bit line TCAM array characterized in that the fifth node is a node to which a bit line (BL) and a search line (SL) are connected. In a single-bit line TCAM cell based on a 7.3-bit memory cell, A first inverter and a second inverter that are cross-connected at the first node and the second node; A first access transistor (M1) connected between the fourth node and ground, with the third node connected to the gate; A second access transistor (M2) connected between the first node and the fifth node, with a word line (WL) connected to the gate; A third access transistor (M3) connected between the first node and the third node, with the fifth node connected to the gate; A fourth access transistor (M4) connected between the fifth node and the third node, with the second node connected to the gate; and A fifth access transistor (M5) connected between the second node and the third node and connected to the gate of the fifth node A single-bit line TCAM cell based on a ternary memory cell, characterized by including 8. In Paragraph 7, The first access transistor (M1), the second access transistor (M2), the fourth access transistor (M4), and the fifth access transistor (M5) are NMOS transistors, and A single-bit line TCAM cell based on a ternary memory cell, characterized in that the third access transistor (M3) is a PMOS.
9. In Paragraph 8, The first node above is the Q node, and the second node above is the QB node, and The above-mentioned fourth node is a node to which a match line (ML) is connected, and A single bit line TCAM cell based on a ternary memory cell, characterized in that the above-mentioned fifth node is a node to which a bit line (BL) and a search line (SL) are connected. In a single-bit line TCAM array based on 10.3-digit memory cells, A single-bit line TCAM cell based on a plurality of ternary memory cells arranged in the form of an nxm matrix; m match lines, each connected to n TCAM cells in the same row; m word lines connected to each of the n TCAM cells in each of the same row; n bit lines and search lines connected to each of the m TCAM cells in each of the same column; and At least a word line and search string driving driver for driving the above word line and match line; Includes, The above-mentioned ternary memory cell-based single-bit line TCAM cell is, A first inverter and a second inverter that are cross-connected at the first node and the second node; A first access transistor (M1) connected between the fourth node and ground, with the third node connected to the gate; A second access transistor (M2) connected between the first node and the fifth node, with a word line (WL) connected to the gate; A third access transistor (M3) connected between the first node and the third node, with the fifth node connected to the gate; A fourth access transistor (M4) connected between the fifth node and the third node, with the second node connected to the gate; and A fifth access transistor (M5) connected between the second node and the third node and connected to the gate of the fifth node A single-bit line TCAM array based on a ternary memory cell, characterized by including 11. In Paragraph 10, The first access transistor (M1), the second access transistor (M2), the fourth access transistor (M4), and the fifth access transistor (M5) are NMOS transistors, and A single-bit line TCAM array based on a ternary memory cell, characterized in that the third access transistor (M3) is a PMOS.
12. In Paragraph 11, The first node above is the Q node, and the second node above is the QB node, and The above-mentioned fourth node is a node to which a match line (ML) is connected, and A ternary memory cell-based single bit line TCAM array characterized in that the fifth node is a node to which a bit line (BL) and a search line (SL) are connected.