Delay chain analysis system and method

Abstract

This invention provides a delay chain analysis system, including a test signal generator, an FPGA chip, and a host computer. The FPGA chip includes a delay chain module and an integrated logic analyzer. The delay chain module includes one or more delay chains. The host computer includes a test controller and a data analyzer. The test signal generator is connected to the FPGA chip, the output of the delay chains is connected to the integrated logic analyzer, and the output of the integrated logic analyzer is connected to the host computer. The test signal generator generates a test signal close to the clock of the delay chains. The delay chains are used to measure minute time intervals. The integrated logic analyzer continuously captures the temperature codes output by the delay chain registers at the rising edge of the clock and transmits them to the host computer. The test controller controls the test process, receives the temperature codes output by the integrated logic analyzer, and stores them as an analyzable file. The data analyzer analyzes the file stored by the test controller to generate a delay time schedule. This invention can reduce the actual bit error rate of the delay chains.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a delay chain analysis system and method. Background Technology

[0002] A time-to-digital converter (TDC) is a device that converts analog quantities into digital quantities in the time domain. It is generally used in fields requiring high-precision time measurement, such as satellite synchronization and lidar ranging. The advantage of implementing it using an FPGA is its programmability and integrability. The Tapped Delay Line (TDL) architecture based on a carry-lookahead adder is currently the mainstream FPGA-TDC structure. This is because, within the internal hardware circuitry of an FPGA, the adder carry chain has the smallest propagation time interval.

[0003] The challenge of this technology lies in the measurement and calibration of the delay chain. Traditionally, delay chain code density testing uses a low-frequency incoherent signal as the test signal. When the amount of test data is large enough, it is assumed that the test signal falls uniformly on the delay chain, and the number of test signals falling in each delay unit reflects the delay time of each unit. In FPGAs with lower process technology and simpler physical structure of the delay chain, this can reflect the signal transmission well.

[0004] The carry of the adder itself is not an ideal delay unit. Due to the nature of the carry-lookahead adder, its carry is not output in complete order, which causes the output of the delay chain to have a large bubble error, resulting in distortion and reducing the time measurement resolution of the system. Summary of the Invention

[0005] The delay chain analysis system and method provided by this invention can reduce the actual bit error rate of the delay chain and improve the time measurement resolution of the system.

[0006] In a first aspect, the present invention provides a delay chain analysis system, the system comprising a test signal generator, an FPGA chip, and a host computer; the FPGA chip includes a delay chain module and an integrated logic analyzer, the delay chain module including one or more delay chains, and the host computer including a test controller and a data analyzer; the test signal generator is connected to the FPGA chip, the output of each delay chain is connected to the integrated logic analyzer, and the output of the integrated logic analyzer is connected to the host computer; wherein...

[0007] The test signal generator is used to generate a test signal that is close to the delay chain clock.

[0008] The delay chain is used to measure minute intervals of time;

[0009] The integrated logic analyzer is used to continuously capture the temperature code output by the clock rising edge delay chain register and transmit this temperature code to the host computer.

[0010] The test controller is used to control the test process, receive the temperature code output by the integrated logic analyzer, and store it as an analyzable file.

[0011] The data analyzer is used to analyze the files stored by the test controller to generate a delay schedule.

[0012] Optionally, the host computer also includes a constraint generator for generating constraint files for the FPGA, controlling the position of the delay chain, and optimizing the overall timing of the FPGA.

[0013] Optionally, the test signal generator uses a high-precision signal generator or a high-precision on-chip adjustable clock chip to generate a square wave signal or a sine wave signal with a 50% duty cycle.

[0014] Optionally, the multiple delay chains in the delay chain module have the same structure, including a delay signal chain connected in sequence and a D flip-flop connected to each delay signal chain respectively; wherein, the delay signal chain is selected as a carry-lookahead adder carry chain, and the D flip-flop connected to the delay signal chain and the adder are located in the same FPGA slice structure.

[0015] Optionally, the test controller and constraint generator are composed of TCL scripts.

[0016] Secondly, the present invention provides a delay chain analysis method, the method comprising:

[0017] Determine system parameters;

[0018] The test clock is connected to multiple delay chains to obtain the temperature code measurement results of multiple delay chains. The temperature code results of multiple delay chains are captured by the integrated logic analyzer, and the data of each delay chain is stored as an analyzable file.

[0019] Analyze multiple sets of data from a single test collected by the integrated logic analyzer;

[0020] The test data of the same delay chain are fitted to form the statistical results of bit error and trigger count of multiple test fittings;

[0021] The delay schedule is obtained by integrating the statistical results of bit errors and trigger counts from the multiple tests.

[0022] Optionally, the parameters include: test clock, single capture length of integrated logic analyzer, trusted error length, trusted stable signal length, and analysis unit length.

[0023] Optionally, the analysis of multiple sets of data from a single test collected by the integrated logic analyzer includes: processing a single file to obtain statistical results of the bit errors and the number of triggers in a single test, specifically:

[0024] Establish a bit error trigger frequency table based on the analysis unit;

[0025] The data is traversed. For each delay unit, if the bit error triggered this time is different from the bit error triggered by the previous data, it is entered into the table as a newly discovered bit error and the trigger count is recorded as 1. If the bit error triggered this time is the same as the bit error triggered by the previous data, the trigger count of this bit error is incremented by 1.

[0026] After the traversal is complete, the frequency table is saved in a file.

[0027] Optionally, fitting the test data from multiple tests on the same delay chain includes:

[0028] Read a test frequency table and build a total frequency table based on it.

[0029] Read an unprocessed frequency table. For the same bit error, add their trigger counts to the total frequency table. For bit errors that do not appear in the total frequency table, insert them into the total frequency table according to their trigger positions.

[0030] After traversing all test frequency tables for this delay chain, save the total frequency table;

[0031] Based on the total frequency table and the delay chain clock, the corresponding delay time table is obtained by integration.

[0032] Optionally, integrating the statistical results of the bit errors and trigger counts fitted from the multiple tests to obtain the delay schedule includes:

[0033] Calculate the bit error delay time;

[0034] Combine error delay times into a delay schedule.

[0035] The delay chain analysis system and method provided in this invention can convert bit errors on the delay chain into virtual delay units, which can not only reduce the actual bit errors of the delay chain, but also make the delay chain more subdivided than the ideal bit-free case, thereby improving the time measurement resolution of the system. Attached Figure Description

[0036] Figure 1 This is a structural block diagram of the delay chain analysis system provided in an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of the coherent sampling principle provided in an embodiment of the present invention;

[0038] Figure 3 A flowchart of the delay chain analysis method provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram illustrating the principle of single-test data error merging provided in an embodiment of the present invention.

[0040] Figure 5 This is a schematic diagram illustrating the principle of fitting multiple test data provided in an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] This invention provides a delay chain analysis system, such as... Figure 1 As shown, the system includes a test signal generator, an FPGA chip, and a host computer; the FPGA chip includes a delay chain module and an integrated logic analyzer, the delay chain module includes one or more delay chains, and the host computer includes a test controller and a data analyzer; the test signal generator is connected to the FPGA chip, the output of the delay chain is connected to the integrated logic analyzer, and the output of the integrated logic analyzer is connected to the host computer; wherein,

[0043] The test signal generator, such as Figure 2 As shown, it is used to generate a test signal close to the delay chain clock in order to achieve the purpose of step testing;

[0044] The delay chain is used to measure minute intervals of time;

[0045] The integrated logic analyzer is used to continuously capture the temperature code output by the clock rising edge delay chain register and transmit this temperature code to the host computer.

[0046] The test controller is used to control the test process, receive the temperature code output by the integrated logic analyzer, and store it as an analyzable file.

[0047] The data analyzer is used to analyze the files stored by the test controller to generate a delay schedule.

[0048] Furthermore, the host computer also includes a constraint generator, used to generate constraint files for the FPGA, control the position of the delay chain, and optimize the overall timing of the FPGA.

[0049] Preferably, the test signal generator uses a high-precision signal generator or a high-precision on-chip adjustable clock chip to generate a square wave signal or a sine wave signal with a 50% duty cycle.

[0050] Preferably, the multiple delay chains in the delay chain module have the same structure, including a delay signal chain connected in sequence and a D flip-flop connected to each delay signal chain respectively; wherein, the delay signal chain is selected as a carry-lookahead adder carry chain, and the D flip-flop connected to the delay signal chain is located in the same FPGA slice structure as the adder.

[0051] The integrated logic analyzer is used to collect the temperature code output by the delayed chain D flip-flop group in each cycle.

[0052] Preferably, the number of acquisition cycles of the integrated logic analyzer is as large as possible while meeting timing requirements.

[0053] Preferably, the constraint generator and test controller are composed of TCL scripts.

[0054] In this embodiment of the invention, multiple delay chains are measured simultaneously, reducing the delay chain testing time. This method can be used for parallel measurement of multiple delay chains, thereby improving measurement accuracy.

[0055] Optionally, in this embodiment, the number of delay chains is 6.

[0056] Optionally, the data analyzer is used to analyze the data files stored by the test controller, and improve the accuracy of delay chain testing by using a method of analyzing a single file and fitting multiple files, thereby forming a delay schedule.

[0057] In this embodiment, the test signal generator is implemented using an onboard high-precision clock generator. The test clock is 499.5MHz, the delay chain clock is 500MHz, and the delay chain scan step size is set to 1ps. The total delay time of the delay chain is one clock cycle, i.e., 2000ps, thus allowing for sequential testing of the delay chain in 2000 equal divisions.

[0058] The delay chain module consists of a 640-bit carry-lookahead adder carry chain, where each carry-lookahead adder is an 8-bit carry-lookahead adder. As the test signal propagates along the delay chain, the adder carry is continuously pulled high, and the signal edge moves towards a longer delay. When the delay chain clock signal goes high, a series of D flip-flops connected to the adder latch the current delay chain state, forming a 640-bit temperature code.

[0059] The integrated logic analyzer is used to transmit the internal signal waveforms of the FPGA to the host computer. The single capture length is 4096. It is triggered when a change in the temperature code is captured and the data is saved as an analyzable file in real time.

[0060] The delay chain analysis system provided in this invention can convert bit errors on the delay chain into virtual delay units, which not only reduces the actual bit errors in the delay chain, but also makes the delay chain more subdivided than the ideal bit-free case, thus improving the system's time measurement resolution. It can be implemented by a built-in integrated logic analyzer, making it simple to use and effective.

[0061] This invention also provides a delay chain analysis method. The basis of this method lies in the identification of analysis units, which can be arbitrarily divided and are not necessarily related to the physical structure of the delay chain. In the analysis, it is assumed that all stable transitions from one analysis unit to the next are considered errors, and all temperature code states between these stable transitions are considered erroneous. Based on this, the analysis method is valid.

[0062] In the field of time measurement, FPGA-based time measurement typically implements a delay chain by using a carry-lookahead adder. Due to the inherent errors in the physical design of the adder itself and the FPGA clock module, as well as random jitter in the system, bit errors often appear in the delay chain measurement results, which is particularly noticeable in advanced process FPGAs.

[0063] like Figure 3 As shown, the delay chain analysis method provided in this embodiment of the invention includes:

[0064] S11. Determine system parameters.

[0065] The parameters may include: test clock A, and the single-pass length N of the integrated logic analyzer. sync Trusted error length L b , reliable and stable signal length L s Analysis unit length M;

[0066] The trusted error length L b , refers to the maximum acceptable bit error length before the signal stabilizes at 0 or 1 at the signal transition edge, based on actual test conditions and actual signal patterns;

[0067] The length of the reliable stable signal L s Based on actual test conditions and actual signal patterns, this refers to the minimum length of the signal transition edge used to determine whether the transition has stabilized at 0 or 1, and whether the signal is all 1s or all 0s.

[0068] The length M of the analysis unit refers to the number of bits occupied by the analysis unit in the temperature code.

[0069] S12. Connect the test clock A to multiple delay chains respectively, obtain the temperature code measurement results of multiple delay chains, capture the temperature code results of multiple delay chains respectively through the integrated logic analyzer, and store the data of each delay chain as an analyzable file.

[0070] S13. Analyze multiple sets of data from a single test collected by the integrated logic analyzer.

[0071] The data analysis methods for the multiple delay chains are the same.

[0072] Specifically, the data of a single file is first processed to obtain statistical results of the bit errors and the number of times they are triggered in a single test.

[0073] S14. Fit multiple test data of the same delay chain to form statistical results of bit error rate and trigger count for multiple test fittings.

[0074] S15. Integrate the statistical results of the bit error rate and trigger count of the multiple tests to obtain the delay schedule.

[0075] Preferably, the frequency of the test clock A is determined based on the delay chain clock B and the predetermined scan step size T. step The scan step size T is determined. step This is the period difference between the delay chain clock B and the test clock A. Due to the period difference between the two signals, the rising time of each rising edge of the delay chain clock B and the rising time of the test clock A relative to the previous period increases by T. step This continues until the rising edges of the two signals coincide again, thus achieving a fine traversal of the delay chain, T. step This represents the resolution of the measurement. Therefore, the frequency F of the test clock A is... A This can be derived from the following formula:

[0076]

[0077] Among them, F B The frequency of delay chain clock B.

[0078] Preferably, the integrated logic analyzer captures a waveform of length N in a single operation. sync The single capture cycle length of the integrated logic analyzer needs to be greater than or equal to the number of cycles required for the rising edge of test clock A to coincide with the rising edge of delay chain clock B.

[0079] Waveform length N captured in a single operation sync Delay chain clock B and scan step size T step Decide.

[0080]

[0081] Preferably, the analysis unit length M is divided according to the physical structure. For example, in the carry delay chain of a carry-lookahead adder, if one or more adders are used as analysis units, the analysis unit length M is the number of bits of the one or more carry-lookahead adders.

[0082] For any delay chain, the first step is to analyze multiple sets of data from a single test. Since the test is performed through coherent sampling, the principle of processing the single test frequency data is as follows: Figure 4 As shown, the specific steps include the following:

[0083] S131. Create an empty table to count the number of errors and their trigger counts at each analysis unit.

[0084] S132. Traverse the temperature code in the direction from longest to shortest delay chain to find the first reliable and stable signal length L. s The jump position L0.

[0085] S133. Determine whether L0 is divisible by the length M of the analysis cell. If it is divisible, it means that this position is at the boundary of the current analysis cell. If it is not divisible, then the nearest divisible position is taken as the boundary L1 of the current analysis cell.

[0086] S134, Read the temperature code before L1 position L b The temperature code is counted as the error code of the current analysis unit.

[0087] S135. If this error has not been triggered before or is different from the previous error, add it as a new error; otherwise, increment the trigger count of this error by 1.

[0088] S136. For each data point in the integrated logic analyzer data, repeat steps S132-S135 until the entire file has been analyzed.

[0089] S137. Iterate through all the errors in each analysis unit. For the same error triggered at different times, add up the number of triggers and merge them into the position with the most triggers.

[0090] like Figure 5 As shown, the principle of fitting multiple test data at the same location specifically includes the following steps:

[0091] S141. Read a set of analytical data and fit it to the benchmark.

[0092] S142. Read one set of analytical data to be fitted and insert it into the baseline data as supplementary data;

[0093] S143. For errors in the supplementary data, if they exist in the first file, add the number of times the error was triggered in the baseline data to the number of times the error was triggered in the baseline data as the result.

[0094] S144. If an error in the supplementary data does not exist in the first file, it shall be inserted after the previous identical error.

[0095] S145. All errors in the baseline data and supplementary data are merged to form combined data, which is then written to a new file.

[0096] S146. For tests conducted more than twice, repeat steps S142-S145 using the combined data as a baseline until all analytical data are properly fitted.

[0097] The specific components of the fitted data forming the time delay schedule include:

[0098] S151. Calculate the error delay time.

[0099] According to the following formula, the analysis unit location X, based on its physical location, is represented as X. [i] , where i is the order of the adders in the chain, and the error data Y is represented as Y [j] j represents the order in which errors were triggered at that position. (The last part, "falling on X," appears to be a typo and is left untranslated.) [i] Y [j] The number of trigger signals reflects the delay time of that bit error at that adder position. Therefore, the delay time represented by each bit error can be obtained. The formula is as follows:

[0100]

[0101] S152. Combine the error delay times into a delay time table.

[0102] The total number of analysis units is m, and the number of bit errors in each analysis unit is n. When the signal is read at the rising edge in adder s, at the t-th bit error, the timing results are as follows:

[0103]

[0104] In this embodiment, the main testing error originates from the jitter of the test clock and the delay chain clock, which can cause the temperature code to jump back and forth when switching between the two error types. The jitter of the two signals follows a normal distribution; therefore, by performing multi-cycle testing and fitting a large amount of test data, the reliability of the final data table can be improved. After 100 cycles of testing, the error rate in the delay chain tends to stabilize. At this point, the total number of error types N is approximately twice the number of delay chain units, and the intrinsic accuracy of the delay chain is doubled. Furthermore, there is no need to convert the temperature code to binary code, eliminating calculation errors.

[0105] The delay chain analysis method provided in this invention can transform bit errors on the delay chain into virtual delay units, which not only reduces the actual bit errors in the delay chain, but also provides a more detailed delay chain than the ideal error-free case, improving the system's time measurement resolution. Through coherent sampling, sequential traversal of the delay chain is achieved, enabling refined and sequential analysis of temperature code data, thereby effectively converting bit errors into usable delay units. Analyzing delay chain delays does not require converting the temperature code to binary code, eliminating the system errors associated with temperature code to binary code conversion.

[0106] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A delay chain analysis system, characterized in that, The system includes a test signal generator, an FPGA chip, and a host computer. The FPGA chip includes a delay chain module and an integrated logic analyzer. The delay chain module includes one or more delay chains. The host computer includes a test controller and a data analyzer. The test signal generator is connected to the FPGA chip, the output of each delay chain is connected to the integrated logic analyzer, and the output of the integrated logic analyzer is connected to the host computer. The test signal generator is used to generate a test signal that is close to the delay chain clock. The delay chain is used to measure minute intervals of time; The integrated logic analyzer is used to continuously capture the temperature code output by the clock rising edge delay chain register and transmit this temperature code to the host computer. The test controller is used to control the test process, receive the temperature code output by the integrated logic analyzer, and store it as an analyzable file. The data analyzer is used to analyze the files stored by the test controller to generate a delay schedule.

2. The system according to claim 1, characterized in that, The host computer also includes a constraint generator, which is used to generate constraint files for the FPGA, control the position of the delay chain, and optimize the overall timing of the FPGA.

3. The system according to claim 1 or 2, characterized in that, The test signal generator uses a high-precision signal generator or a high-precision on-chip adjustable clock chip to generate a square wave signal or sine wave signal with a 50% duty cycle.

4. The system according to claim 1 or 2, characterized in that, The multiple delay chains in the delay chain module have the same structure, including a delay signal chain connected in sequence and a D flip-flop connected to each delay signal chain respectively; wherein, the delay signal chain is a carry-lookahead adder carry chain, and the D flip-flops connected to the delay signal chain are located in the same FPGA slice structure as the adder.

5. The system according to claim 1 or 2, characterized in that, The test controller and constraint generator are composed of TCL scripts.

6. A delay chain analysis method, characterized in that, The method includes: Determine system parameters; The test clock is connected to multiple delay chains to obtain the temperature code measurement results of multiple delay chains. The temperature code results of multiple delay chains are captured by the integrated logic analyzer, and the data of each delay chain is stored as an analyzable file. Analyze multiple sets of data from a single test collected by the integrated logic analyzer; The test data of the same delay chain are fitted to form the statistical results of bit error and trigger count of multiple test fittings; The delay schedule is obtained by integrating the statistical results of bit errors and trigger counts from the multiple tests.

7. The method according to claim 6, characterized in that, The parameters include: test clock, single capture length of integrated logic analyzer, trusted error length, trusted stable signal length, and analysis unit length.

8. The method according to claim 6 or 7, characterized in that, The analysis of multiple sets of data from a single test collected by the integrated logic analyzer includes: processing data from a single file to obtain statistical results of the bit errors and the number of triggers in a single test, specifically: Establish a bit error trigger frequency table based on the analysis unit; The data is traversed. For each delay unit, if the bit error triggered this time is different from the bit error triggered by the previous data, it is entered into the table as a newly discovered bit error and the trigger count is recorded as 1. If the bit error triggered this time is the same as the bit error triggered by the previous data, the trigger count of this bit error is incremented by 1. After the traversal is complete, the frequency table is saved in a file.

9. The method according to claim 6 or 7, characterized in that, The fitting of multiple test data for the same delay chain includes: Read a test frequency table and build a total frequency table based on it. Read an unprocessed frequency table. For the same bit error, add their trigger counts to the total frequency table. For bit errors that do not appear in the total frequency table, insert them into the total frequency table according to their trigger positions. After traversing all test frequency tables for this delay chain, save the total frequency table; Based on the total frequency table and the delay chain clock, the corresponding delay time table is obtained by integration.

10. The method according to claim 6 or 7, characterized in that, The step of integrating the statistical results of the bit error rate and trigger count fitted by the multiple tests to obtain the delay schedule includes: Calculate the bit error delay time; Combine error delay times into a delay schedule.

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