Circuit analysis method and apparatus, electronic device, and storage medium

Abstract

The application relates to a circuit analysis method and device, electronic equipment and a storage medium. The circuit analysis device comprises an information module configured to acquire a plurality of layout units; an environment configuration module configured to set a corresponding layout parasitic parameter extraction environment based on the type and / or parameters of the layout units; and a batch processing module configured to batch extract a parasitic parameter netlist of the plurality of layout units in the layout parasitic parameter extraction environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a circuit analysis method and device, an electronic device, and a storage medium. BACKGROUND

[0002] Simulation can be divided into pre-simulation and post-simulation, and both processes should be included in a complete circuit design.

[0003] Pre-simulation is functional simulation, and the goal is to analyze the correctness of the logical relationship of the circuit, and the waveforms of any signal and register inside the circuit and the input and output ports of the circuit can be observed as needed. Pre-simulation is relatively ideal simulation and does not contain any physical information (such as parasitic effects, interconnection delays, etc.), and the simulation speed is fast.

[0004] Post-simulation is to simulate the extracted circuit netlist by adding parasitic parameters and interconnection delays, analyze the circuit, and ensure that the circuit meets the design requirements. The method used in post-simulation is not much different from that used in pre-simulation, except that parasitic parameters and interconnection delays are added. The speed of post-simulation is much slower than that of pre-simulation.

[0005] In the related art, as the scale of integrated circuits continues to increase, the number of transistors on the chip continues to increase, which leads to a sharp increase in the number of parasitic resistors and capacitors, and the time required for circuit post-simulation increases, and the circuit verification time becomes longer, which to some extent affects the chip design cycle and product delivery time. SUMMARY

[0006] To at least partially overcome the problems in the related art, the present application provides a circuit analysis method and device, an electronic device, and a storage medium.

[0007] In a first aspect, an embodiment of the present application provides a circuit analysis device, comprising:

[0008] An information module is configured to obtain a plurality of layout units; an environment configuration module is configured to set a corresponding layout parasitic parameter extraction environment one by one based on the types and / or parameters of the layout units; and a batch processing module is configured to extract the parasitic parameter netlist of the plurality of layout units in the layout parasitic parameter extraction environment.

[0009] In an optional embodiment, the environment configuration module is in communication with at least one EDA software, and the environment configuration module automatically configures the layout parasitic parameter extraction environment by calling the interface of the EDA software.

[0010] In an alternative embodiment, the environment configuration module is in communication with a plurality of EDA software of different types, and the environment configuration module automatically configures the layout parasitic parameter extraction environment of different types by invoking interfaces of the different EDA software.

[0011] In an alternative embodiment, the environment configuration module is further configured to set a GDS export environment, and the batch processing module comprises an export module configured to batch export GDS files of the layout units in the GDS export environment.

[0012] In an alternative embodiment, the information module is further configured to obtain a circuit unit corresponding to the layout unit, and the environment configuration module is further configured to set a netlist export environment, and the export module is further configured to batch export a circuit netlist of the circuit unit in the netlist export environment.

[0013] In an alternative embodiment, the environment configuration module is further configured to set a verification environment, and the batch processing module further comprises a verification module configured to perform layout versus circuit verification based on the GDS files and the circuit netlist in the verification environment.

[0014] In an alternative embodiment, the apparatus further comprises a result output module configured to generate a report corresponding to the layout units according to a verification result of the layout versus circuit verification and the parasitic netlist.

[0015] In an alternative embodiment, the apparatus further comprises a simulation module configured to perform post-simulation according to the parasitic netlist output by the batch processing module.

[0016] In an alternative embodiment, the information module has a graphical interactive interface for obtaining the layout units.

[0017] In a second aspect, an embodiment of the present application provides a circuit analysis method, which comprises: obtaining a plurality of layout units; setting a corresponding layout parasitic parameter extraction environment based on a type and / or a parameter of each layout unit; and batch extracting a parasitic netlist of each layout unit in the layout parasitic parameter extraction environment.

[0018] In an alternative embodiment, the setting of the corresponding layout parasitic parameter extraction environment based on the type and / or the parameter of each layout unit comprises: automatically configuring the layout parasitic parameter extraction environment by invoking an interface of EDA software.

[0019] In an optional implementation, the setting of the layout parasitic parameter extraction environment corresponding to each of the layout units based on the type and / or parameter of the layout unit comprises: automatically configuring the layout parasitic parameter extraction environment of different types by calling the interface of different EDA software.

[0020] In an optional implementation, before the batch extraction of the parasitic parameter netlist of the plurality of layout units in the environment, the method further comprises: setting a GDS export environment, and batch exporting GDS files of the layout units in the GDS export environment.

[0021] In an optional implementation, the setting of the layout parasitic parameter extraction environment corresponding to each of the layout units based on the type and / or parameter of the layout unit comprises: setting a netlist export environment.

[0022] The obtaining of the plurality of layout units comprises: obtaining a circuit unit corresponding to the layout unit.

[0023] The method further comprises: batch exporting a circuit netlist of the circuit unit in the netlist export environment.

[0024] In an optional implementation, the setting of the layout parasitic parameter extraction environment corresponding to each of the layout units based on the type and / or parameter of the layout unit further comprises: setting a verification environment.

[0025] The method further comprises: performing layout versus circuit verification based on the GDS file and the circuit netlist in the verification environment.

[0026] In an optional implementation, the method further comprises: generating a report corresponding to the layout unit according to the verification result of the layout versus circuit verification and the parasitic parameter netlist.

[0027] In an optional implementation, the method further comprises: performing post-simulation according to the parasitic parameter netlist.

[0028] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory configured to store a computer program; and a processor configured to execute the computer program in the memory to implement the operation steps of the method in any one of the second aspect.

[0029] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the operation steps of the method in any one of the second aspect.

[0030] The scheme of the present application can provide an environment configuration module to set a corresponding layout parasitic parameter extraction environment based on the type and / or parameters of a layout unit, and then batch extract the parasitic netlist of multiple layout units. In this way, the user does not need to manually perform complex environment settings, and can also batch extract the parasitic netlist of multiple layout units in an automatically set environment. This can greatly reduce the time of parasitic parameter extraction, thereby shortening the time required for circuit post-simulation. BRIEF DESCRIPTION OF DRAWINGS

[0031] In the drawings, like reference numerals refer to same or similar elements throughout the several views. The drawings are not necessarily to scale. It should be understood that these drawings are merely schematic and certain

[0032] Figure 1 is a schematic diagram of a program module of a circuit analysis device provided in an embodiment of the present application;

[0033] Figure 2 is a schematic diagram of a circuit analysis flow provided in an embodiment of the present application;

[0034] Figure 3 is a schematic diagram of an implementation flow of a circuit analysis method provided in an embodiment of the present application;

[0035] Figure 4 is a schematic diagram of an implementation flow of a parasitic parameter extraction method provided in a specific example of the present application;

[0036] Figure 5 is a schematic diagram of a hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In the following description, numerous specific details are given to provide a thorough understanding of the application. However, it will be apparent that the application can be practiced without one or more of these specific details. In other instances, well-known techniques have not been described in detail in order to avoid obscuring the application. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known techniques have not been described in detail in order to avoid unnecessarily obscuring the present application.

[0038] In addition, the accompanying drawings are included to provide a thorough understanding of embodiments of the application and are not intended to be in any way limiting of the application. Unless otherwise noted, identical or similar components are identified with the same reference numerals throughout the text. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the application. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views, and similar components of drawings are identified by like reference characters.

[0039] The flow charts shown in the drawings are merely illustrative examples and do not necessarily include all steps. For example, some steps can be further divided, and some steps can be combined or partially combined, so that the actual execution order can be changed according to the actual situation.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] Figure 1 is a schematic diagram of a program module of a circuit analysis device provided in an embodiment of the application. The device comprises:

[0042] An information module 110 is configured to obtain a plurality of layout units.

[0043] An environment configuration module 120 is configured to set a corresponding layout parasitic parameter extraction (LPE) environment for each layout unit based on the type and / or parameters of the layout unit.

[0044] A batch processing module 130 is configured to extract a parasitic netlist of the plurality of layout units in the layout parasitic parameter extraction environment.

[0045] The scheme of the application can provide an environment configuration module to set a corresponding layout parasitic parameter extraction environment for each layout unit based on the type and / or parameters of the layout unit, and then extract a parasitic netlist of the plurality of layout units. In this way, the user does not need to manually perform complex environment setting, and can extract a parasitic netlist of the plurality of layout units in the automatically set layout parasitic parameter extraction environment. This can greatly reduce the time for parasitic parameter extraction, thereby shortening the time required for circuit post-simulation.

[0046] For better understanding of the embodiments of the present application, reference is made to Figure 2 , Figure 2 is a schematic diagram of the circuit analysis process provided in the embodiments of the present application. In Figure 2 , the circuit layout includes a plurality of layout units A, B, C and D, and the circuit schematic diagram includes a plurality of circuit units A', B', C' and D' corresponding to the plurality of layout units. It should be noted that the parasitic parameter netlist is actually flattened, without hierarchical structure, and the unit hierarchy in the figure is only for describing the logical structure. Here, both the circuit units and the layout units are batch acquired by the information module 110.

[0047] In some embodiments, the batch processing module 130 includes an export module 131, which is configured to batch export the GDS files of the layout units in a GDS export environment and batch export the circuit netlists of the circuit units in a netlist export environment. Here, the GDS export environment and the netlist export environment are both set by the environment configuration module 120 based on the types and / or parameters of the layout units. Here, the GDS file is a file in the Graphic Data System (GDS) format.

[0048] In other embodiments, the export module 131 can include a layout export module 1311 and a netlist export module 1312; the layout export module 1311 is configured to batch export the GDS files of the layout units in a GDS export environment, and the netlist export module 1312 is configured to batch export the circuit netlists of the circuit units in a netlist export environment.

[0049] Here, the GDS file of the layout unit represents the designed integrated circuit layout, which contains the physical information of each device or hardware unit of the designed integrated circuit, which can be the shape, area and position information of each device or hardware unit on the chip; the circuit netlist corresponding to the circuit unit represents a text file describing the logical information between the circuit elements, i.e. the connection relationship between the circuit elements, which contains the connection line information between each device unit of the designed integrated circuit.

[0050] In some embodiments, the information module 110 can acquire a plurality of layout units at a time, in other words, the information module 110 can batch acquire the layout units, and then the environment configuration module 120 sets the corresponding layout parasitic parameter extraction environment for each of the plurality of layout units, and the batch processing module 130 simultaneously extracts the parasitic parameter netlist of each of the plurality of layout units in the layout parasitic parameter extraction environment set by the environment configuration module 120.

[0051] In some embodiments, the information module 110 can acquire a plurality of layout units at one time, in other words, the information module 110 can acquire the layout units in batches. Then the environment configuration module 120 sets the corresponding layout parasitic parameter extraction environment for each of the plurality of layout units, and the batch processing module 130 extracts the parasitic parameter netlist of each of the plurality of layout units under the layout parasitic parameter extraction environment set by the environment configuration module 120.

[0052] In some embodiments, the environment configuration module 120 is further configured to set a verification environment, and the batch processing module 130 further includes a verification module 132, which is configured to perform layout versus schematic (LVS) verification based on the GDS file and the circuit netlist under the verification environment.

[0053] Here, the main function of the layout versus schematic verification is to verify whether the circuit structure of the integrated circuit layout is consistent with the circuit schematic, that is, the circuit netlist. The GDS file and the circuit netlist are input into the verification module 132, which verifies the consistency of the circuit structure of the GDS file and the circuit netlist. In this process, the verification module 132 establishes a one-to-one correspondence between the physical information in the GDS file and the logical information in the circuit netlist. After verification, the verification module 132 outputs the verification result and the data file with the one-to-one correspondence between the physical information and the logical information. Here, the layout versus schematic verification result (LVS result) includes the verification result and the data file.

[0054] The verification result in the embodiments of the present application includes verification pass and verification failure. Verification pass means that the circuit structure of the GDS file and the circuit netlist is correct in the LVS verification, and verification failure means that the circuit structure of the GDS file and the circuit netlist is incorrect in the LVS verification. It should be noted that the data file output by the verification module 132 in the embodiments of the present application is a data file obtained in the case of verification pass, and the data file includes the physical information of each device unit and the corresponding connection line information.

[0055] In the embodiments of the present application, the batch processing module 130 includes a parasitic parameter extraction module 133, which is configured to extract the parasitic parameter netlist of each of the plurality of layout units under the layout parasitic parameter extraction environment.

[0056] It should be noted that the parasitic parameter extraction module 133 in the embodiments of the present application extracts the parasitic parameter netlist of the layout unit whose circuit structure is correct in the LVS verification of the GDS file and the netlist based on the verification result and the data file output by the verification module 132.

[0057] In the design flow for fabricating integrated circuits, the physical design of the integrated circuit can describe specific geometric elements, often referred to as a "layout" design. The geometric elements define shapes that will be created in various materials to fabricate the integrated circuit. Typically, groups of geometric elements representing circuit device components, such as contacts, gates, etc., will be selected and placed in a design area. These groups of geometric elements can be custom designed, selected from a previously created library of designs, or some combination of the two. Once the groups of geometric elements representing circuit device components are placed, geometric elements representing connecting lines are then placed between these geometric elements according to a predetermined routing. These connecting lines will form the wiring used to interconnect the electronic devices. Typically, a great deal of analysis is performed on the final layout design of the integrated circuit. For example, the layout design can be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the logic design of the integrated circuit. The layout design can also be analyzed to confirm that it meets various design requirements, such as minimum spacing between geometric elements. Still further, the layout design can be modified to include the use of redundant geometric elements or to add correction features to various geometric elements to offset limitations in the manufacturing process, etc. During the physical design analysis, the layout design can be analyzed to determine the parasitic parameter values, such as parasitic capacitance, parasitic resistance, parasitic inductance, etc., of the networks in the layout design, which can be used to determine whether the layout design includes voltage drops, signal delays, or signal noise.

[0058] Here, according to the data file output by the verification module 132, the parasitic parameter extraction is performed, and then the parasitic parameter netlist corresponding to the integrated circuit of the design is obtained, which contains a plurality of parasitic parameter information. The plurality of parasitic parameter information can include parasitic parameter information corresponding to each device unit and / or parasitic parameter information of each connecting line (wire). The parasitic parameter information corresponding to each device unit or wire can be one or more. The parasitic parameter information contains the attribute of the parasitic parameter (such as parasitic resistance, parasitic capacitance, or parasitic inductance) and the parasitic parameter value (such as parasitic resistance value, parasitic capacitance value, and parasitic inductance value). In the parasitic parameter netlist, each device unit or line is associated with the attribute of the corresponding parasitic parameter and the parasitic parameter value. Here, the parasitic parameter can be a parasitic parameter in a standard parasitic file (SPF) format.

[0059] In some embodiments, the environment configuration module 120 communicates with at least one electronic design automation (EDA) software, and the environment configuration module 120 automatically configures the GDS export environment, the netlist export environment, the verification environment, and the layout parasitic parameter extraction environment by calling the interface of the EDA software.

[0060] In some embodiments, the environment configuration module 120 is in communication with a plurality of EDA software of different types, and the environment configuration module 120 automatically configures GDS export environment, netlist export environment, verification environment and layout parasitic parameter extraction environment of different types by calling interfaces of different EDA software.

[0061] Here, electronic design automation means using computers to design and simulate the performance of electronic circuits on integrated circuits, and EDA can be used to handle demanding complex semiconductor integrated circuit design work. In integrated circuit design, the connection relationship between each component of the circuit can be detected by EDA, so as to test and verify whether the integrated circuit works correctly.

[0062] The environment configuration module in the embodiments of the present application can automatically configure the environment (including GDS export environment, netlist export environment, verification environment and layout parasitic parameter extraction environment) in the parasitic parameter extraction process based on the type and / or parameters of the layout unit, without manual configuration by the user.

[0063] In some embodiments, the circuit analysis device further comprises a result output module 140 for generating a report corresponding to the layout unit according to the LVS result and the parasitic parameter netlist. The report extracts the batch processing result of all layout units, including the error type, number and parasitic parameter netlist of verification failure, and presents it to the user in a visual manner.

[0064] Reference Figure 2 After the circuit analysis device provided in the embodiments of the present application performs batch processing on a plurality of layout units, the LVS verification of layout units A, C and D passes, while the LVS verification of layout unit B fails. The parasitic parameters of layout units A, C and D that pass the LVS verification are extracted to obtain the parasitic parameter netlist of layout units A, C and D. Finally, a report corresponding to the layout unit is generated according to the LVS result and the parasitic parameter netlist. It should be noted that for the layout unit that fails the verification, the layout engineer needs to correct the layout unit.

[0065] In some embodiments, the circuit analysis device further comprises a simulation module 150 for performing post-simulation according to the parasitic parameter netlist.

[0066] Here, post-simulation refers to simulating the parasitic parameters in the parasitic parameter netlist, such as parasitic resistance, parasitic capacitance or parasitic inductance, into the extracted circuit netlist, analyzing the integrated circuit, and ensuring that the integrated circuit meets the design requirements.

[0067] In some embodiments, the information module 110 has a graphical user interface (GUI) for obtaining the layout units. After a user inputs the specified information through the graphical user interface, the circuit analysis device can quickly and batch extract the parasitic parameters of the plurality of layout units included in the specified information, obtain a parasitic parameter netlist, and perform batch post-simulation according to the parasitic parameter netlist.

[0068] The scheme of the present application can provide an environment configuration module to set a corresponding layout parasitic parameter extraction environment for each layout unit based on the type and / or parameters of the layout unit, and then batch extract the parasitic netlist of the plurality of layout units. In this way, the user does not need to manually perform complex environment setting, and can also batch extract the parasitic netlist of the plurality of layout units in an automatically set environment. This can greatly reduce the time for extracting parasitic parameters, thereby shortening the time required for circuit post-simulation.

[0069] The example scheme or technology of the present application can be applied to the integrated circuit layout of a memory. The memory can be a volatile memory, such as a dynamic random access memory (DRAM). The memory can also be a non-volatile memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a resistive random access memory (RRAM), a ferroelectric random access memory (FRAM), etc.

[0070] Based on the above circuit analysis device, the embodiment of the present application further provides a circuit analysis method, Figure 3 is a flowchart of an implementation process of a circuit analysis method provided by the embodiment of the present application, as Figure 3 shown, the circuit analysis method includes the following steps:

[0071] Step 310: Obtain a plurality of layout units;

[0072] Step 320: Set a corresponding layout parasitic parameter extraction environment for each layout unit based on the type and / or parameters of the layout unit;

[0073] Step 330: Batch extract the parasitic parameter netlist of the plurality of layout units in the layout parasitic parameter extraction environment.

[0074] In some embodiments, setting a corresponding layout parasitic parameter extraction environment for each layout unit based on the type and / or parameters of the layout unit includes: automatically configuring the layout parasitic parameter extraction environment by calling the interface of the EDA software.

[0075] In some embodiments, the layout parasitic parameter extraction environment corresponding to each layout unit is set based on the type and / or parameters of the layout unit, including automatically configuring the layout parasitic parameter extraction environment of different types by calling the interface of different EDA software.

[0076] In some embodiments, before the parasitic parameter netlist of the plurality of layout units is extracted in the layout parasitic parameter extraction environment, the circuit analysis method further includes:

[0077] The GDS export environment is set, and the GDS file of the layout unit is exported in the GDS export environment.

[0078] In some embodiments, the layout parasitic parameter extraction environment corresponding to each layout unit is set based on the type and / or parameters of the layout unit, including setting the netlist export environment.

[0079] The plurality of layout units are obtained, including obtaining the circuit unit corresponding to the layout unit.

[0080] The method further includes: exporting the circuit netlist of the circuit unit in the netlist export environment.

[0081] In some embodiments, the layout parasitic parameter extraction environment corresponding to each layout unit is set based on the type and / or parameters of the layout unit, including setting the verification environment.

[0082] The circuit analysis method further includes: based on the GDS file and the circuit netlist, performing layout versus circuit verification in the verification environment.

[0083] In some embodiments, the circuit analysis method further includes: generating a report of the corresponding layout unit according to the verification result of the layout versus circuit verification and the parasitic parameter netlist.

[0084] In some embodiments, the circuit analysis method further includes: a simulation module for post-simulation according to the parasitic parameter netlist.

[0085] Regarding the circuit analysis method in the above embodiments, the specific steps of performing operations in each step have been described in detail in the embodiments related to the circuit analysis device, and will not be described in detail here.

[0086] Figure 4 is a flowchart of an implementation of a parasitic parameter extraction method provided by a specific example of the present application, as shown in Figure 4 The method includes the following steps:

[0087] Step 410: obtaining the specified information input by the user from the graphical interactive interface;

[0088] In the embodiments of the present application, the specified information includes a layout unit list, a layout library, and a circuit library, etc. The layout unit list includes information of a plurality of layout units. After the layout unit list is obtained from the graphical interactive interface, the corresponding layout units are obtained from the layout library based on the information (e.g. ID) of each layout unit in the layout unit list, and the plurality of circuit units corresponding to the plurality of layout units are obtained from the circuit library.

[0089] Step 420: setting a GDS export environment, and batch exporting GDS files of the layout units under the GDS export environment;

[0090] In the embodiments of the present application, the plurality of layout units in the layout unit list can be processed one by one, or can be processed in batches, or can be processed simultaneously in batches.

[0091] Here, the GDS file of the layout unit represents a designed integrated circuit layout, which includes physical information of each device or hardware unit of the designed integrated circuit, and the physical information can be shape, area, and position information of each device or hardware unit on a chip.

[0092] Step 430: setting a netlist export environment, and batch exporting circuit netlists of the circuit units under the netlist export environment;

[0093] Step 440: judging whether the GDS file and the circuit netlist are successfully exported or not;

[0094] Here, the circuit netlist corresponding to the circuit unit represents a text file describing logical information between circuit elements, i.e. connection relationship between the circuit elements, which includes connection line information between each device unit of the designed integrated circuit.

[0095] In the embodiments of the present application, if the judgment result is that the GDS file and the circuit netlist are successfully exported, step 450 is executed; if the judgment result is that the GDS file and the circuit netlist are not successfully exported, step 480 is executed.

[0096] Step 450: setting a verification environment, and performing LVS verification based on the GDS file and the circuit netlist under the verification environment;

[0097] Step 460: judging whether the LVS verification is passed or not;

[0098] Here, the main role of LVS verification is to verify whether the integrated circuit layout and the circuit structure of the circuit netlist are consistent, to verify the consistency of the obtained GDS file and the circuit structure of the circuit netlist, and to establish a one-to-one correspondence between the physical information in the GDS file and the logical information in the circuit netlist in the process. After verification, the verification result and the data file with one-to-one correspondence between the physical information and the logical information are output. Here, the layout versus circuit verification result (LVS result) includes the verification result and the data file.

[0099] The verification result in the embodiment of the application includes verification pass and verification failure; the verification pass indicates that the GDS file and the circuit structure of the circuit netlist are correct in the LVS verification, and the verification failure indicates that the GDS file and the circuit structure of the circuit netlist are incorrect in the LVS verification.

[0100] In the embodiment of the application, if the judgment result is LVS verification pass, step 470 is performed; if the judgment result is LVS verification failure, step 480 is performed.

[0101] Step 470: Set up a layout parasitic parameter extraction environment, and extract the parasitic parameter netlist of the layout unit in the layout parasitic parameter extraction environment; here, the parasitic parameter extraction is performed on the layout unit, and then the parasitic parameter netlist corresponding to the designed integrated circuit is obtained. The parasitic parameter netlist contains a plurality of parasitic parameter information, wherein the plurality of parasitic parameter information can include the parasitic parameter information corresponding to each device unit and / or the parasitic parameter information of each connection line (wire). The parasitic parameter information corresponding to each device unit or wire can be one or more. The parasitic parameter information contains the attribute of the parasitic parameter (such as parasitic resistance or parasitic capacitance), and also contains the parasitic parameter value, such as (parasitic resistance value and parasitic capacitance value). In the parasitic parameter netlist, each device unit or line is associated with the attribute of the corresponding parasitic parameter and the parasitic parameter value.

[0102] Step 480: Determine whether all layout units in the layout unit list are processed.

[0103] In the embodiment of the application, if the judgment result is that all layout units in the layout unit list are processed, step 490 is performed; if the judgment result is that all layout units in the layout unit list are not processed, step 420 is performed to continue processing the layout units in the layout unit list which are not processed.

[0104] Step 490: Generate a report corresponding to the layout unit according to the LVS result and the parasitic parameter netlist.

[0105] In the embodiment of the present application, the report extracts the batch processing results of all layout units, including error types of verification failure, number and parasitic parameter netlist, and presents them to the user in a visual manner.

[0106] As to the parasitic parameter extraction method in the above embodiment, the specific steps of performing operations in each step have been described in detail in the embodiment of the circuit analysis device, and will not be described in detail here.

[0107] The parasitic parameter extraction method provided in the embodiment of the present application can extract parasitic parameters of multiple layout units in batches, and can also set the corresponding environment in each process (GDS export, netlist export, LVS verification and layout parasitic parameter extraction) based on the type and / or parameters of the layout unit, without manual setting by the user.

[0108] Each module in the above circuit analysis device can be realized by software, hardware and combinations thereof, in whole or in part. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the above modules.

[0109] In order to better understand the embodiments of the present application, refer to Figure 5 , Figure 5 is a hardware structure schematic diagram of an electronic device provided by the embodiment of the present application. As shown in Figure 5 , the electronic device of the embodiment of the present application includes a memory for storing a computer program, and a processor for executing the computer program in the memory to realize each step in the circuit analysis method described in the above embodiment. For details, refer to the related description in the foregoing method embodiment, which will not be described here.

[0110] Optionally, the memory can be independent or integrated with the processor. When the memory is independently arranged, the device further includes a bus for connecting the memory and the processor.

[0111] Based on the content described in the above embodiment, the embodiment of the present application further provides a computer readable storage medium, which stores computer execution instructions. When the processor executes the computer execution instructions, each step in the circuit analysis method described in the above embodiment is realized. For details, refer to the related description in the foregoing circuit analysis method embodiment, which will not be described here.

[0112] It can be understood that the same or similar parts in the above embodiments can be mutually referred to, and the content not described in detail in some embodiments can refer to the same or similar content in other embodiments.

[0113] It should be noted that, in the description of the present application, the terms "first", "second" and the like are used only for descriptive purposes, and cannot be construed as indicating or implying relative importance. In addition, in the description of the present application, the meaning of "a plurality of" is at least two, unless otherwise specified.

[0114] Any process or method descriptions in flow charts or described elsewhere herein can be understood as representing code modules, segments, or portions of code that include one or more executable instructions for implementing specific logic functions (or steps) in the process, and that the various embodiments of the application can include additional or fewer steps performing the same or equivalent functions as those described, in the same or a different order, in combination with each other, in place of each other, or in an additional manner. It will be appreciated that the scope of the application encompasses not only the described embodiments, but also the subject matter of the described embodiments.

[0115] It should be understood that each of the parts of the present application can be realized by hardware, software, firmware or a combination thereof. In the above-described embodiments, a plurality of steps or methods can be realized by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if realized by hardware, and as in another embodiment, it can be realized by any one or a combination of the following technologies known in the art: discrete logic circuit with logic gate circuit for implementing logic functions on data signals, application specific integrated circuit with suitable combination logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) and the like.

[0116] Those skilled in the art of the present technology can understand that all or part of the steps carried out by the above-mentioned embodiment method can be completed by a program instructing the relevant hardware, and the program can be stored in a computer readable storage medium, which includes one or a combination of the steps of the method embodiments when executed.

[0117] In addition, each functional unit in each embodiment of the present application can be integrated in one processing module, or each unit can be physically present separately, or two or more units can be integrated in one module. The above-mentioned integrated module can be realized in the form of hardware or in the form of software functional module. The integrated module, if realized in the form of software functional module and sold or used as an independent product, can also be stored in a computer readable storage medium.

[0118] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0119] In the description of the application, reference to terms such as "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. is not necessarily a reference to the same embodiment or example. Furthermore, description of features or aspects within such examples or embodiments that are described as being optional is not meant to exclude from the scope of the application other embodiments or examples that do not include such features or aspects. Thus, the scope of the application should be determined by the appended claims and their legal equivalents rather than by the description of the application.

[0120] The above description is only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A circuit analysis device, characterized by comprising: The device comprises: an information module configured to acquire a plurality of layout units; an environment configuration module configured to set a corresponding layout parasitic parameter extraction environment based on the type and / or parameters of the layout units; a batch processing module configured to extract a parasitic parameter netlist of the plurality of layout units in the layout parasitic parameter extraction environment; the environment configuration module is in communication with a plurality of EDA software of different types, and the environment configuration module automatically configures the layout parasitic parameter extraction environment of different types by calling the interfaces of different EDA software.

2. The apparatus of claim 1, wherein, The environment configuration module is further configured to set a GDS export environment, and the batch processing module comprises an export module configured to export GDS files of the layout units in the GDS export environment.

3. The apparatus of claim 2, wherein, The information module is further configured to acquire a corresponding circuit unit of the layout units, and the environment configuration module is further configured to set a netlist export environment, and the export module is further configured to export a circuit netlist of the circuit units in the netlist export environment.

4. The apparatus of claim 3, wherein, The environment configuration module is further configured to set a verification environment, and the batch processing module further comprises a verification module configured to perform layout versus circuit verification based on the GDS files and the circuit netlist in the verification environment.

5. The apparatus of claim 4, wherein, The device further comprises a result output module configured to generate a report corresponding to the layout units according to the verification result of the layout versus circuit verification and the parasitic parameter netlist.

6. The apparatus of claim 1, wherein, The information module has a graphical interactive interface configured to acquire the layout units.

7. The apparatus of claim 1, wherein, The device further comprises: a simulation module configured to perform post-simulation based on the parasitic parameter netlist output by the batch processing module.

8. A circuit analysis method characterized by, The method comprises: acquiring a plurality of layout units; setting a corresponding layout parasitic parameter extraction environment based on the type and / or parameters of the layout units; extracting a parasitic parameter netlist of the plurality of layout units in the layout parasitic parameter extraction environment; the setting of the corresponding layout parasitic parameter extraction environment based on the type and / or parameters of the layout units comprises automatically configuring the layout parasitic parameter extraction environment of different types by calling the interfaces of different EDA software.

9. The method of claim 8, wherein, Before the extracting of the parasitic parameter netlist of the plurality of layout units in the environment, the method further comprises: setting a GDS export environment and exporting GDS files of the layout units in the GDS export environment.

10. The method of claim 9, wherein, the setting of the corresponding layout parasitic parameter extraction environment based on the type and / or parameters of the layout units comprises setting a netlist export environment; the acquiring of the plurality of layout units comprises acquiring a corresponding circuit unit of the layout units; the method further comprises exporting a circuit netlist of the circuit units in the netlist export environment.

11. The method of claim 10, wherein, the setting of the corresponding layout parasitic parameter extraction environment based on the type and / or parameters of the layout units further comprises: setting a verification environment; the method further comprises performing layout versus circuit verification based on the GDS files and the circuit netlist in the verification environment.

12. The method of claim 11, wherein, The method further comprises: According to the verification result of the layout comparison circuit verification and the parasitic parameter netlist, a report corresponding to the layout unit is generated.

13. The method of claim 8, wherein, The method further comprises: According to the parasitic parameter netlist, post-simulation is performed.

14. An electronic device, comprising: Comprise: A memory for storing a computer program; A processor for executing the computer program in the memory to implement the operation steps of the method in any one of claims 8 to 13.

15. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the operation steps of the method in any one of claims 8 to 13.

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