Semiconductor devices and their fabrication methods

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes a substrate, multiple active regions, shallow trench isolation, and multiple buried gates. The active regions are disposed on the surface of the substrate, each containing a semiconductor layer, with a first interface between the semiconductor layer and the substrate. The shallow trench isolation is disposed on the substrate and surrounds the active regions. The buried gates are buried within the active regions and positioned above the first interface. Therefore, this invention improves the isolation effect between active regions while maintaining a certain level of integration, mitigating device defects that may arise from increased integration levels.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing the same, and more specifically, to a semiconductor device comprising an active region isolated from a shallow trench and a method for manufacturing the same. Background Technology

[0002] With the miniaturization of semiconductor devices and the increasing complexity of integrated circuits, the size of components continues to shrink, and their structures are constantly changing. Therefore, maintaining the performance of small-sized semiconductor components is currently the industry's primary goal. In semiconductor manufacturing processes, multiple active areas (AAs) are typically defined on a substrate as a basis, and the desired components are then formed on these active areas. Generally, active areas are multiple patterns formed on the substrate using processes such as photolithography and etching. However, with the demands of size reduction, the width of active areas is gradually decreasing, and the spacing between each active area is also gradually shrinking. This presents many limitations and challenges to the manufacturing process, making it impossible to meet product requirements. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method. The method utilizes a mask layer to define the contours of active regions, resulting in each active region having a cross-sectional contour that is wider at the top and narrower at the bottom. Shallow trench isolation between the active regions forms a cross-sectional contour that is narrower at the top and wider at the bottom. In this way, the semiconductor device maintains a certain level of integration, while the shallow trench isolation effectively isolates adjacent active regions, providing optimized insulation.

[0004] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a substrate, a plurality of active regions, a shallow trench isolation, and a plurality of buried gates. The active regions are disposed on the surface of the substrate, wherein each active region includes a semiconductor layer, and the semiconductor layer has a first interface with the substrate. The shallow trench isolation is disposed on the substrate and surrounds the active regions. The buried gates are buried within the active regions and located above the first interface.

[0005] To achieve the above objectives, one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: A substrate is provided, the substrate having a surface, and a plurality of active regions are formed on the surface of the substrate, wherein each active region includes a semiconductor layer, and the semiconductor layer has a first interface with the substrate. Shallow trench isolation is formed on the substrate, surrounding the active regions. A plurality of buried gates are formed within the active regions, the buried gates being located above the first interface. Attached Figure Description

[0006] The accompanying drawings are provided to give a more in-depth understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0007] Figures 1 to 2 The diagram shown is a schematic diagram of a semiconductor device according to a first embodiment of the present invention, wherein:

[0008] Figure 1 A top view schematic diagram of a semiconductor device; and

[0009] Figure 2 for Figure 1 A cross-sectional view along tangents A-A' and B-B'.

[0010] Figures 3 to 11 A schematic diagram illustrating the fabrication process of the semiconductor memory device according to the second embodiment of the present invention is shown; wherein:

[0011] Figure 3 This is a top view of a semiconductor device after the mask layer has been formed.

[0012] Figure 4 for Figure 3 A cross-sectional view along tangents A-A' and B-B';

[0013] Figure 5 This is a schematic cross-sectional view of a semiconductor device after the deposition fabrication process.

[0014] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device after another deposition fabrication process.

[0015] Figure 7 This is a schematic cross-sectional view of a semiconductor device after the semiconductor layer has been formed.

[0016] Figure 8 This is a top view of a semiconductor device after the mask layer has been removed.

[0017] Figure 9 for Figure 8 A cross-sectional view along tangents A-A' and B-B';

[0018] Figure 10 This is a top view of a semiconductor device after the cutting and fabrication process; and

[0019] Figure 11 for Figure 10 A cross-sectional view along tangents A-A' and B-B'.

[0020] Figure 12 The diagram shown is a cross-sectional schematic of a semiconductor device according to a preferred embodiment of the present invention.

[0021] Figure 13 The diagram shown is a cross-sectional schematic of a semiconductor device according to another preferred embodiment of the present invention.

[0022] The reference numerals in the attached figures are explained as follows:

[0023] 10, 20, 30, 40 semiconductor devices

[0024] 100, 200 substrates

[0025] 102, 104, 204 ditches

[0026] 110 Shallow ditch isolation

[0027] 130 Active Zone

[0028] 202 surface

[0029] 210 Active Fragment

[0030] 210a, 310 active regions

[0031] Side walls 211, 213, 311, 313

[0032] 212 First Semiconductor Sublayer

[0033] 212a First Interface

[0034] 214 Second Semiconductor Sublayer

[0035] 214a Second Interface

[0036] 220 mask layers

[0037] 222 Opening

[0038] 230, 230a, 330 Shallow Ditch Isolation

[0039] 232, 232a Insulation Layer

[0040] 234, 234a Insulation Layer

[0041] 240 Embedded Gate

[0042] 242 Dielectric layer

[0043] 244 Gate Dielectric Layer

[0044] 246 gate

[0045] 248 cap layer

[0046] 260 gate wire

[0047] 262 Semiconductor material layer

[0048] 264 Barrier Layer

[0049] 266 conductive layer

[0050] 268 cap layer

[0051] 270 spacer wall

[0052] 280 Insulation Structure

[0053] 290 plugs

[0054] D1 First Direction

[0055] D2 Second Direction

[0056] L21, L22 length

[0057] Lengths of S1 and S2

[0058] W11 First Distance

[0059] W12 Second Distance

[0060] W21, W22 Length

[0061] Angle between θ1 and θ2 Detailed Implementation

[0062] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0063] Please refer to the following: Figures 1 to 2 The illustration shown is a schematic diagram of the semiconductor device 10 in the first embodiment of the present invention. First, as Figures 1 to 2 As shown, the semiconductor device 10 includes, for example, a substrate 100, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe) or a silicon-on-insulator (SOI) substrate, etc. At least one shallow trench isolation (STI) 110 is formed in the substrate 100 to define a plurality of active areas (AAs) 130 in the substrate 100.

[0064] In one embodiment, the active regions 130 are fabricated, for example, by patterning the substrate 100. For instance, a mask layer (not shown) is first formed on the substrate 100, exposing a portion of the substrate 100. The mask layer includes multiple patterns (not shown) that can be used to define the active regions 130. An etching process is then performed using the mask layer to remove a portion of the substrate 100 to form at least one trench 102, 104. A deposition process is then performed to form an insulating layer (not shown), such as silicon oxide, silicon nitride, or silicon oxynitride, within the trenches 102, 104. A shallow trench isolation 110, with its top surface lower than the surface of the substrate 100, is then formed through an etch-back process, simultaneously defining the active regions 130. Thus, the shallow trench isolation 110 can surround the active regions 130, and the portion of the active regions 130 protruding from the surface of the shallow trench isolation 110 is a fin. However, in another embodiment, a shallow trench isolation (not shown) with its top surface flush with the surface of the substrate 100 can also be formed through an etch-back process, making the defined active region 130 a planar active region (planar AAs, not shown). Furthermore, the specific fabrication process of the active region 130 is not limited to the aforementioned processes. In another embodiment, a mask layer defining the active region 130 can also be fabricated using a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but is not limited thereto.

[0065] In one embodiment, the active regions 130 extend parallel to each other and spaced apart from each other along a first direction D1, and have the same length S1, wherein the first direction D1 is preferably not parallel to either the x-direction or the y-direction, such as... Figure 1 As shown. Furthermore, each active region 130 is arranged sequentially in multiple columns along the first direction D1, such that adjacent active regions 130 are staggered relative to each other in the second direction D2 perpendicular to the first direction D1, thus presenting a specific arrangement, as shown. Figure 1 The array arrangement shown is an example, but not limited to it. In this embodiment, adjacent active regions 130 are separated by shallow trench isolation 110 in the second direction D2 by a first distance W11 and a second distance W12. The second distance W12 has a relatively large distance because it is located at the adjacent position at the ends of each active region 130, for example, about 2 to 2.5 times the first distance W11, but is not limited thereto.

[0066] Thus, the semiconductor device 10 of the first embodiment of the present invention is completed. Subsequently, the semiconductor device 10 can continue to be used to form other active semiconductor components to further improve the performance of the subsequently formed devices. For example, in subsequent fabrication processes, transistor components (not shown) can continue to be formed on the active region 130 of the semiconductor device 10 to serve as fin field-effect transistors (not shown); or, transistor components (not shown) and memory components (not shown) can continue to be formed in and on the active region 130 of the semiconductor device 10, respectively, to serve as the smallest unit (memory cell) of a dynamic random access memory (DRAM) device and to receive voltage information from bit lines (not shown) and word lines (not shown).

[0067] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and its fabrication method of this invention may have other forms or be achieved by other means, and are not limited to the foregoing. For example, in another embodiment, the active regions of the semiconductor device can further improve the isolation effect between active regions while maintaining a certain level of integration, thereby improving device defects (such as component short circuits, misalignments, or leakage currents) that may arise from increased integration levels. Other embodiments or variations of the semiconductor device and its fabrication method of this invention will be further described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0068] Please refer to the following: Figures 3 to 11 The illustration shown is a schematic diagram of the semiconductor device 20 in the second embodiment of the present invention. First, as Figures 3 to 4 As shown, a semiconductor device 20 includes, for example, a substrate 200, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate, etc. A mask layer 220 is formed on the substrate 200, exposing a portion of the surface 202 of the substrate 200. The mask layer 220 includes a plurality of openings 222, for example, extending parallel to each other and spaced apart along a first direction D1, wherein the first direction D1 is preferably any direction that is not parallel to the x-direction or the y-direction, such as... Figure 3 As shown.

[0069] In one embodiment, reference Figure 3 and Figure 4As shown, the mask layer 220 is fabricated, for example, using a patterning process. For instance, a mask material layer (not shown) and a photoresist layer (not shown) completely covering the surface 202 of the substrate 200 are first formed on the substrate 200. An etching process is then performed on the photoresist layer to transfer the pattern of the photoresist layer onto the mask material layer, forming the mask layer 220. It should be noted that because the mask layer 220 has a certain thickness T1 in the direction perpendicular to the substrate 200 (not shown), for example, approximately 30 to 40 nanometers (nm), the cross-sections of each opening 222 of the mask layer 220 in the first direction D1 or the second direction D2 all exhibit a profile that is wider at the top and narrower at the bottom. Figure 4 As shown. In one embodiment, the top of the opening 222 in the cross-section in the second direction D2 has a relatively large aperture, with a length L21 of, for example, about 20 to 30 nanometers, while the bottom of the cross-section has a relatively small aperture, with a length L22 of, for example, about 10 to 20 nanometers, preferably about 0.5 to 0.75 times the length L21, but not limited thereto. In this case, the cross-section of the mask layer 220 in the second direction D2 exhibits an opposite profile, narrower at the top and wider at the bottom, as shown. Figure 4 As shown, the top of the cross-section has a relatively small length W21, while the bottom of the cross-section has a relatively large length W22, preferably about 1.5 to 2 times the length W21, but not limited thereto.

[0070] like Figure 5 As shown, a first deposition process is performed on substrate 200 to form a first semiconductor sublayer 212 within each opening 222, such that the first semiconductor sublayer 212 fills but does not completely fill each opening 222. The first deposition process is preferably a selective epitaxial growth (SEG) process, but is not limited thereto. Specifically, the first semiconductor sublayer 212, for example, is formed along... <110> Crystalline surface or <111> Growth occurs along the crystal plane, preferably along the plane of growth. Figure 4 The surfaces 202 shown are oriented at an angle of approximately 50 to 72 degrees, more preferably 53 degrees, such that the cross-section of the first semiconductor sublayer 212 presents as follows: Figure 5 The hexagonal (also known as SigmaΣ), arc-shaped (not shown), or octagonal (not shown) cross-sectional shapes shown are not limited thereto. However, in another embodiment, the first deposition process may also be a low-temperature deposition process, rapidly forming a material layer (not shown) including amorphous or polycrystalline material within each opening 222, followed by a heat treatment process to modify the material layer into a first semiconductor sublayer 212 including monocrystalline material using high temperature.

[0071] The first semiconductor sublayer 212 can include different materials depending on the actual device requirements. For example, when the substrate 200 includes a single-crystal silicon substrate or other materials, it can be made of different materials. <100> When considering the material of the crystalline surface, the first semiconductor sublayer 212 can be selected from germanium, germanium silicide (SiGe), or other materials with... <110> Crystalline surface or <111> The material of the crystal surface, etc., but not limited to this. Under this setting, due to the influence of similar materials and lattice differences, a first interface 212a can be formed between the first semiconductor sublayer 212 and the substrate 200, such as... Figure 5 As shown. Furthermore, in another embodiment, the first deposition process can be formed in a single-layer or multi-layer manner, allowing the concentration of heteroatoms (such as germanium atoms) within the first semiconductor sublayer 212 to change gradually. Alternatively, an in-situ doping process can be performed simultaneously with the first deposition process, resulting in a gradual concentration of heteroatoms (such as germanium atoms) within the first semiconductor sublayer 212. Generally, it is preferable that the surface of the first semiconductor sublayer 212 has a relatively low concentration of germanium atoms, but this is not a limitation.

[0072] like Figure 6 As shown, a second deposition process is performed on the first semiconductor sublayer 212 to form a second semiconductor sublayer 214 within each opening 222 and fill it as shown. Figure 5 The remaining portion of the opening 222 shown. The second deposition process is preferably a selective epitaxial growth process, but is not limited thereto. Specifically, the second semiconductor sublayer 214, for example, also along... <110> Crystalline surface or <111> The crystal plane is grown, preferably along a direction with an angle of about 50 to 72 degrees, more preferably 53 degrees, so that the cross-section of the second semiconductor sublayer 214 presents as follows: Figure 6 The hexagon shown is not a limitation. In other embodiments, the second semiconductor sublayer 214 may also have other cross-sectional shapes, such as arcuate or octagonal, depending on the actual device requirements. Furthermore, in another embodiment, the second deposition process may also be a low-temperature deposition process, with each opening 222 (refer to...) Figure 5 Another material layer (not shown) including amorphous or polycrystalline material is rapidly formed within the substrate, and then a heat treatment process is performed to modify the other material layer into a second semiconductor sublayer 214 including monocrystalline material using high temperature.

[0073] In this embodiment, the second semiconductor sublayer 214 may also include different materials depending on the actual device requirements, such as germanium, germanium silicide (SiGe), or other materials with specific properties. <110> Crystalline surface or <111> The material of the crystal surface, etc., and the second semiconductor sublayer 214 preferably includes a material with a larger lattice than the first semiconductor sublayer 212. For example, if the first semiconductor sublayer 212 includes single-crystal germanium with a smaller lattice, the second semiconductor sublayer 214 may include germanium silicide, germanium boron silicide (SiGeB), etc., with a larger lattice, but is not limited thereto. In this configuration, due to the similarity of materials and the difference in lattice, a second interface 214a can be formed between the second semiconductor sublayer 214 and the first semiconductor sublayer 212, and the cross-sectional profile of the second interface 214a, for example, has the following characteristics: Figure 6 The hexagonal or arc-shaped shape shown is not a limitation. Furthermore, the second deposition process can also be formed in a single-layer or multi-layer manner, allowing the heteroatoms (such as germanium atoms) within the second semiconductor sublayer 214 to change in a gradual manner, or an in-situ doping process can be performed simultaneously with the second deposition process, resulting in a gradual concentration of heteroatoms (such as germanium atoms) within the second semiconductor sublayer 214. Generally, it is preferable that the surface of the second semiconductor sublayer 214 has a relatively light concentration of germanium atoms or no germanium atoms, but this is not a limitation. In one embodiment, the second semiconductor sublayer 214 and the first semiconductor sublayer 212 may also be selected to include the same material (such as germanium silicide), wherein the concentration of heteroatoms (such as germanium atoms) in the first semiconductor sublayer 212 is greater than the concentration of heteroatoms in the second semiconductor sublayer 214.

[0074] like Figure 7 As shown, a planarization process is performed, removing layers exceeding 220 (reference) of the mask layer. Figure 6 The second semiconductor sublayer 214 on the surface of the substrate 200, such that the first semiconductor sublayer 212 and the second semiconductor sublayer 214, which are sequentially stacked on the substrate 200, together form a semiconductor layer, thereby forming each opening 222 (see reference). Figure 4 The semiconductor layer within the semiconductor layer forms the semiconductor device 20 (reference). Figure 3 Multiple active segments 210. It should be noted that each active segment 210 includes a composite material (a first semiconductor sublayer 212 and a second semiconductor sublayer 214), which has a different material and lattice size than the substrate 200, so that there is a first interface 212a between the semiconductor layer and the substrate 200, and there is also a second interface 214a in the semiconductor layer, which is located between the first semiconductor sublayer 212 and the second semiconductor sublayer 214.

[0075] It should be noted that, in this embodiment, the contour of each active segment 210 is defined by each opening 222, and therefore the cross-section in the first direction D1 or the second direction D2 has a contour that is wider at the top and narrower at the bottom, such as... Figure 7 As shown. In one embodiment, reference is made to... Figure 7 The active segment 210 has a relatively large length L21 at the top of the cross section in the second direction D2, for example, about 20 to 30 nanometers, while the active segment 210 has a relatively small length L22 at the bottom of the cross section in the second direction D2, for example, about 10 to 20 nanometers, which is about 0.5 to 0.75 times the length L21, but not limited thereto.

[0076] like Figures 8 to 9 As shown, remove mask layer 220 (reference). Figure 7 This is to form a trench 204 between the active segments 210. In this embodiment, the contour of the trench 204 is determined by, as shown in the figure below. Figure 7 The mask layer 220 is defined such that the cross-section of the trench 204 in the second direction D2 has a profile that is narrower at the top and wider at the bottom, as shown. Figure 9 As shown. In one embodiment, reference is made to... Figure 9 The top of the trench 204 in the second direction D2 has a relatively small aperture, approximately W21 in length, while the bottom of the trench 204 in the second direction D2 has a relatively large aperture, approximately W22 in length, which is about 1.5 to 2 times the aperture W21, but not limited thereto. Then, a deposition process and an etch-back process are sequentially performed to form an insulating layer 232 between each active segment 210, with its top surface lower than the top surface of the active segment 210. This insulating layer may include, for example, silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. In another embodiment, an insulating layer (not shown) with its top surface flush with the top surface of the active segment 210 may also be formed. With this configuration, each active segment 210 in the second direction D2 can achieve optimized insulation by utilizing the insulating layer 232, which has a narrow top and wide bottom cross-sectional profile. Simultaneously, the cross-sectional profile of each active segment 210 in the second direction D2, which is wider at the top and narrower at the bottom, can maintain a certain level of integration.

[0077] like Figures 10 to 11 As shown, a fin-cut fabrication process is performed to remove unnecessary portions of the active segment 210, forming multiple active regions 210a. Each active region 210a extends parallel to and spaced apart from each other along the first direction D1 and has the same length S2. The portion of each active region 210a protruding from the surface of the insulating layer 232 is a fin. It should be noted that the sidewalls of the active regions 210a in the first direction D1 or the second direction D2 are respectively composed of... Figure 7 The mask layer 220 shown is defined, or formed by an etching process during the cutting fabrication process, and therefore has different slopes. Specifically, each active region 210a has two opposing sidewalls 211, 213 with different inclinations in its cross-section in the first direction D1, wherein the sidewall 211 is formed by the mask layer 220 (see reference) in two deposition processes. Figure 7 The profile of the sidewall 211 is defined such that the included angle θ1 between the sidewall 211 and the surface 202 of the substrate 200 is influenced by the growth directions of the first semiconductor sublayer 212 and the second semiconductor sublayer 214, and has an angle of approximately 50 to 72 degrees, preferably 53 degrees, but not limited thereto. The sidewall 213 is formed by etching during the cutting process, and thus has a relatively straight profile. The included angle θ2 between the sidewall 213 and the surface 202 of the substrate 200 is significantly larger than the included angle θ1, for example, an angle of approximately 60 to 80 degrees, but not limited thereto.

[0078] After that, and so on Figures 10 to 11 As shown, another deposition process and an etch-back process are performed sequentially to remove part of the active fragment 210 (refer to...). Figure 8 An insulating layer 234 is re-formed at a position where its top surface is lower than the top surface of the active region 210a. This insulating layer may be made of the same or different material as the insulating layer 232, such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. Thus, the insulating layers 232 and 234 together form the shallow trench isolation 230 of the semiconductor device 20, surrounding each active region 210a. In other words, the shallow trench isolation 230 of the semiconductor device 20 may also include composite materials (insulating layers 232 and 234). A portion of the shallow trench isolation 230 (i.e., insulating layer 232) is formed before the dicing process and is positioned in the second direction D2 between adjacent active regions 210a, surrounding most of the active regions 210a. Another portion (i.e., insulating layer 234) is positioned in the first direction D1 at the adjacent positions at the ends of each active region 210a. Figure 10 As shown, but not limited to.

[0079] In addition, refer to Figure 10 The fabrication method of the shallow trench isolation 230 is not limited to the aforementioned. In another embodiment, it is also possible to remove the mask layer 220 (see reference). Figure 7 Before or after the cutting process, the cutting and fabrication process can be performed directly, and then a shallow trench isolation of a single material can be formed together (not shown). Alternatively, the top surface and active segment 210 can be formed first before the cutting and fabrication process. Figure 8 An insulating layer (not shown) with the top surface flush with the top surface is formed. Then, after the cutting process, another insulating layer (not shown) with the top surface flush with the top surface of the active region 210a is filled at the location where the active segment 210 is removed, forming a shallow trench isolation (not shown) with the top surface of the active region 210a flush with the top surface, making the active region 210a a planar active region; or, finally, a back etching process is performed together to etch the top surfaces of the insulating layer and the other insulating layer to a position lower than the top surface of the active region 210a, forming a shallow trench isolation 230.

[0080] Therefore, for reference Figure 10 and Figure 11 This completes the fabrication of the semiconductor device 20 according to the second embodiment of the present invention. The fabrication method according to this embodiment is a reverse application of... Figure 4 The mask layer 220 defines the contour of the active regions 210a, such that each active region 210a forms a cross-sectional contour that is wider at the top and narrower at the bottom, while the shallow trench isolation 230 between the active regions 210a forms a cross-sectional contour that is narrower at the top and wider at the bottom. With this configuration, the active regions 210a of the semiconductor device 20 can maintain a certain level of integration, while the shallow trench isolation 230, with its narrower-than-wider cross-sectional contour, effectively isolates adjacent active regions 210a, providing optimized insulation. Therefore, the semiconductor device 20 of this embodiment has improved structural advantages and can be used to form other active semiconductor components to further improve the performance of subsequently formed devices. For example, in subsequent manufacturing processes, transistor components (not shown) can be formed on the active region 210a of the semiconductor device 20 to serve as fin field-effect transistors (not shown); or, transistor components (not shown) and memory components (not shown) can be formed in and on the active region 210a of the semiconductor device 20 respectively to serve as the smallest unit of a dynamic random access memory device (not shown).

[0081] Please refer to Figure 12 The illustration shown is a schematic diagram of a semiconductor device 30 in a preferred embodiment of the present invention. The structure of the semiconductor device 30 in this embodiment is generally the same as that of the semiconductor device 20 in the aforementioned second embodiment, also including an active region 210a and a shallow trench isolation 230a (including insulating layers 232a and 234a). Furthermore, the fabrication method of the front end of the semiconductor device 30 in this embodiment is generally the same as that of the semiconductor device 20 in the aforementioned second embodiment, such as... Figures 3 to 11 As shown, the similarities will not be repeated here. The main difference between the semiconductor device 30 in this embodiment and the aforementioned second embodiment is that the top surface of the shallow trench isolation 230a is flush with the top surface of the active region 210a, and, in forming as... Figure 10 and Figure 11 After the structure shown, multiple buried gates 240 are formed in the active region 210a, and multiple gate lines 260 and multiple plugs 290 are formed in alternating arrangement on the active region 210a.

[0082] Specifically, the substrate 200 includes, for example, a cell region (not shown) with relatively high component density and a pierphery region (not shown) with relatively low component density. First, multiple buried gates 240 are formed within the cell region, extending through the active region 210a. Although the overall extension direction of the active region 210a and the buried gates 240 is not specifically shown in the accompanying drawings of this embodiment, those skilled in the art should easily understand that, viewed from a top view (not shown), the buried gates 240 extend along, for example, along... Figure 10 The x-direction shown extends and intersects with multiple active regions 210a and shallow ditch isolation 230a.

[0083] like Figure 12 As shown, each buried gate 240 includes a dielectric layer 242, a gate dielectric layer 244, a gate 246, and a capping layer 248 stacked sequentially from bottom to top. The surface of the capping layer 248 of each buried gate 240 can be aligned with the surface of the active region 210a, so that each buried gate 240 can serve as a buried word line (BWL) of the semiconductor device 30, and can be further formed into a transistor assembly (not shown) located in the substrate 200 in subsequent fabrication processes. In one embodiment, the method of fabricating the buried gate 240 includes, but is not limited to, the following steps: for example, first forming a plurality of trenches (not shown) that pass through the active region 210a and the shallow trench isolation 230a; then, sequentially forming a dielectric layer 242 covering the entire surface of the trench, a gate dielectric layer 244 covering the lower half of the surface of the trench, a gate 246 filling the lower half of the trench, and a capping layer 248 filling the upper half of the trench, but not limited to this.

[0084] It should be noted that in this embodiment, the buried gate 240 is preferably formed within the second semiconductor sublayer 214, that is, the bottom surface of the buried gate 240 is not lower than the second interface 214a, such as... Figure 12 As shown, the channel (not shown) of the buried gate 240 can also fall within the second semiconductor sublayer 214, for example, above the second interface 214a, so that the channel of the buried gate 240 is higher than the second interface 214a, or the bottom surface of the buried gate 240 just overlaps with the second interface 214a, but it is not limited to this. In another embodiment, depending on the actual device requirements, the bottom surface of a buried gate (not shown) can also be formed within the first semiconductor sublayer 212. In this way, the channel (not shown) of the buried gate will fall within the first semiconductor sublayer 212 and be located between the first interface 212a and the second interface 214a.

[0085] Please refer to this again. Figure 12As shown, after the buried gate 240 is formed, an insulating layer 250 is formed on the surface of the active region 210a, for example, comprising a silicon monoxide-silicon nitride-oxide (ONO) structure, completely covering the active region 210a and the buried gate 240. Then, gate lines 260 and plugs 290 are sequentially formed on the insulating layer 250. Although the overall extension direction of the gate lines 260 is not specifically shown in the accompanying drawings of this embodiment, those skilled in the art should easily understand that, viewed from a top view (not shown), each gate line 260 extends along, for example, along... Figure 10 The line extends in the y-direction and intersects with the active region 210a and the buried gate 240. The gate line 260 that crosses each active region 210a is formed by a portion of the semiconductor material layer 262 formed below it, which passes through the insulating layer 150 and extends into the active region 210a. This allows each gate line 260 to serve as a bit line of the semiconductor device 30, while a portion of the semiconductor material layer 262 serves as a bit line contact (BLC), electrically connecting to the transistor assembly formed in the substrate 200.

[0086] Specifically, refer to Figure 12 Each gate line 260 includes, from bottom to top, a semiconductor material layer 262 (e.g., containing polysilicon), a barrier layer 264 (e.g., containing titanium and / or titanium nitride), a conductive layer 266 (e.g., containing a low-resistivity metal such as tungsten, aluminum, or copper), and a capping layer 268 (e.g., containing silicon oxide, silicon nitride, or silicon oxynitride). The sidewalls of the gate line 260 include spacer walls 270 having a single-layer structure or a composite layer structure. In one embodiment, the gate line 260 is fabricated in a manner including but not limited to the following steps: for example, firstly, an etching process is performed on a mask layer (not shown) to partially remove the insulating layer 250 and a portion of the active region 210a below it to form contact openings between adjacent buried gates 240; then, the mask layer is removed and a semiconductor material (not shown, for example, including polysilicon), a barrier material layer (not shown, for example, including titanium and / or titanium nitride), a conductive material layer (not shown, for example, including low-resistivity metals such as tungsten, aluminum, or copper), and a cover material layer (not shown, for example, including silicon oxide, silicon nitride, or silicon oxynitride) are sequentially formed on the active region 210a; finally, the gate line 260 is formed by a patterning process, and the semiconductor material layer 262 filling the contact openings simultaneously forms contacts.

[0087] Subsequently, after the gate line 260 is formed, the plug 290 is formed through a patterned manufacturing process. For example... Figure 12As shown, the plugs 290 and gate lines 260 are alternately disposed on the active region 210a, passing through the insulating layer 250 and directly contacting both ends of the active region 210a. Thus, each plug 290 sequentially overlaps with the active region 210a and the shallow trench isolation 230 directly below it in the direction perpendicular to the substrate 200. In one embodiment, the plugs 290 are made of low-resistivity metals such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W) to serve as storage node contacts (SNCs) of the semiconductor device 30, electrically connecting to transistor components formed within the substrate 200. On the other hand, an insulating structure 280 is formed on the insulating layer 250 and sandwiched between the plugs 290 and the gate lines 260 to isolate the gate lines 260 from the plugs 290.

[0088] refer to Figure 12 According to this embodiment, the semiconductor device 30 has buried gates 240 within each active region 210a that is wider at the top and narrower at the bottom, and gate lines 260 and plugs 290 are provided on each active region 210a. With this configuration, the active regions 210a of the semiconductor device 30 maintain a certain level of integration, while the shallow trench isolation 230a, which has a narrower cross-sectional profile at the top and wider at the bottom, effectively isolates various components (such as buried gates 240, gate lines 260, or plugs 290) located within or above adjacent active regions 210a. This gives the semiconductor device 30 significant structural advantages, achieving relatively optimized device performance. Furthermore, in subsequent fabrication processes, memory components (not shown) can be formed on the active regions 210a of the semiconductor device 30, thus forming the smallest unit of a dynamic random access memory device together with the transistor components in the substrate 200. Thus, the memory device fabricated according to the semiconductor device 30 of this embodiment can benefit from the structural advantages of the active region 210a, improve the integration level of the memory cells, and improve the device defects that may arise from the improved integration level, thereby achieving superior performance.

[0089] Please refer to Figure 13 The illustration shown is a schematic diagram of a semiconductor device 40 in another preferred embodiment of the present invention. The structure and fabrication method of the semiconductor device 40 in this embodiment are generally the same as or similar to those in the foregoing embodiments, and the similarities will not be repeated here. The main difference between the semiconductor device 40 in this embodiment and the foregoing embodiments is that each active region 310 has two opposite sidewalls 311 and 313 with the same degree of inclination in the cross section of the first direction D1.

[0090] Specifically, in this embodiment, in forming such Figure 4After the mask layer 220 shown, multiple inner blocking layers (cut-first blocking, not shown) are additionally formed within each opening 222. The ends of the active regions 310 are predefined by cutting off the openings 222 through the inner blocking layers. Then, two deposition processes are performed to form each active region 310. In this way, the cutting process can be omitted, and the fabrication of the shallow trench isolation 330 is simplified. It is only necessary to directly form a shallow trench isolation 330 with a single material and a top surface flush with the top surface of the active regions 310 after the active regions 310 are formed. In addition, in this embodiment, the sidewalls of the active regions 310 in the first direction D1 or the second direction D2 are all made of the following material: Figure 4 As defined by the mask layer 220 shown, they therefore have the same slope. For example, the two opposite sidewalls 311, 313 of the cross-section of each active region 310 in the first direction D1 are respectively formed with the surface 202 of the substrate 200 at the same angle θ1, such as... Figure 13 As shown.

[0091] Under this setting, refer to Figure 13 In this embodiment, the active region 310 of the semiconductor device 40 can effectively isolate various components (such as buried gates 240, gate lines 260, or plugs 290) disposed within or above adjacent active regions 310 by means of a shallow trench isolation 330 with a cross-sectional profile that is narrow at the top and wide at the bottom, while maintaining a certain level of integration. This gives the semiconductor device 40 significant structural advantages and achieves relatively optimized device performance. Furthermore, in subsequent fabrication processes, memory components (not shown) can be formed on the active region 310 of the semiconductor device 40, thereby forming the smallest unit of a dynamic random access memory device together with the transistor components in the substrate 200. Thus, the memory device fabricated according to the semiconductor device 40 of this embodiment can benefit from the structural advantages of the active region 310, improve the integration level of the memory cells, and achieve superior performance, effectively mitigating device defects that may arise from increased integration levels.

[0092] Overall, the fabrication method of this invention utilizes a mask layer to define the contours of the active regions, resulting in a cross-sectional profile that is wider at the top and narrower at the bottom for the active regions, while the shallow trench isolation between the active regions has a cross-sectional profile that is narrower at the top and wider at the bottom. With this configuration, the semiconductor device fabricated by the method of this invention can effectively isolate adjacent active regions by presenting shallow trench isolation with a narrower top and wider bottom cross-sectional profile, while maintaining a certain level of integration, thus providing optimized insulation. In this way, the semiconductor device has improved structural advantages and can be further used to form other active semiconductor components, mitigating device defects that may arise from increased integration levels.

[0093] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized by Comprising: a substrate having a surface; a plurality of active regions disposed on the surface of the substrate, wherein each of the active regions comprises a semiconductor layer having a first interface with the substrate; a first shallow trench isolation disposed on the substrate and surrounding the active regions; and a second shallow trench isolation disposed between adjacent ends of the active regions; a plurality of buried gates embedded within the active regions and above the first interface; the active regions have a top wide and bottom narrow cross section, the cross section includes a first sidewall in direct contact with the first shallow trench isolation, and a second sidewall in direct contact with the second shallow trench isolation, the first sidewall has a first included angle with a bottom surface of the first shallow trench isolation, the second sidewall has a second included angle with a bottom surface of the second shallow trench isolation, the second included angle is greater than the first included angle. the semiconductor layer comprises a concentration gradient of a heterogeneous atom.

2. The semiconductor device according to claim 1, wherein the semiconductor layer comprises a first semiconductor sub-layer and a second semiconductor sub-layer stacked in sequence, the first semiconductor sub-layer and the second semiconductor sub-layer have a second interface therebetween, the second interface has a circular arc or hexagonal cross section.

3. The semiconductor device of claim 2, wherein, a lattice of the first semiconductor sub-layer is smaller than a lattice of the second semiconductor sub-layer, a concentration of the heterogeneous atom in the first semiconductor sub-layer is greater than a concentration of the heterogeneous atom in the second semiconductor sub-layer.

4. The semiconductor device according to claim 3, wherein a channel of the buried gate overlaps the second interface.

5. The semiconductor device of claim 3, wherein the channel of the buried gate is above the second interface.

6. The semiconductor device of claim 3, wherein the channel of the buried gate is between the first interface and the second interface.

7. The semiconductor device of claim 3, wherein Further comprising:

8. The semiconductor device of claim 1, wherein at least one gate line disposed on the substrate between two adjacent buried gates; and a plurality of plugs disposed on the active regions and alternating with the gate lines, each of the plugs sequentially overlaps the active regions and the shallow trench isolation in a direction perpendicular to the substrate. each of the active regions has a top wide and bottom narrow cross section. the cross section of each of the active regions has sidewalls with different degrees of inclination.

9. The semiconductor device of claim 1, wherein, Comprising:

10. The semiconductor device of claim 9, wherein, providing a substrate having a surface; 11. A method of fabricating a semiconductor device, characterized by forming a plurality of active regions on the surface of the substrate, wherein each of the active regions comprises a semiconductor layer having a first interface with the substrate; forming a first shallow trench isolation on the substrate and surrounding the active regions, and a second shallow trench isolation disposed between adjacent ends of the active regions; forming a plurality of buried gates within the active regions, the buried gates being above the first interface; the active regions have a top wide and bottom narrow cross section, the cross section includes a first sidewall in direct contact with the first shallow trench isolation, and a second sidewall in direct contact with the second shallow trench isolation, the first sidewall has a first included angle with a bottom surface of the first shallow trench isolation, the second sidewall has a second included angle with a bottom surface of the second shallow trench isolation, the second included angle is greater than the first included angle. forming each of the active regions further comprises: forming a mask layer on the surface, the mask layer having a plurality of openings; 12. The method of fabricating a semiconductor device according to Claim 11, wherein forming the semiconductor layer within the openings through the mask layer; and ​ ​ removing the mask layer.

13. The method of fabricating a semiconductor device according to Claim 12, wherein forming the semiconductor layer further comprises:

14. The method of fabricating a semiconductor device according to Claim 12, wherein depositing a material layer within the opening; and performing a heat treatment process to modify the material layer into the semiconductor layer. forming the semiconductor layer further comprises:

15. The method of fabricating a semiconductor device according to Claim 12, wherein performing a first deposition process to form a first semiconductor sub-layer within the opening; and performing a second deposition process to form a second semiconductor sub-layer within the opening, on the first semiconductor sub-layer, the first semiconductor sub-layer and the second semiconductor sub-layer having a second interface therebetween. forming each of the active regions further comprises:

16. The method of fabricating a semiconductor device according to Claim 12, wherein performing a cutting process to cut the semiconductor layer into the active regions after removing the mask layer. the cutting process is performed before forming the shallow trench isolation.

17. The method of fabricating a semiconductor device according to Claim 16, wherein the cutting process is performed after forming part of the shallow trench isolation.

18. The method of fabricating a semiconductor device according to Claim 16, wherein forming each of the active regions further comprises:

19. The method of fabricating a semiconductor device according to Claim 12, wherein forming a plurality of inner barrier layers within each of the openings to block each of the openings; and forming the active regions through the mask layer and the inner barrier layers. further comprising:

20. The method of fabricating a semiconductor device of claim 11, wherein, forming at least one gate line on the substrate, between two adjacent buried gates; and forming a plurality of plugs on the active regions, the plugs and the gate lines being arranged alternately, each of the plugs sequentially overlapping the active regions and the shallow trench isolation in a direction perpendicular to the substrate. ​ ​

Images