A TOPCon battery and its preparation method
By setting first and second doped polycrystalline silicon regions on the back of the TOPCon cell and etching grooves, the grid line structure is optimized, solving the problems of high screen printing difficulty and metallization damage passivation, thereby improving the cell's open-circuit voltage and fill factor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHUZHOU JIETAI NEW ENERGY TECH CO LTD
- Filing Date
- 2023-05-31
- Publication Date
- 2026-05-26
AI Technical Summary
In existing TOPCon batteries, increasing the grid line aspect ratio presents significant challenges in screen fabrication, and the metal electrodes may disrupt the passivation effect of the interface oxide layer, leading to a decline in battery performance.
By setting first and second doped polycrystalline silicon regions on the back of a single-crystal silicon wafer and etching grooves in the first region, combined with laser grooving technology, a deeper inner expansion layer and a larger contact area are formed, thus optimizing the gate line structure.
It improves the open-circuit voltage and fill factor of the battery, reduces the contact resistance, solves the problems of process complexity and metallization printing difficulties in the existing technology, and achieves a high-efficiency improvement in battery performance.
Smart Images
Figure CN116469948B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of TOPCon batteries, and more specifically, to a TOPCon battery and its preparation method. Background Technology
[0002] Existing TOPCon (tunneling oxide passivated contact) solar cells typically consist of a 1-2 nm ultrathin tunneling oxide layer fabricated on the back side of a silicon wafer, followed by the deposition of an 80-200 nm thick doped polycrystalline silicon layer on the oxide layer surface, and finally, silicon nitride deposited on the doped polycrystalline silicon layer. This structure provides excellent surface and field passivation for the back side of the silicon wafer. The ultrathin oxide layer allows electrons to tunnel into the polycrystalline silicon layer while blocking hole transport, reducing recombination current. The lateral transport characteristics of the doped polycrystalline silicon layer reduce series resistance. These two characteristics together improve the open-circuit voltage, fill factor, and conversion efficiency of the cell.
[0003] On the back of TOPCon solar cells, an Ag paste is typically used to burn through the dielectric film and form an ohmic contact with doped polycrystalline silicon. In crystalline silicon solar cells, the grid lines act as collectors of photogenerated charge carriers. The amount of charge carriers generated (the magnitude of the short-circuit current) and the amount of charge carrier loss during collection (the magnitude of the series resistance) largely determine the electrical performance of the cell. Higher grid line height and narrower width (i.e., a larger aspect ratio) contribute to increasing the short-circuit current and decreasing the series resistance of the cell.
[0004] Currently, grid lines are mainly obtained through screen printing and sintering of paste. Under the same process conditions, increasing the aspect ratio of the grid lines and selecting a high-mesh screen results in a small screen opening area, which is detrimental to the silver paste loading. Therefore, coordinating the grid line aspect ratio with the screen printing process is challenging. Furthermore, during paste sintering, Ag grains may penetrate the doped polycrystalline silicon film, damaging the passivation effect of the interface oxide layer. To reduce the recombination current density in the metal contact area, the doped polycrystalline silicon thickness cannot be too thin, typically between 100-150 nm. To ensure good field passivation and low ohmic contact, the doped polycrystalline silicon needs a sufficient doping concentration, typically greater than 1e20 cm⁻¹. -3 However, excessive thickness and doping concentration of the polycrystalline silicon film in the aforementioned passivation structure can cause severe Auger recombination on the surface, resulting in a deterioration in the short-wavelength response of the battery and an increase in the saturation current.
[0005] Currently, the main approach is to minimize the thickness and doping concentration of the polycrystalline silicon film while ensuring that the metal electrode paste does not burn through the tunnel oxide layer and that the metal electrode forms a good ohmic contact with the polycrystalline silicon film, in order to reduce current loss. Alternatively, the passivation structure can be used only in the metal electrode region of the battery, which makes it difficult to balance the light absorption and passivation effects of the battery.
[0006] Industry experts have also disclosed that the polysilicon doped layer on the tunneling layer is set into a first region and a second region with different thicknesses, with the metal electrode located on the thicker first region. However, the fabrication process of polysilicon doped layers with different thicknesses is more complex. Moreover, as the overall thickness of the film decreases, it becomes more difficult to differentiate the thickness of the polysilicon doped layer in different regions. Summary of the Invention
[0007] To overcome the problem of coordinating the increase in grid line aspect ratio with the high difficulty in screen printing process when using existing TOPCon cells to improve short-circuit current and reduce series resistance, this invention provides a TOPCon cell comprising a monocrystalline silicon wafer. The front side of the monocrystalline silicon wafer, from the inside out, is provided with a diffusion layer, a passivation layer, a front anti-reflection layer, and a front metal electrode; the back side of the monocrystalline silicon wafer, from the inside out, is provided with a tunneling layer, a doped polycrystalline silicon layer, a back anti-reflection layer, and a back metal electrode.
[0008] The doped polycrystalline silicon layer includes a first doped polycrystalline silicon region and a second doped polycrystalline silicon region. The back metal electrode penetrates the back antireflection layer and contacts the first doped polycrystalline silicon region. The first doped polycrystalline silicon region is phosphorus-doped polycrystalline silicon with a thickness of 100-200 nm and a doping concentration of not less than 1e20cm. -3 The second doped polycrystalline silicon region is a phosphorus-doped polycrystalline silicon layer with a thickness of 100-200 nm and a doping concentration of not less than 1e20 cm⁻¹. -3 The junction depth of the first doped polysilicon region is greater than that of the second doped polysilicon region. Here, the first doped polysilicon region and the second doped polysilicon region correspond to the back metal region and the back non-metal region, respectively.
[0009] Preferably, a groove is etched at the corresponding position of the first doped polysilicon region on the back side of the monocrystalline silicon wafer, the corresponding inner junction depth of the doped polysilicon layer is 50-500nm, and the difference in the corresponding inner junction depth between the first doped polysilicon region and the second doped polysilicon region is 10-150nm.
[0010] Preferably, the junction depth of the first doped polysilicon region is 150-300 μm, and the junction depth of the second doped polysilicon region is 50-200 μm.
[0011] Preferably, the doping concentration difference between the first doped polysilicon region and the second doped polysilicon region does not exceed 1e19cm. -3 .
[0012] Preferably, the back tunneling layer is silicon oxide with a thickness of 1-3 nm.
[0013] Preferably, the back antireflection layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.
[0014] Preferably, the total thickness of the back antireflection layer is 70-120 nm; the overall refractive index of the back antireflection layer is 1.9-2.1, and the refractive index of the film layer decreases sequentially in the direction away from the single crystal silicon wafer.
[0015] Preferably, the back metal electrode is an Ag gate electrode with an aspect ratio of 0.5-0.8; and the width of the second doped polysilicon region is greater than the width of the back metal electrode.
[0016] The present invention also provides a method for preparing the above-mentioned TOPCon battery, comprising the following steps:
[0017] On the back of the silicon wafer after texturing and BCl3 diffusion, laser grooving is used to etch grooves at the corresponding positions of the first doped polycrystalline silicon region on the back of the monocrystalline silicon wafer.
[0018] Single-sided etching removes the BSG layer on the back side;
[0019] Backside etching removes the PN junction formed by parasitic diffusion on the backside, while polishing the surface to be etched, forming a polished surface in the ungrooved area and a groove in the grooved area.
[0020] A tunneling layer is prepared on the back side of a single-crystal silicon wafer, and the thickness of the tunneling oxide layer at the groove is lower than that on the polished surface.
[0021] An intrinsic amorphous silicon layer is deposited on the surface of the tunneling layer, and phosphorus diffusion doping is performed on the intrinsic amorphous silicon layer to transform it from an amorphous state to a crystalline state.
[0022] Deposit a back antireflection layer on the surface of a doped polycrystalline silicon layer;
[0023] A metal electrode is printed on the surface of the back antireflection layer corresponding to the first doped polysilicon region, and co-sintering is performed so that the metal electrode burns through the back antireflection layer to form an ohmic contact with the first doped polysilicon region.
[0024] Preferably, during phosphorus diffusion doping, POCl3 is used for diffusion to crystallize amorphous silicon, forming a doped polycrystalline silicon layer, and the doping concentration is controlled at (1-5)e²⁰cm⁻¹. -3 Because the thickness of the tunneling oxide layer at the groove is lower than that of the polished surface, the depth of the inner expansion junction corresponding to the first doped polysilicon layer is greater.
[0025] Preferably, the laser wavelength for laser grooving is 532nm or 1064nm.
[0026] Beneficial effects:
[0027] The beneficial effects of adopting the technical solution of this invention are as follows:
[0028] (1) The doped polysilicon layer is divided into a first doped polysilicon region and a second doped polysilicon region. The first doped polysilicon region is in contact with the back metal electrode. The first doped polysilicon region is set on the surface of the groove. The tunnel oxide layer is thinner and the inner junction depth is greater than that of the second doped polysilicon region. This can effectively prevent the electrode metal from penetrating into the junction region, reduce the metal region recombination current, and improve the battery open circuit voltage.
[0029] On the other hand, the first doped polysilicon region is set on the surface of the groove, which has a larger contact area with the printing paste, thus reducing the cell contact resistance. At the same time, the groove can prevent the printing paste from widening outward, ensuring a high grid line aspect ratio, reducing grid line resistance, and thereby improving the cell fill factor.
[0030] (2) By forming a groove surface by using back laser grooving at the corresponding position of the first doped polysilicon region, a deeper inner expansion layer and a larger contact area are obtained in the back metal region. This solves the technical problems in the prior art, such as complex mask preparation and removal processes, poor pattern accuracy, difficulty in alignment of subsequent metallization printing, inability to mass produce or high mass production cost. The preparation method is simple and easy to implement. Attached Figure Description
[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.
[0032] Figure 1 This is a structural diagram of the TOPCon battery layer in Example 1;
[0033] Figure 2 This is a structural diagram of the TOPCon battery layer in Comparative Example 1;
[0034] Figure 3 This is a flowchart of the TOPCon battery fabrication process in Example 1.
[0035] In the diagram, 1 is the monocrystalline silicon layer; 2 is the diffusion layer; 3 is the passivation layer; and 4 is the front anti-reflection layer.
[0036] 5. Front metal electrode; 6. Tunneling layer; 7. Doped polycrystalline silicon layer;
[0037] 71. First doped polysilicon region; 72. Second doped polysilicon region; 8. Back antireflection layer; 9. Back metal electrode. Detailed Implementation
[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0039] like Figure 1 As shown, the TOPCon cell includes a monocrystalline silicon wafer 1. The front side of the monocrystalline silicon wafer 1 is provided with a diffusion layer 2, a passivation layer 3, a front anti-reflection layer 4 and a front metal electrode 5 from the inside to the outside. The back side of the monocrystalline silicon wafer 1 is provided with a tunneling layer 6, a doped polycrystalline silicon layer 7 and a back anti-reflection layer 8 and a back metal electrode 9 from the inside to the outside.
[0040] The doped polysilicon layer 7 includes a first doped polysilicon region 71 and a second doped polysilicon region 72. The back metal electrode 9 penetrates the back antireflection layer 8 and contacts the first doped polysilicon region 71. The first doped polysilicon region 71 is phosphorus-doped polysilicon with a thickness of 100-200 nm and a doping concentration of not less than 1e20 cm⁻¹. -3 The second doped polycrystalline silicon region 72 is a phosphorus-doped polycrystalline silicon layer with a thickness of 100-200 nm and a doping concentration of not less than 1e20 cm⁻¹. -3 The junction depth of the first doped polysilicon region 71 is greater than that of the second doped polysilicon region 72. Here, the first doped polysilicon region 71 and the second doped polysilicon region 72 correspond to the back metal region and the back non-metal region, respectively.
[0041] In a preferred embodiment, a groove is etched at the corresponding position of the first doped polysilicon region on the back side of the monocrystalline silicon wafer, the corresponding inner expansion junction depth of the doped polysilicon layer is 50-500nm, and the junction depth difference between the first doped polysilicon region and the second doped polysilicon region is 10-150nm.
[0042] In a preferred embodiment, the junction depth of the first doped polysilicon region is 150-300 μm, and the junction depth of the second doped polysilicon region is 50-200 μm.
[0043] In a preferred embodiment, the doping concentration difference between the first doped polysilicon region and the second doped polysilicon region does not exceed 1e19cm. -3 .
[0044] In a preferred embodiment, the back tunneling layer is silicon oxide with a thickness of 1-3 nm, and is formed by thermal oxidation, wet chemical oxidation, ozone oxidation, or plasma oxidation.
[0045] In a preferred embodiment, the back antireflection layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.
[0046] In a preferred embodiment, the total thickness of the back antireflection layer is 70-120 nm; the overall refractive index of the back antireflection layer is 1.9-2.1, and the refractive index of the film layer decreases sequentially in the direction away from the single crystal silicon wafer.
[0047] In a preferred embodiment, the back metal electrode is an Ag gate electrode with an aspect ratio of 0.5-0.8; and the width of the second doped polysilicon region is greater than the width of the back metal electrode. Ag paste is printed using methods such as screen printing or laser transfer, and ohmic contact is formed between the back antireflection layer and the doped polysilicon layer through sintering.
[0048] In a preferred embodiment, the single-crystal silicon wafer is a phosphorus-doped N-type single-crystal silicon wafer with a resistivity of 0.1-10 Ωcm and a thickness of 100-200 μm.
[0049] In a preferred embodiment, the diffusion layer is a boron-doped P-type doped layer with a sheet resistance of 100-300 Ω / □, formed by high-temperature diffusion using BCl3 or BBr3.
[0050] In a preferred embodiment, the passivation layer is aluminum oxide with a thickness of 2-6 nm, obtained by ALD deposition;
[0051] In a preferred embodiment, the front antireflective layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.1. The refractive index of the film layers decreases sequentially away from the silicon wafer.
[0052] In a preferred embodiment, the front metal electrode is an AgAl gate electrode, which is printed with AgAl paste by means of screen printing, laser transfer, etc., and sintered through the front antireflection layer and passivation layer to form an ohmic contact with the doped layer.
[0053] This embodiment also provides a method for preparing the above-mentioned TOPCon battery, including the following steps:
[0054] Step S101, texturing, using acid and alkali chemicals to remove organic contaminants and metallic impurities from the silicon wafer surface, forming a surface texture on the silicon wafer surface to increase the absorption of sunlight and reduce reflection;
[0055] Step S102, boron diffusion to form a front diffusion layer; the diffusion layer is a boron-doped P-type doped layer.
[0056] Step S103, laser grooving on the back side: laser grooving is used to etch grooves under the metal area on the back side.
[0057] Step S104: Single-sided HF etching to remove the back side BSG layer;
[0058] Step S105: Backside etching to remove the PN junction formed by parasitic diffusion on the backside and prevent edge leakage.
[0059] In step S106, an in-situ oxidative tunneling oxide layer is generated using LPCVD technology, and an intrinsic amorphous silicon layer is deposited. Of course, other processes can also be selected to prepare the tunneling oxide layer and the intrinsic amorphous silicon layer, such as PECVD technology or sputtering.
[0060] Step S107, phosphorus diffusion, phosphorus diffusion doping is performed on the back amorphous silicon and amorphous silicon oxide, and they are transformed from the amorphous state to the crystalline state;
[0061] Step S108: Single-sided HF etching to remove the PSG layer on the front and edge of the polysilicon surface after diffusion.
[0062] Step S109, front etching, using alkaline solution etching to remove the polysilicon layer, and using hydrofluoric acid cleaning to remove the BSG on the front and the PSG on the back.
[0063] Step S110: A dense AlOx film is deposited on the front side of the substrate using ALD atomic layer deposition.
[0064] Step S111: Deposit one or more stacked films of silicon nitride and silicon oxynitride on the front side of the substrate by PECVD.
[0065] Step S112: Deposit one or more stacked films of silicon nitride and silicon oxynitride on the back side of the substrate by PECVD.
[0066] Step S113: Print Ag / Al electrode paste on the front side and Ag electrode paste on the back side; co-sinter to form good ohmic contact; photoinjection to repair defects in the cell body and surface.
[0067] The preparation order of the front and back layers of the battery in S101-S113 can be adjusted according to actual needs, and the structure of the front and back layers of the battery can also be prepared using other existing commonly used processes.
[0068] The following examples and comparative examples further illustrate the beneficial effects of the TOPCon battery structure and its preparation method in this embodiment.
[0069] Example 1:
[0070] like Figure 1 As shown, the TOPCon cell includes a monocrystalline silicon wafer 1. The front side of the monocrystalline silicon wafer 1 is provided with a diffusion layer 2, a passivation layer 3, a front anti-reflection layer 4 and a front metal electrode 5 from the inside to the outside. The back side of the monocrystalline silicon wafer 1 is provided with a tunneling layer 6, a doped polycrystalline silicon layer 7 and a back anti-reflection layer 8 and a back metal electrode 9 from the inside to the outside.
[0071] The doped polysilicon layer 7 includes a first doped polysilicon region 71 and a second doped polysilicon region 72. The back metal electrode 9 penetrates the back antireflection layer 8 and contacts the first doped polysilicon region 71. The first doped polysilicon region 71 is phosphorus-doped polysilicon with a thickness of 100-200 nm and a doping concentration of not less than 1e20 cm⁻¹. -3 The second doped polycrystalline silicon region 72 is a phosphorus-doped polycrystalline silicon layer with a thickness of 100-200 nm and a doping concentration of not less than 1e20 cm⁻¹. -3 The junction depth of the first doped polysilicon region is 150-300 nm, and the junction depth of the second doped polysilicon region is 50-200 nm; the inner junction depth of the first doped polysilicon region 71 is greater than that of the second doped polysilicon region 72.
[0072] like Figure 3 As shown, the above-mentioned TOPCon battery fabrication method includes the following steps:
[0073] Step S101: Texturing. Select a phosphorus-doped N-type single crystal silicon wafer with a resistivity of 0.5-1.0 Ωcm and a thickness of 130-160 μm. Use acid and alkali chemicals to remove organic contaminants and metallic impurities from the silicon wafer surface, forming a surface texture on the silicon wafer surface to increase the absorption of sunlight and reduce reflection.
[0074] Step S102, boron diffusion, using BCl3 low-voltage diffusion of the front PN junction, diffusion temperature 950-1050℃, sheet resistance 150-250Ω / □;
[0075] Step S103, back side laser grooving, using laser grooving to etch grooves below the back side metal area; the laser wavelength for the laser grooving is 532nm;
[0076] Step S104: Single-sided HF etching to remove the back side BSG layer;
[0077] Step S105: Backside etching to remove the PN junction formed by parasitic diffusion on the backside, prevent edge leakage, and form a groove at the laser etched groove.
[0078] Step S106: Using LPCVD process, an in-situ oxidation is performed to generate a tunneling oxide layer at a temperature of 550-650℃ and a thickness of 1-3nm; and an intrinsic amorphous silicon layer with a thickness of 120-150nm is deposited. Of course, other processes can also be selected to prepare the tunneling oxide layer and the intrinsic amorphous silicon layer, such as PECVD process or sputtering method.
[0079] Step S107, phosphorus diffusion, using POCl3 diffusion to crystallize amorphous silicon to form a doped polycrystalline silicon layer, controlling the doping concentration to be (1-5)e20cm. -3 Since the thickness of the tunneling oxide layer at the groove is lower than that of the polished surface, the inner expansion junction depth corresponding to the first doped polysilicon layer is greater than that of the second doped polysilicon layer. In a preferred embodiment, the junction depth of the first doped polysilicon region is 150-300 nm, and the junction depth of the second doped polysilicon region is 50-200 nm.
[0080] Step S108: Single-sided HF etching to remove the PSG layer on the front and edge of the polysilicon surface after diffusion.
[0081] Step S109, front etching, using alkaline solution etching to remove the polysilicon layer, and using hydrofluoric acid cleaning to remove the BSG on the front and the PSG on the back.
[0082] Step S110: A dense AlOx film with a thickness of 3-5 nm is deposited on the front side of the substrate using ALD atomic layer deposition.
[0083] Step S111: Deposit one or more stacked films of silicon nitride and silicon oxynitride on the front side of the substrate by PECVD, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.1.
[0084] Step S112: Deposit one or more stacked films of silicon nitride and silicon oxynitride on the back side of the substrate by PECVD, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.1.
[0085] Step S113: Print Ag / Al electrode paste on the front side and Ag electrode paste on the back side; co-sinter to form good ohmic contact; photoinjection to repair defects in the cell body and surface.
[0086] Comparative Example 1:
[0087] like Figure 2As shown, compared with Example 1, the difference is that the back side of the silicon wafer uses single-doped polycrystalline silicon with a thickness of 120-130 nm and a doping concentration of (2-3)e20cm. -3 .
[0088] The batteries in one set of embodiments and one set of comparative embodiments were tested under the same conditions, and the test results are shown in Table 1.
[0089] Table 1. Battery test results for the examples and comparative examples.
[0090]
[0091] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.
Claims
1. A TOPCon battery, characterized in that, The wafer includes a monocrystalline silicon wafer, wherein the front side of the monocrystalline silicon wafer is provided with a diffusion layer, a passivation layer, a front anti-reflection layer and a front metal electrode in sequence from the inside to the outside; and the back side of the monocrystalline silicon wafer is provided with a tunneling layer, a doped polycrystalline silicon layer, a back anti-reflection layer and a back metal electrode in sequence from the inside to the outside. The doped polysilicon layer comprises a first doped polysilicon region and a second doped polysilicon region, the back metal electrode penetrates the back anti-reflection layer and contacts the first doped polysilicon region; the first doped polysilicon region is phosphorus-doped polysilicon, with a thickness of 100-200 nm and a doping concentration not less than 1e20 cm -3 -3; the second doped polysilicon region is phosphorus-doped polysilicon layer, with a thickness of 100-200 nm and a doping concentration not less than 1e20 cm -3 -3. A groove is etched on the back of the monocrystalline silicon wafer at a position corresponding to the first doped polycrystalline silicon region, and the first doped polycrystalline silicon region is located on the surface of the groove; the inner expansion depth of the first doped polycrystalline silicon region is greater than that of the second doped polycrystalline silicon region. The method for forming the first doped polycrystalline silicon region with a greater inner junction depth than the second doped polycrystalline silicon region is as follows: deposit an intrinsic amorphous silicon layer on the surface of the tunneling layer, and perform phosphorus diffusion doping on the intrinsic amorphous silicon layer to transform it from an amorphous state to a crystalline state; during phosphorus diffusion doping, since the thickness of the tunneling oxide layer at the groove is lower than that of the polished surface, the inner junction depth corresponding to the first doped polycrystalline silicon region is greater than that of the second doped polycrystalline silicon region.
2. The TOPCon battery according to claim 1, characterized in that, The corresponding inner junction depth of the doped polysilicon layer is 50-500nm, and the difference in the corresponding inner junction depth between the first doped polysilicon region and the second doped polysilicon region is 30-250nm.
3. A TOPCon battery according to claim 2, characterized in that, The inner junction depth of the first doped polysilicon region is 150-300 nm, and the inner junction depth of the second doped polysilicon region is 50-200 nm.
4. A TOPCon battery according to claim 1, characterized in that, The doping concentration difference between the first doped polysilicon region and the second doped polysilicon region does not exceed 1e19cm. -3 .
5. A TOPCon battery according to claim 1, characterized in that, The back tunneling layer is silicon oxide with a thickness of 1-3 nm.
6. A TOPCon battery according to claim 1, characterized in that, The back antireflection layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide; the total thickness of the back antireflection layer is 70-120 nm; the overall refractive index of the back antireflection layer is 1.9-2.1, and the refractive index of the film layer decreases sequentially in the direction away from the single crystal silicon wafer.
7. A TOPCon battery according to claim 1, characterized in that, The back metal electrode is an Ag gate electrode with an aspect ratio of 0.5-0.8; and the width of the second doped polysilicon region is greater than the width of the back metal electrode.
8. A method for preparing a TOPCon battery as described in any one of claims 1-7, characterized in that, Includes the following steps: On the back of the silicon wafer after texturing and BCl3 diffusion, laser grooving is used to etch grooves at the corresponding positions of the first doped polycrystalline silicon region on the back of the monocrystalline silicon wafer. Single-sided etching removes the BSG layer on the back side; Backside etching removes the PN junction formed by parasitic diffusion on the backside, while polishing the backside to form a polished surface in the ungrooved area and a groove in the grooved area. A tunneling layer is prepared on the back side of a single-crystal silicon wafer, and the thickness of the tunneling oxide layer at the groove is lower than that on the polished surface. An intrinsic amorphous silicon layer is deposited on the surface of the tunneling layer, and phosphorus diffusion doping is performed on the intrinsic amorphous silicon layer to transform it from an amorphous state to a crystalline state. During phosphorus diffusion doping, since the thickness of the tunneling oxide layer at the groove is lower than that of the polished surface, the inner junction depth corresponding to the first doped polycrystalline silicon region is greater than that of the second doped polycrystalline silicon region. Deposit a back antireflection layer on the surface of a doped polycrystalline silicon layer; A metal electrode is printed on the surface of the back antireflection layer corresponding to the first doped polysilicon region, and co-sintering is performed so that the metal electrode burns through the back antireflection layer to form an ohmic contact with the first doped polysilicon region.
9. The method for preparing a TOPCon battery according to claim 8, characterized in that, During phosphorus diffusion doping, POCl3 is used for diffusion to crystallize amorphous silicon, forming a doped polycrystalline silicon layer, with the doping concentration controlled at (1-5)e20cm⁻¹. -3 .
10. A method for preparing a TOPCon battery according to claim 8, characterized in that, During laser grooving, the laser wavelength is 532nm or 1064nm.