Staged time-to-digital converter, control method, medium, device and terminal

Abstract

The present application belongs to the technical field of time interval measurement, and discloses a segmented time-to-digital converter, a control method, a medium, an equipment and a terminal, which change the structure of a delay chain, utilize a plurality of short parallel chains to measure the 'fine' time of a signal to be measured in a TDL TDC, and introduce different fixed delay processing in front of each short chain to enable each short chain to essentially perform parallel measurement on different intervals of the signal to be measured, wherein the number of chain lengths is determined according to clock conditions and the measurement interval of each chain. The control method of the segmented time-to-digital converter has good linearity, the entire long chain is ingeniously placed in a logic block through a folding manner, and the nonlinearity problem caused by the inconsistent line length introduced due to the crossing of multiple resource blocks is completely avoided; the segmented time-to-digital converter has a simple structure, high resource utilization, and good robustness, is not sensitive to the changes of devices and channels, and can correct the drift introduced by temperature online.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of time interval measurement, and particularly relates to a segmented time-to-digital converter, a control method, a medium, a device and a terminal. BACKGROUND

[0002] At present, a time-to-digital converter (TDC) is a high-precision (picosecond level) time interval measurement unit, which is widely used in many industrial application fields, including nuclear physics, automotive vehicles, medical imaging, etc. A simple TDC can use a high-frequency clock signal to roughly depict a time interval by calculating the number of clocks experienced, but the resolution of this method is limited by the clock frequency, usually in nanoseconds.

[0003] Existing TDC solutions can be divided into analog and digital solutions. Analog solutions include time stretching or time-amplitude conversion. On the one hand, these analog solutions need to use analog quantities in implementation, which are easily affected by signal fluctuations; on the other hand, the single measurement time of these solutions is often much higher than the time interval to be measured, i.e., a longer conversion rate, which results in a too long dead time and cannot perform high-frequency measurement. Therefore, although they can achieve an observable integrated non-linearity (INL) performance, even a sub-picosecond time resolution, they are not very common. In contrast, digital solutions are more popular because they can be deployed and iterated faster (on FPGAs), have a more compact hardware structure, are flexible, and are more tolerant to noise interference. Therefore, digital TDC solutions are more popular.

[0004] The first digital solution is the interpolation method, also known as the Nutt method. The interpolation method uses multiple delay units (usually carry modules in FPGA) to interpolate the system clock. In this method, a series of delay units are connected in series to form a long chain (also known as a tapped delay line, TDL), and their measurement results are often referred to as "fine" time. In the Nutt method, the system clock is first used to roughly measure the time interval to be measured, and the time to be measured is divided into an integer clock component and a fractional clock component. The integer clock component can be obtained by counting, and the fractional clock component can be obtained by measuring the number of delay units in the TDL chain that are triggered. In this method, the delay time that each delay unit in the TDL chain can cause can be obtained in advance by code density measurement, and the number of triggers of these units can be obtained by measurement, so the value of the "fine" time can be obtained, and the value of the "coarse" time obtained by the system clock can be combined to obtain the final time interval.

[0005] The premise of this method is that each delay cell has the same delay, which also determines the time resolution of the measurement. However, the characteristics of these delay cells are easily affected by device inherent defects, power and temperature dynamics, etc., resulting in serious non-linear problems. At the same time, the inherent delay of each cell is determined by its manufacturing process and cannot be modified. Therefore, once the hardware platform is determined, the time resolution of the TDC is also determined. In order to solve these problems, methods such as vernier method, multi-chain average topology, WaveUnion architecture and bin-to-bin calibration have been proposed.

[0006] Although these methods can improve the performance of the TDC in some aspects, they often introduce other problems. For example, the vernier method can greatly alleviate the non-linear defects of the device itself, improve the time resolution, and even exceed the inherent time delay of the delay cell, but the vernier method requires more logic resources and longer conversion rate. The multi-chain average topology does not improve the dead time, but compared with the vernier method, it occupies more resources. The WaveUnion method saves resources, but requires a complex ring oscillator design, and its performance depends on the non-uniformity between the delay cells. However, with the improvement of semiconductor manufacturing processes, this non-uniformity is not serious at present. The bin-to-bin calibration method can only alleviate the non-linear problems of the delay cell, and its scalability is poor, and it needs to be reprocessed when the channel position is changed or the hardware platform is replaced.

[0007] The TDC design using Application-Specific Integrated Circuit (ASIC) can significantly solve the above problems. Although these ASIC-oriented solutions can usually achieve satisfactory performance, they require high manufacturing costs and long design cycles on the one hand, so the technical iteration is slow and the development speed is greatly limited; on the other hand, they cannot be reused, resulting in poor flexibility. Therefore, only experienced and resource-rich groups have the strength to choose ASIC-based solutions. This phenomenon may inhibit the pace of innovation to some extent, so many TDC designs often use FPGAs for verification first, and then use ASICS for mass stream.

[0008] Traditional TDCs usually connect delay units in a straight line. For example, a TDC implemented on an FPGA is connected by the carry units of the FPGA as delay units. In order to ensure that the resources on the TDC chain can completely interpolate the system clock, the inherent delay of the entire delay chain must be greater than the clock period of the counter, which is often referred to as the clock condition. The delay generated by the entire delay chain is determined by the inherent delay of each delay unit and the number of delay units. Therefore, when the precision of the delay unit is high, the number of delay units must be large, which will cause the traditional single-chain TDC to be very long on the FPGA, and the following technical problems will be caused:

[0009] (1) Poor linearity. An ideal TDC requires that the transmission delay between each delay unit be the same to ensure high linearity. However, in practice, only delay units within the same resource block can ensure good consistency. Delay units between different resource blocks have large differences in wiring resources, resulting in serious nonlinearity problems.

[0010] (2) Large error. When the TDC chain is too long, it will cause the "bubble" problem, that is, when a signal passes through a chain, all the delay units it passes through will be triggered in theory, that is, the output should be all "1" (or "0" instead). However, when the chain is long, there may be many "0"s in the "1" trigger section, which will seriously interfere with the measurement results of the TDC.

[0011] (3) Poor robustness. The inherent delay time of the delay unit is greatly affected by temperature changes. When the temperature changes greatly, not only will the linearity of the delay unit in the chain be affected, but the inherent delay of the entire chain will also be shifted, causing errors in measurement.

[0012] Through the above analysis, the problems and defects of the prior art are:

[0013] (1) The existing TDC analog scheme needs to use analog quantities in implementation, and analog quantities are easily affected by signal fluctuations. At the same time, the single measurement time of the existing TDC analog scheme is often much longer than the time interval to be measured, that is, the conversion rate is longer, which will cause the dead time to be too long and unable to perform high-frequency measurement.

[0014] (2) The existing Vernier method requires more logic resources and a longer conversion rate, and the multi-chain average topology will occupy more resources. The WaveUnion method requires a complex ring oscillator design, and its performance depends on the non-uniformity between delay units. The bin-to-bin calibration method can only alleviate the nonlinearity problem of delay units, and has poor scalability. When the channel position is changed or the hardware platform is replaced, it needs to be reprocessed.

[0015] (3) In the existing TDC digital scheme, the characteristics of the delay unit are easily affected by the inherent defects of the device, power and temperature dynamic changes, etc., resulting in serious nonlinearity problems; at the same time, the inherent delay of each delay unit is determined by its manufacturing process and cannot be modified.

[0016] (4) The existing ASIC-oriented solution requires high manufacturing cost and long design cycle, slow technical iteration, and greatly limited development speed; cannot be reused, resulting in poor flexibility and inhibiting the pace of innovation; and the traditional TDC has the problems of poor linearity, large error and poor robustness. SUMMARY

[0017] In view of the problems existing in the prior art, the present application provides a segmented time-to-digital converter, a control method, a medium, an equipment and a terminal.

[0018] The present application is implemented as follows: a control method of a segmented time-to-digital converter, the control method of the segmented time-to-digital converter comprising: changing the structure of the delay chain, using multiple short parallel chains to measure the "fine" time of the signal to be measured in the TDL TDC; and introducing different fixed delay processing in front of each short chain to essentially measure different intervals of the signal to be measured by each short chain.

[0019] Further, the number of chain lengths is determined according to the clock condition and the measurement interval of each chain.

[0020] Further, the control method of the segmented time-to-digital converter further comprises:

[0021] In the "fine" time measurement of the signal to be measured using multiple parallel short chains, chain 1 is connected to the signal to be measured, and the front of chain 1 and chain 2 is connected to a delay unit for generating a fixed delay time, wherein the delay time Δt d2 configured in front of chain 2 delay unit is longer than the delay time Δt d1 caused by the delay unit in chain 1, Δt d2 > Δt d1 .

[0022] Further, the delay unit in front of the chain and the delay unit in the chain are two different logical resources;

[0023] Wherein, the delay unit in front of the chain is a single or multiple delay units configured by software, which is an IDelay resource in Xilinx FPGA; and the delay unit in the chain adopts a CARRY4 / 8 resource.

[0024] Further, the measurement range Mτ of chain 1 and the delay time generated by the delay units in front of the two chains satisfy the condition Mτ> Δtd2 -Δt d1 wherein M is the number of delay units, and τ is the fixed delay time of each delay unit. The measurement range of chain 2 is the same as that of chain 1, and the total measurement time of chain 1 and chain 2 is 2Mτ, which satisfies the clock condition 2Mτ>T.

[0025] Further, when a signal with a time interval of Δt is input, if Δt d2 -Δt d1 d2 -Δt d1 ); when Δt>T, the measurement is divided into two parts, one part is the integer part of the system clock, and the other part is the decimal part of the system clock; the integer part is realized by the counting function, and the decimal part is measured by using multiple parallel short chains.

[0026] Another object of the present application is to provide a segmented time-to-digital converter applying the control method of the segmented time-to-digital converter, which comprises multiple short chains and delay units connected in front of the short chains, and the delay units are used to generate fixed delay time; the "fine" time of the signal to be measured in the TDL TDC is measured by using multiple short chains; by introducing different fixed delay processes in front of each short chain, each short chain essentially measures different intervals of the signal to be measured in parallel.

[0027] Another object of the present application is to provide a computer device, which comprises a memory and a processor, and the memory stores a computer program, and the computer program is executed by the processor to make the processor execute the steps of the control method of the segmented time-to-digital converter.

[0028] Another object of the present application is to provide a computer readable storage medium, which stores a computer program, and the computer program is executed by the processor to make the processor execute the steps of the control method of the segmented time-to-digital converter.

[0029] Another object of the present application is to provide an information data processing terminal, which is used to realize the segmented time-to-digital converter.

[0030] ​In combination with the above technical solutions and the technical problems solved, the technical solutions to be protected by the present application have the following advantages and positive effects:

[0031] First, in view of the technical problems existing in the prior art and the difficulty in solving the problems, the technical solutions to be protected by the present application and the results and data obtained during the research and development are combined to analyze in detail and profoundly how the technical solutions solve the technical problems and bring some creative technical effects after solving the problems. The specific description is as follows:

[0032] 1. Good linearity. The control method of the segmented time-to-digital converter proposed in the present application ingeniously places all the delay units in one logic block through "folding" of the whole long chain, which completely avoids the nonlinearity problem caused by the inconsistent line length of multiple resource blocks.

[0033] 2. Simple structure and high resource utilization. The segmented time-to-digital converter of the present application has a simple structure and only needs fixed delay units and multiple short chains placed in one logic resource block. The fixed delay units can be more compact in layout due to their shorter chain length, and they waste less layout space. On the contrary, long chain resources are inherently scarce, and when long chains are laid out in a limited space, the unused part may not be able to accommodate another long chain. This is similar to memory allocation in a computer system, where long chains are equivalent to large blocks of continuous free memory, and short chains are equivalent to small pieces of free memory distributed in different spaces. Large blocks of continuous memory are well-known scarce resources, and they are very limited. Small pieces of free memory are more abundant, and if they can be used to form large blocks of free memory, the resource utilization will be higher.

[0034] 3. Good robustness, not sensitive to device and channel changes, and can correct the drift caused by temperature. During the manufacturing process of a device, resources with similar spatial positions have better similarity, i.e., better consistency. This property still holds when the device or channel changes. Therefore, the TDC of the present application, which is based on resources with similar spatial positions, has better consistency in the time delay of each delay unit. When the device or channel changes, the consistency of these delay units will not be destroyed, so the TDC of the present application has better robustness. In addition, the logic resources in the present application that require configurable delay time, such as IDELAY in Xilinx FPGA, are often insensitive to temperature changes. By using these insensitive resources and multiple short chains, a differential measurement unit can be formed. In combination with a pulse signal with known time (which can be easily provided by a PLL in FPGA), the number of delay units triggered under different temperature conditions can be measured, so that the inherent delay time of a single delay unit under different temperature conditions can be obtained, and the impact of temperature can be compensated.

[0035] Second, considering the technical solution as a whole or from a product perspective, the technical effects and advantages of the technical solution to be protected by this invention are specifically described as follows:

[0036] (1) Technical effect: The experimental results of TDC in code density test show that the segmented time-to-digital converter structure proposed in this invention has significantly better INL and DNL than the traditional structure; and both INL and DNL are lower than 0.5 LSB, while the traditional scheme is as high as 1.5 LSB; the smaller INL and DNL are, the better the linearity and the better the performance.

[0037] (2) Technical advantages: As a time measurement tool, TDC needs to ensure the accuracy of the measurement. The factors affecting its accuracy mainly include its own resolution and linearity. The high linearity of this invention can effectively improve the accuracy of TDC measurement.

[0038] Third, as supplementary evidence of the inventive step of the claims of this invention, it is also reflected in the following important aspects:

[0039] (1) The technical solution of this invention fills a technological gap in the domestic and international industry: traditional time-to-digital converters suffer from poor linearity, poor robustness, complex structure, and low resource utilization. To solve the problems of linearity and time resolution, either more resources need to be introduced, resulting in low resource utilization and increased structural complexity; or a lot of work needs to be done for calibration, resulting in extremely poor robustness. Although there is an improvement in performance, these additional costs often deter people, especially in multi-channel scenarios, making it difficult to promote. The segmented time-to-digital converter provided by this invention fills the gap in the existing technology.

[0040] (2) The technical solution of the present invention solves the technical problem that people have been eager to solve but have never been able to succeed in: there are methods that have been trying to solve the nonlinear problem in TDC, but in order to solve the nonlinear problem, too much time or resource cost is introduced. The TDC structure proposed in the present invention can perfectly solve the nonlinear problem without consuming more resources and without calibration (i.e. without additional time and computation costs). Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1This is a flowchart of the control method for a segmented time-to-digital converter provided in an embodiment of the present invention;

[0043] Figure 2 This is a basic schematic diagram of the principle of using multiple parallel short chains to perform "fine" time measurement of the signal under test, provided by an embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of the "fine" time measurement part provided in an embodiment of the present invention;

[0045] Figure 4A This is an experimental result diagram of TDC in code density testing provided by an embodiment of the present invention;

[0046] Figure 4B This is an experimental result diagram of TDC in DNL testing provided by an embodiment of the present invention;

[0047] Figure 4C This is an experimental result diagram of TDC in INL testing provided by an embodiment of the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0049] To address the problems existing in the prior art, the present invention provides a segmented time-to-digital converter, a control method, a medium, a device, and a terminal. The present invention will be described in detail below with reference to the accompanying drawings.

[0050] like Figure 1 As shown, the control method for a segmented time-to-digital converter provided in this embodiment of the invention includes the following steps:

[0051] S101, change the structure of the delay chain and use multiple short parallel chains to measure the "fine" time of the signal under test in TDL TDC;

[0052] S102, by introducing different fixed delay processing before each short chain, so that each short chain is essentially used to perform parallel measurement of different intervals of the signal to be measured.

[0053] The core idea of ​​this invention is to modify the structure of the delay chain and utilize multiple short parallel chains to measure the "fine" time in TDL and TDC. Because the delay time caused by the short chains is short, a single short chain cannot meet the clock conditions. Therefore, by introducing different fixed delays before each short chain, the purpose is to enable each short chain to perform parallel measurements on different intervals of the signal under test. Here, we use two short chains as a model to illustrate the basic measurement process. In actual implementation, more than two short chains may be needed. The specific chain length required depends on the clock conditions and the range that each chain can measure.

[0054] like Figure 2 The diagram shown illustrates the basic principle of this invention: utilizing multiple parallel short chains to perform "fine" time measurements on the signal under test. Figure 2 In the diagram, chain 1 is directly connected to the signal under test. Both chain 1 and chain 2 are preceded by a delay unit, which is used to generate a fixed delay time. The delay time Δt configured in the delay unit before chain 2 is... d2 It is longer than the delay time Δt caused by the delay unit in chain 1. d1 That is, Δt d2 >Δt d1 Note that the delay units at the beginning of the chain and the delay units in the chain are two different logical resources. The delay units at the beginning of the chain are single or multiple delay units that can be configured in software; for example, in a Xilinx FPGA, they can be IDELAY resources. The delay units in the chain, on the other hand, often use CARRY4 / 8 resources.

[0055] At the same time, the measurement range Mτ of chain 1 and the delay time generated by the delay units of the two chains should satisfy Mτ > Δt. d2 -Δt d1 Where M is the number of delay units, and τ is the fixed delay time for each unit. For simplicity, the measurement range of chain 2 can be the same as that of chain 1. The combined measurement time of chains 1 and 2, i.e., 2Mτ, should satisfy the clock condition, i.e., 2Mτ > T.

[0056] When a signal with a time interval of Δt is input, if Δt < Mτ, then any chain can complete the measurement of the signal to be measured. In this case, it is only necessary to count the number of triggered delay units on the chain, let's say N, then the signal to be measured is Δt = Nτ. If the time interval to be measured is T > Δt >= Mτ, then the measurement process requires two chains to work together, where T is the system clock.

[0057] In this case, the first chain measures the Mτ portion, while the other chain is assumed to measure the M'τ. Therefore, the final measurement result is (M+M')τ-(Mτ-(Δt)). d2 -Δt d1 ))=M'τ+(Δtd2 -Δt d1 When Δt > T, the measurement can be divided into two parts: the integer part of the system clock and the fractional part. The integer part can be measured using a counting function, while the fractional part can be measured using multiple parallel short chains.

[0058] The segmented time-to-digital converter provided in this embodiment of the invention includes multiple short chains and delay units connected in front of the short chains. The delay units are used to generate fixed delay times. The multiple short chains are used to measure the "fine" time of the signal under test in the TDL TDC. By introducing different fixed delay processing in front of each short chain, the purpose is to make each short chain essentially perform parallel measurement of different intervals of the signal under test.

[0059] This invention can be applied to various fields, such as nuclear physics, automotive, and medical imaging. In nuclear physics, for example, high-energy particle tracking requires accurate measurement of particle flight time, and the high linearity of this invention can significantly improve measurement accuracy. In automotive, where radar is used to detect vehicle information, this invention can improve detection accuracy. In medical imaging, such as PET, where PET detectors are needed to accurately measure the flight time of gamma photons, the high linearity of this invention can significantly improve the accuracy of gamma photon flight time measurement. Furthermore, since PET detectors have dozens of signal readout channels, dozens of TDCs need to be integrated, and the high resource utilization and robustness of this invention can significantly reduce the difficulty of multi-channel TDC integration.

[0060] The embodiments of the present invention have achieved some positive results during the research and development or use process, and have indeed great advantages compared with the prior art. The following content describes them in conjunction with the data, charts and other information of the experimental process.

[0061] The specific implementation process of this invention is described using a Xilinx Ultrascale FPGA as an example. The measurement principle of the TDC of this invention is essentially the same as that of the TDL TDC, that is, "coarse" time is measured through the system clock, and "fine" time is measured through the delay chain resources. The innovation of this invention lies in the creative update of the measurement structure of "fine" time. Therefore, only the measurement implementation process of "fine" time will be described here.

[0062] like Figure 3The diagram shows the system implementation schematic. The entire system consists of 6 IDELAY units and 120 CARRY8 units forming parallel short chains. The IDELAY units employ a clustered hierarchical structure, and the delay time of each cluster is marked in the diagram. The 120 CARRY8 units form 4 short chains, each with a delay time of approximately 30 ps, ​​thus the measurement range of each short chain is only 900 ps. The above settings satisfy the clock conditions: 600 - 0 < 900, 1200 - 600 < 900, 1800 - 1200 < 900, 120 * 30 = 3600 ps > T = 2.5 ns, i.e., a 400 MHz system clock. During operation, the time interval to be measured can be obtained by detecting the trigger status on each chain. Let the delays caused by the delay units before each chain from top to bottom be ΔT1, ΔT2, ΔT3, and ΔT4, respectively. Let the inherent delay of the delay units on each short chain be τ, and let the number of delay units on each chain be M. Then the measurement process for the "fine" time is as follows:

[0063] (1) Detect the positions of the "01" transition edges (rising edge, signal tail) and the "10" transition edges (falling edge, signal start) on each short chain, and let their positions be P. 01 ,P 10 The positions of these two signals on the chain are C and C, respectively. 01 C 10 , where ≤1P 01 ,P 10 ≤30, 1≤C 01 C 10 ≤4.

[0064] (2) Determine the number of system clock cycles N between the "01" transition edge and the "10" transition edge. 01 N 10 .

[0065] (3) If N 01 =N 10 We will discuss two cases: when C 01 =C 10 At that time, Δt=(P 10 -P 01 )τ;When C 01 ≠C 10 ,

[0066] (4) If N 01 ≠N 10 ,but

[0067] The experimental results of the TDC provided in the embodiments of the present invention in code density testing are as follows: Figures 4A-4BAs shown, the light gray portion represents the code density test results of the TDC proposed in this invention, while the dark gray portion represents the test results of the traditional structure. Figures 4A-4B As can be seen, the structure proposed in this invention has significantly better INL and DNL than the traditional structure. Under the structure proposed in this invention, both INL and DNL are below 0.5 LSB, while the traditional scheme is as high as 1.5 LSB; the smaller the INL and DNL, ​​the better the linearity and the superior the performance.

[0068] Figure 3 In this context, Input represents the input signal; IODELAY unit represents a delay unit that introduces a fixed delay, where IODELAY is the name of the resource used during instantiation; similarly, CARRY8 unit is a delay unit for performing subdivision measurements, and CARRY8 is the name of the resource used during instantiation.

[0069] It should be noted that embodiments of the present invention can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of the above-described hardware circuitry and software, such as firmware.

[0070] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A control method for a segmented time-to-digital converter, characterized in that, The control method for segmented time-to-digital converters includes: changing the structure of the delay chain to measure the "fine" time of the signal under test in the TDL TDC using multiple short parallel chains; and introducing different fixed delay processing before each short chain so that each short chain can essentially measure different intervals of the signal under test in parallel. The control methods for segmented time-to-digital converters also include: In the fine-tuning time measurement of the signal under test using multiple parallel short chains, chain 1 is connected to the signal under test. Both chain 1 and chain 2 are preceded by delay units to generate a fixed delay time. The delay unit preceding chain 2 is configured with a specific delay time. Longer than the delay time caused by the delay unit in chain 1 , ; The delay unit before the chain and the delay unit in the chain are two different logical resources; The delay units before the chain are one or more delay units configured in software, which are IDELAY resources in Xilinx FPGAs; while the delay units in the chain use CARRY4 / 8 resources. Measurement range of chain 1 The delay time generated by the delay units of the two chains satisfies the condition. ,in The number of delay units. A fixed delay time is assigned to each delay unit; the measurement range of chain 2 is the same as that of chain 1, and the total measurement time of chains 1 and 2 is... The clock condition is satisfied. ; When the time interval is When the signal is input, if If any chain can complete the measurement of the signal to be measured, then only the number of triggered delay units on the chain is counted; when the number is N, the signal to be measured is... If the time interval to be measured The measurement process is completed using two chains working together, where T is the system clock cycle; the measurement is performed by the first chain. Part of it, while the measurement results for the other chain are... The final measurement result is ;when The measurement is divided into the integer part and the fractional part of the system clock. The integer part of the system clock is measured through a counting function, while the fractional part of the system clock is measured using multiple parallel short chains.

2. The control method for the segmented time-to-digital converter as described in claim 1, characterized in that, The number of chains is determined based on clock conditions and the measurement range of each chain.

3. A segmented time-to-digital converter employing the control method of the segmented time-to-digital converter as described in any one of claims 1 to 2, characterized in that, The segmented time-to-digital converter includes multiple short chains and delay units connected before the short chains. The delay units are used to generate a fixed delay time. The "fine" time of the signal under test in the TDL TDC is measured using multiple short chains. By introducing different fixed delays before each short chain, the purpose is to enable each short chain to perform parallel measurements on different intervals of the signal under test.

4. A computer device, characterized in that, The computer device includes a memory and a processor. The memory stores a computer program, which, when executed by the processor, causes the processor to perform the steps of the control method for the segmented time-to-digital converter as described in any one of claims 1 to 2.

5. A computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the control method for a segmented time-to-digital converter as described in any one of claims 1 to 2.

6. An information data processing terminal, characterized in that, The information data processing terminal is used to implement the segmented time-to-digital converter as described in claim 3.

Images