Voltage stabilizer, chip and electronic device

Abstract

The application discloses a voltage stabilizer, a chip and an electronic device. The voltage stabilizer comprises an error amplifier circuit, a pole compensation circuit, a power tube, a resistance feedback network and a compensation capacitor. The resistance feedback network is used for sampling an output voltage of a voltage stabilizing output end, adjusting the sampled voltage, and outputting a feedback voltage to a negative input end of the error amplifier circuit. The error amplifier circuit is used for amplifying a difference between a reference voltage and the feedback voltage, so that the reference voltage and the feedback voltage are equal, and the error amplifier circuit output becomes a main pole in cooperation with the compensation capacitor. The pole compensation circuit is used for weakening an output impedance corresponding to the voltage stabilizing output end, so that an output pole becomes a secondary pole. A drain of the power tube is used as the voltage stabilizing output end for voltage stabilizing output. The application can improve the robustness of the voltage stabilizer.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a voltage regulator, chip, and electronic device. Background Technology

[0002] Low dropout linear regulators (LDOs) are key modules in power management chips. They can filter out "dirty" power supplies with noise ripples of different frequencies and convert them into a "clean" and "stable" voltage that can power the digital modules inside the chip. In order to overcome the robustness problem caused by changes in the size of the output capacitor, the regulator usually needs to implement a low dropout linear regulator circuit that is compatible with different output capacitors.

[0003] Some solutions improve PSRR performance by keeping the gate (G) and source (S) voltages of the PMOS power transistor in the regulator constant, and adjust the zero point of the zero-point generator capacitor to eliminate the second pole in the corresponding system, thereby enhancing system stability. These solutions use the output capacitor for simple frequency compensation and place the main pole at the output terminal. However, the influence of capacitance deviation caused by inconsistent output capacitor quality and load current changes on the output pole can make the regulator system unstable and have low robustness. Summary of the Invention

[0004] In view of this, this application provides a voltage regulator, chip, and electronic device to solve the problem that traditional solutions easily lead to instability and low robustness of the voltage regulator system.

[0005] This application provides a voltage regulator, including an error amplifier circuit, a pole compensation circuit, a power transistor, a resistor feedback network, and a compensation capacitor;

[0006] The positive input terminal of the error amplifier circuit is used to connect to the reference voltage, the negative input terminal is connected to the output terminal of the resistor feedback network, the output terminal is connected to the first input terminal of the pole compensation circuit and grounded through the compensation capacitor, the second input terminal of the pole compensation circuit is connected to the gate of the power transistor, and the output terminal is connected to the regulated output terminal. The source of the power transistor is used to connect to an external power supply, the drain is connected to the regulated output terminal, and the sampling terminal of the resistor feedback network is connected to the regulated output terminal.

[0007] The resistor feedback network is used to sample the output voltage of the regulated output terminal, adjust the sampled voltage, and output a feedback voltage to the negative input terminal of the error amplifier circuit.

[0008] The error amplifier circuit is used to amplify the difference between the reference voltage and the feedback voltage, so that the reference voltage and the feedback voltage are equal, and in conjunction with the compensation capacitor, the output of the error amplifier circuit becomes the dominant pole.

[0009] The pole compensation circuit is used to weaken the output impedance corresponding to the regulated output terminal so as to make the output pole a secondary pole.

[0010] The drain of the power transistor serves as the regulated output terminal for regulated output.

[0011] Optionally, the error amplifier circuit includes a folded common-source cascode operational amplifier.

[0012] Optionally, the folded common-source common-gate operational amplifier includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, and a first current source; the gate of the first MOSFET is used to connect to the reference voltage, the drain is connected to the drain of the third MOSFET and the source of the fifth MOSFET, the source is connected to the source of the second MOSFET and grounded through the first current source, the gate of the second MOSFET is used to connect to the feedback voltage, the drain is connected to the drain of the fourth MOSFET and the source of the sixth MOSFET, and the gate of the third MOSFET is connected to the fourth MOSFET. The gate and source of the MOSFET are connected to the regulated output terminal. The source of the fourth MOSFET is connected to the regulated output terminal. The gate of the fifth MOSFET is connected to the gate of the sixth MOSFET. The drain of the fifth MOSFET is connected to the drain of the seventh MOSFET, the gate of the ninth MOSFET, and the gate of the tenth MOSFET. The drain of the sixth MOSFET is connected to the source of the eighth MOSFET and the first terminal of the compensation capacitor. The gate of the seventh MOSFET is connected to the gate of the eighth MOSFET, and the source of the seventh MOSFET is connected to the drain of the ninth MOSFET. The source of the eighth MOSFET is connected to the drain of the tenth MOSFET. The source of the ninth MOSFET is connected to the source of the tenth MOSFET and ground.

[0013] Optionally, the error amplifier circuit includes an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, and a second current source; the gate of the eleventh MOSFET is used to connect to the reference voltage, the drain is connected to the drain of the thirteenth MOSFET, the gate of the thirteenth MOSFET, and the gate of the fourteenth MOSFET, respectively, the source is connected to the source of the twelfth MOSFET, and grounded through the second current source, the gate of the twelfth MOSFET is used to connect to the feedback voltage, the drain is connected to the drain of the fourteenth MOSFET and the first terminal of the compensation capacitor, the source of the thirteenth MOSFET is connected to the regulated output terminal, and the source of the fourteenth MOSFET is connected to the regulated output terminal.

[0014] Optionally, the pole compensation circuit includes a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, an eighteenth MOSFET, a first resistor, and a third current source; the gate of the fifteenth MOSFET is connected to the first terminal of the compensation capacitor, the source is connected to the regulated output terminal, the drain is connected to the gate of the sixteenth MOSFET and the source of the seventeenth MOSFET, and grounded through the third current source; the source of the sixteenth MOSFET is connected to the regulated output terminal, and the drain is grounded; the gate of the seventeenth MOSFET is used to connect to a first preset voltage, and the drain is connected to the drain of the eighteenth MOSFET, the gate of the eighteenth MOSFET, and the gate of the power transistor; the source of the eighteenth MOSFET is connected to the external power supply; and the first resistor is connected between the external power supply and the gate of the eighteenth MOSFET.

[0015] Optionally, the expression for the output pole includes: P(D)≈gm1*gmp*R0 / CL; where P(D) represents the output pole, gm1 represents the transconductance of the fifteenth MOS transistor, gmp represents the transconductance of the power transistor, R0 represents the resistance value of the first resistor, and CL represents the load capacitance.

[0016] Optionally, the pole compensation circuit further includes a nineteenth MOS transistor; the gate of the nineteenth MOS transistor is used to connect to a second preset voltage, the source is connected to the gate of the fifteenth MOS transistor, the drain is connected to the gate of the sixteenth MOS transistor and the source of the seventeenth MOS transistor respectively, and is grounded through the third current source.

[0017] Optionally, the expression for the output pole includes: P(D)≈gm2*gmp*R0 / CL; where P(D) represents the output pole, gm2 represents the transconductance of the fifteenth MOSFET and the nineteenth MOSFET, gmp represents the transconductance of the power transistor, R0 represents the resistance value of the first resistor, and CL represents the load capacitance.

[0018] Optionally, the resistor feedback network includes a second resistor and a third resistor; the first end of the third resistor is connected to the regulated output terminal, and the second end is grounded through the second resistor, and is also used to provide the feedback voltage.

[0019] Optionally, the voltage regulator further includes an external load unit; the external load unit is connected between the regulated output terminal and the ground terminal; the external load unit is used to simulate actual load scenarios.

[0020] Optionally, the off-chip load unit includes a load capacitor and a fourth resistor; the load capacitor and the fourth resistor are connected in parallel between the regulated output terminal and the ground terminal.

[0021] This application also provides a chip including any of the above-mentioned voltage regulators.

[0022] This application also provides an electronic device, including any of the above-described voltage regulators or any of the above-described chips.

[0023] In the voltage regulator, chip, and electronic device provided in this application, the resistor feedback network can adjust the output voltage and output a feedback voltage to the negative input terminal of the error amplifier circuit, so that the reference voltage VREF connected to the error amplifier circuit and the feedback voltage VFB are equal. Combined with the compensation capacitor Cc, the output of the error amplifier circuit becomes the dominant pole. The pole compensation circuit weakens the output impedance and makes the output pole a secondary pole, thereby pushing the output pole away from the origin, so that the voltage regulator has strong robustness under different load capacitances. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a voltage regulator structure according to an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of a voltage regulator structure according to another embodiment of this application;

[0027] Figure 3 This is a schematic diagram of a voltage regulator structure according to another embodiment of this application;

[0028] Figure 4 This is a schematic diagram of a voltage regulator structure according to another embodiment of this application;

[0029] Figure 5 This is a schematic diagram of an equivalent model of an embodiment of this application;

[0030] Figure 6 This is a simulation analysis diagram of an embodiment of this application;

[0031] Figure 7 This is a schematic diagram of a voltage regulator structure according to another embodiment of this application;

[0032] Figure 8 This is a schematic diagram of a voltage regulator structure according to another embodiment of this application. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0034] The first aspect of this application provides a voltage regulator, as referenced... Figure 1 As shown, the voltage regulator includes an error amplifier circuit 110, a pole compensation circuit 120, a power transistor Mp, a resistor feedback network 130, and a compensation capacitor Cc. The positive input terminal of the error amplifier circuit 110 is connected to a reference voltage VREF, the negative input terminal of the error amplifier circuit 110 is connected to the output terminal of the resistor feedback network 130, and the output terminal of the error amplifier circuit 110 is connected to the first input terminal of the pole compensation circuit 120. The output terminal of the error amplifier circuit 110 is also grounded through the compensation capacitor Cc. The second input terminal of the pole compensation circuit 120 is connected to the gate of the power transistor Mp, and the output terminal of the pole compensation circuit 120 is connected to the regulated output terminal. The source of the power transistor Mp is connected to an external power supply VDD, and the drain of the power transistor Mp is connected to the regulated output terminal. The sampling terminal of the resistor feedback network 120 is connected to the regulated output terminal.

[0035] The resistor feedback network 130 is used to sample the output voltage VOUT of the regulated output terminal, adjust the sampled voltage, and output a feedback voltage VFB to the negative input terminal of the error amplifier circuit 110. Specifically, the resistor feedback network 130 can adjust the output voltage VOUT by weighting it according to a certain feedback coefficient to obtain the feedback voltage VFB. Optionally, the feedback coefficient includes a weighting coefficient that makes the reference voltage VREF and the feedback voltage VFB equal.

[0036] The error amplifier circuit 110 is used to amplify the difference between the reference voltage VREF and the feedback voltage VFB. The output voltage VOUT is adjusted through the negative feedback loop formed by the resistor feedback network 130 so that the reference voltage VREF and the feedback voltage VFB are equal. In conjunction with the compensation capacitor Cc, the output of the error amplifier circuit 110 becomes the dominant pole, so that the dominant pole is located inside the loop.

[0037] The pole compensation circuit 120 is used to weaken the output impedance corresponding to the regulated output terminal, so as to make the output pole a secondary pole. Furthermore, by weakening the output impedance, the pole compensation circuit 120 can push the output pole away from the origin, so that the dominant pole is located inside the loop, making the regulator have strong robustness under different load capacitances.

[0038] The drain of the power transistor Mp serves as the regulated output terminal for voltage regulation. Specifically, the power transistor Mp is a P-type power transistor. During the operation of the voltage regulator, the drain output voltage VOUT of this P-type power transistor can be used as the power supply for the error amplifier circuit 110 and the pole compensation circuit 120.

[0039] Specifically, the error amplifier circuit 110 can use a high output impedance amplifier, in conjunction with a compensation capacitor Cc, so that the output of the error amplifier circuit 110 becomes the main pole of the loop. By designing the feedback coefficient and other loop parameters of the resistor feedback network 130, the corresponding loop of the regulator has high stability when the load capacitance CL=1uF. When the load capacitance is smaller than the nominal value or the load current of the loop increases, the pole compensation circuit 120 weakens the output impedance, causing the output pole to move away from the origin, which can improve the loop stability. Thus, the regulator has strong robustness under different load capacitance conditions.

[0040] In the aforementioned voltage regulator, the resistor feedback network 130 can adjust the output voltage VOUT and output a feedback voltage VFB to the negative input terminal of the error amplifier circuit 110, making the reference voltage VREF connected to the error amplifier circuit 110 equal to the feedback voltage VFB. Combined with the compensation capacitor Cc, this makes the output of the error amplifier circuit 110 a dominant pole. The pole compensation circuit 120 weakens the output impedance, making the output pole a secondary pole, thereby pushing the output pole away from the origin. This makes the voltage regulator robust under different load capacitances.

[0041] In one embodiment, reference Figure 2 As shown, the voltage regulator also includes an external load unit 140; the external load unit 140 is connected between the regulated output terminal and the ground terminal; the external load unit 140 is used to simulate actual load scenarios so that the operation of the voltage regulator is more in line with the actual working scenario, and further improves the stability of the voltage regulator during operation.

[0042] In one example, the off-chip load unit 140 includes a load capacitor CL and a fourth resistor RL; the load capacitor CL and the fourth resistor RL are connected in parallel between the regulated output terminal and the ground terminal. Specifically, the first end of the load capacitor CL is connected to the regulated output terminal and the second end is grounded, and the first end of the fourth resistor RL is connected to the regulated output terminal and the second end is grounded.

[0043] In one embodiment, the error amplifier circuit 110 includes a folded common-source cascode operational amplifier, which can improve the output impedance at point A of the output terminal of the error amplifier circuit 110, and at the same time, with the help of the compensation capacitor Cc, the dominant pole is designed at point A of the output terminal of the error amplifier circuit 110.

[0044] In one example, refer to Figure 3 As shown, the folded common-source common-gate operational amplifier includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, and a first current source I1. The gate of the first MOSFET M1 is connected to the reference voltage VREF, its drain is connected to the drain of the third MOSFET M3 and the source of the fifth MOSFET M5, and its source is connected to the source of the second MOSFET M2, and grounded through the first current source I1. The gate of the second MOSFET M2 is connected to the feedback voltage VFB, and its drain is connected to the drain of the fourth MOSFET M4 and the source of the sixth MOSFET M6. The gate of the third MOSFET M3 is connected to the gate of the fourth MOSFET M4, and its source is connected to the regulated output terminal. The source of the fourth MOSFET M4 is connected to the regulated output terminal. The gate of the fifth MOSFET M5 is connected to... The gate and drain of the sixth MOSFET M6 are connected to the drain of the seventh MOSFET M7, the gate of the ninth MOSFET M9, and the gate of the tenth MOSFET M10, respectively. The drain of the sixth MOSFET M6 is connected to the source of the eighth MOSFET M8 and the first terminal of the compensation capacitor Cc, with the second terminal of the compensation capacitor Cc grounded. The gate of the seventh MOSFET M7 is connected to the gate of the eighth MOSFET M8, and its source is connected to the drain of the ninth MOSFET M9. The source of the eighth MOSFET M8 is connected to the drain of the tenth MOSFET M10, and the source of the ninth MOSFET M9 is connected to the source of the tenth MOSFET M10 and ground.

[0045] Optionally, the first MOSFET M1, the second MOSFET M2, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10 can all be NMOS transistors. The third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6 can all be PMOS transistors.

[0046] In one embodiment, the error amplifier circuit 110 includes a five-transistor operational amplifier with N input pairs. It can adopt a relatively simple structure to provide a high output impedance at point A of the output terminal of the error amplifier circuit 110, so as to cooperate with the compensation capacitor Cc to design the dominant pole at point A.

[0047] Specifically, refer to Figure 4As shown, the error amplifier circuit 110 (i.e., a five-transistor operational amplifier with an N-input pair) includes an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, a fourteenth MOSFET M14, and a second current source I2. The gate of the eleventh MOSFET M11 is connected to the reference voltage VREF, its drain is connected to the drain of the thirteenth MOSFET M13, its gate, and the gate of the fourteenth MOSFET M14, and its source is connected to the source of the twelfth MOSFET M12 and grounded through the second current source I2. The gate of the twelfth MOSFET M12 is connected to the feedback voltage VFB, and its drain is connected to the drain of the fourteenth MOSFET M14 and the first terminal of the compensation capacitor Cc. The source of the thirteenth MOSFET M13 is connected to the regulated output terminal, and the source of the fourteenth MOSFET M14 is also connected to the regulated output terminal.

[0048] Optionally, the eleventh MOSFET M11 and the twelfth MOSFET M12 can be NMOS transistors, respectively. The thirteenth MOSFET M13 and the fourteenth MOSFET M14 can be PMOS transistors, respectively.

[0049] In one embodiment, such as Figure 3 and Figure 4As shown, the pole compensation circuit 120 includes a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, an eighteenth MOSFET M18, a first resistor R0, and a third current source I3. The gate of the fifteenth MOSFET M15 is connected to the first terminal of the compensation capacitor Cc, its source is connected to the regulated output terminal, and its drain is connected to the gate of the sixteenth MOSFET M16 and the source of the seventeenth MOSFET M17, and grounded through the third current source I3. The source of the sixteenth MOSFET M16 is connected to the regulated output terminal, and its drain is grounded. The gate of the seventeenth MOSFET M17 is used to connect to a first preset voltage Vb, and its drain is connected to the drain of the eighteenth MOSFET M18, the gate of the eighteenth MOSFET M18, and the gate of the power transistor Mp. The source of the eighteenth MOSFET M18 is connected to the external power supply VDD. The first resistor R0 is connected between the external power supply VDD and the gate of the eighteenth MOSFET M18. This embodiment uses components such as the fifteenth MOSFET M13, the sixteenth MOSFET M13, the seventeenth MOSFET M13, and the eighteenth MOSFET M13 to implement a pole compensation circuit, which reduces the output impedance at the regulated output terminal D, pushing the output pole away from the origin and making the output pole a secondary point. Furthermore, by designing the feedback coefficient and other loop parameters of the resistor feedback network 130, the loop stability is effectively guaranteed when the load capacitance CL = 1uF. When the actual capacitance of the load capacitor is less than the nominal value or the load current increases, the output pole can move away from the origin, resulting in better loop stability of the regulator and strong robustness under different load capacitances.

[0050] Optionally, the seventeenth MOSFET M17 can be an NMOS transistor. The fifteenth MOSFET M15, the sixteenth MOSFET M16, and the eighteenth MOSFET M18 can each be a PMOS transistor.

[0051] In one example, the resistive feedback network 130 includes a second resistor R1 and a third resistor R2; the first end of the third resistor R2 is connected to the regulated output terminal, the second end is grounded through the second resistor R1, and the second end of the third resistor R2 is also used to provide the feedback voltage VFB. In this example, the feedback coefficient can be adjusted by adjusting the resistance values ​​of the second resistor R1 and the third resistor R2.

[0052] In one example, the expression for the output pole includes: P(D)≈gm1*gmp*R0 / CL; where P(D) represents the output pole, gm1 represents the transconductance of the fifteenth MOSFET, gmp represents the transconductance of the power transistor, R0 represents the resistance of the first resistor, and CL represents the load capacitance. This expression for the output pole indicates that by providing a larger gm1 and R0 through the pole compensation circuit 120, the output pole can be moved away from the origin, thus placing the main pole inside the loop. This achieves the goal of improving the robustness of the loop system by making the secondary pole move away from the origin as CL decreases under different load capacitances.

[0053] Specifically, the expression for the output poles above will be derived and analyzed below. Figure 3 and Figure 4 In the voltage regulator loop shown, the error amplifier circuit 110 contributes a single pole, namely the dominant pole P(A). Ignoring the high-frequency poles at points B and C (point B is located at the gate of the sixteenth MOSFET M16, and point C is located at the gate of the power transistor Mp), the current equation for the regulated output terminal D is:

[0054] (VD-VA)*gm1=i1;

[0055] i1*R0=VC;

[0056] VC*gmp=i2;

[0057] VD / RZ=i2-i1;

[0058] Where: RZ=(1 / sCL) / / (R1+R2), s represents the s-domain variable, CL represents the load capacitance, R1 represents the second resistor, R2 represents the third resistor, the symbol " / / " indicates parallel connection, VD represents the voltage at point D, VA represents the voltage at point A, VC represents the voltage at point C, i1 represents the source current of the fifteenth MOSFET, gm1 represents the transconductance of the fifteenth MOSFET, gmp represents the transconductance of the power transistor, R0 represents the resistance value of the first resistor, and i1 represents the source current of the power transistor Mp.

[0059] By approximating the current equations corresponding to point D above, the transfer function from point A to point D can be obtained. After simplification and approximation, the expression for the output pole P(D) can be obtained: P(D)≈gm1*gmp*R0 / CL.

[0060] The frequency expression corresponding to the output pole is as follows: f(D)=(gm1*gmp*R0) / (2*pi*CL), where pi represents pi. The above expression for the output pole and its frequency expression indicate that by providing a larger gm1 and R0 through the pole compensation circuit 120, the output pole can be moved away from the origin, thereby placing the main pole inside the loop. This achieves the goal of improving the robustness of the loop system by making the secondary pole move away from the origin as CL decreases under different load capacitances.

[0061] The robustness of the above-mentioned voltage regulator loop as a function of the load capacitance CL can be found in Table 1. Table 1 shows that the corresponding loop has high robustness under different load capacitance conditions.

[0062] Table 1

[0063]

[0064] also, Figure 3 The voltage regulator shown achieves a high power supply ripple rejection ratio (PSRR). It utilizes an error amplifier circuit 110 with a folded cascode structure and a common-gate amplifier branch with diode loads (the seventeenth MOSFET M17 and the eighteenth MOSFET M18) to jointly improve the PSRR. Firstly, the equivalent impedance of the eighteenth MOSFET M18 is 1 / gm⁴, a very small value. Therefore, the ripple on the external power supply VDD can be approximately entirely distributed at point C, ensuring that the gate voltage VGS of the power transistor Mp remains constant under power supply ripple interference, thereby improving the circuit's PSRR. Secondly, increasing the gain of the error amplifier circuit 110 can improve the PSRR of the regulator loop.

[0065] right Figure 3 The voltage regulator shown can be modeled equivalently to obtain the following: Figure 5 The equivalent model for PSRR analysis is shown below to facilitate PSRR analysis. Let the open-loop output impedance of the above regulator be Zo, the closed-loop output impedance be Zo_reg, the open-loop gain of the error amplifier circuit 110 be Av, the resistor feedback network 130 be the series connection of the second resistor R1 and the third resistor R2, the output impedance looking downwards from the output be Zo', and the output impedance looking upwards be rds. Then:

[0066] Open-loop output impedance: Zo = Zo' / / rds = {(R1 + R2) / / [1 / (CL*s)] / / RL} / / rds,

[0067] Closed-loop output impedance: Zo_reg = Zo / (1 + βAv), where the feedback coefficient: β = R1 / (R1 + R2).

[0068] The PSRR of a voltage regulator is inversely proportional to (Zo' / / Zo_reg) / (rds+Zo' / / Zo_reg). The smaller (Zo' / / Zo_reg) / (rds+Zo' / / Zo_reg), the larger the PSRR. The following analysis examines the PSRR for different frequency bands:

[0069] (1) Low frequency (0 to -3dB bandwidth)

[0070] At low frequencies, the capacitive reactance of the load capacitor (1 / s*CL) is very large, and the open-loop gain of the error amplifier circuit 110 is very high. Therefore, Zo' is approximately (R1+R2) / / RL, and Zo_reg = Zo' / (1+βAv) is very small. Thus, Zo' / / Zo_reg ≈ Zo_reg, and the PSRR expression at low frequencies is as follows: PSRR1 = VOUT / VDD = ((R1+R2) / / RL / / rds) / (β∙Av∙rds+(R1+R2) / / RL / / rds). At this time, PSRR has the following characteristics: ① The gain of the error amplifier circuit 110 increases as the gain of EA increases; ② The gain increases as the load current increases (RL decreases).

[0071] (2) Mid-to-high frequency (-3dB bandwidth to 10*GBW)

[0072] In the mid-to-high frequency range, the capacitive reactance of the load capacitor 1 / s*CL is very small. Therefore, Zo'≈1 / s*CL=1 / 2pi*f*CL. Thus, the PSRR expression for the mid-to-high frequency range is: PSRR2= VOUT / VDD=1 / (4pi∙f∙CL∙rds). At this point, we have: ① PSRR increases with increasing load capacitance CL; ② Increasing rds, i.e., the smaller the load current, the higher the PSRR.

[0073] (3) Ultra-high frequency (greater than 10*GBW)

[0074] As the frequency continues to increase, the capacitive reactance of the load capacitor can be equivalent to the equivalent series resistance (ESR), so the PSRR expression at higher frequencies is as follows: PSRR3 = VOUT / VDD = ESR / (rds+ESR). At this point, the power supply rejection ratio is mainly determined by the ESR of the load capacitor; the smaller the ESR, the better the PSRR at ultra-high frequencies.

[0075] The above analysis shows that increasing the open-loop gain of the error amplifier circuit 110 and using a diode-connected PSRR enhancement circuit can improve the low-frequency PSRR, using a large load capacitor CL can improve the mid-to-high frequency PSRR, and selecting a load capacitor with a small ESR can improve the high-frequency PSRR. Simulation analysis of the PSRR under various frequency conditions yields the following results. Figure 6 The simulation diagram is shown below. Figure 6The above-mentioned voltage regulator can achieve a high power supply ripple rejection ratio (PSRR) under various frequency conditions. Analysis of the PSRR under different process corner conditions yields the data shown in Table 2. Table 2 characterizes the PSRR improvement effect achievable by the above-mentioned voltage regulator, where TT, SS, FF, FS, and SF represent the models corresponding to the Corner (process corner); specifically, TT represents the typical model, SS represents the slow model, FF represents the fast model, FS represents the fast-slow model, and SF represents the slow-fast model.

[0076]

[0077] In one example, refer to Figure 7 and Figure 8 As shown, the pole compensation circuit also includes a nineteenth MOSFET M0; the nineteenth MOSFET M0 is disposed between the gate of the fifteenth MOSFET M15 and the gate of the sixteenth MOSFET M16. Specifically, the gate of the nineteenth MOSFET M0 is used to connect to the second preset voltage Vb', the source is connected to the gate of the fifteenth MOSFET M15, the drain is connected to the gate of the sixteenth MOSFET M16 and the source of the seventeenth MOSFET M17 respectively, and is grounded through the third current source I3. In this example, the fifteenth MOSFET M15 and the nineteenth MOSFET M0 form a common-source common-gate structure, which can be equivalent to a transconductance much larger than gm1, denoted as gm2. This common-source common-gate structure allows the output impedance at the voltage regulator's regulated output terminal D to be reduced to a greater extent, pushing the output pole away from the origin, making the output pole a secondary point; at the same time, in conjunction with the compensation capacitor Cc, the main pole is designed at the output terminal of the error amplifier circuit 110. Furthermore, the voltage regulator provided in this example has stricter requirements for device threshold voltages, requiring low-threshold devices and a larger loop bandwidth. By designing relevant loop parameters, loop stability can be easily guaranteed when the load capacitance CL = 1uF. When the actual capacitance of the load capacitor is smaller than the nominal value due to different manufacturers, or when the load current increases, the output poles tend to move away from the origin, resulting in better stability. This achieves strong robustness of the low-dropout linear regulator under different load capacitances. Optionally, the nineteenth MOSFET M0 is a PMOS transistor.

[0078] In one example, the expression for the output pole includes: P(D)≈gm2*gmp*R0 / CL; where P(D) represents the output pole, gm2 represents the transconductance shared by the fifteenth and nineteenth MOSFETs, which is much larger than the transconductance gm1 of the fifteenth MOSFET, gmp represents the transconductance of the power transistor, R0 represents the resistance value of the first resistor, and CL represents the load capacitance. In this example, through the pole compensation circuit 120, a larger gm2 and R0 are provided, causing the output pole to move away from the origin. This places the main pole inside the loop, ensuring that under different load capacitances, the secondary pole moves away from the origin as CL decreases, thus improving the robustness of the loop system.

[0079] In the above voltage regulator, the resistor feedback network 130 can adjust the output voltage VOUT and output the feedback voltage VFB to the negative input terminal of the error amplifier circuit 110, so that the reference voltage VREF connected to the error amplifier circuit 110 and the feedback voltage VFB are equal. Combined with the compensation capacitor Cc, the output of the error amplifier circuit 110 becomes the dominant pole. The pole compensation circuit 120 weakens the output impedance and makes the output pole a secondary pole, thereby pushing the output pole away from the origin, so that the voltage regulator has strong robustness under different load capacitances.

[0080] During their research, the inventors also discovered that some traditional solutions employ zero-pole tracking frequency compensation circuits to eliminate the impact of output pole changes on stability, including interconnected switched capacitors and oscillators. However, this introduces additional circuitry such as switched capacitors and oscillators, increasing chip area and dynamic power consumption during switching. The voltage regulator provided in this application, compared to these solutions, does not add switched capacitors and oscillators, thus avoiding interference from switching signals on the output and eliminating dynamic power consumption. It is compatible with low-dropout linear regulator circuits with various complex capacitors, and its robustness remains largely unaffected when the load capacitance is much smaller than the nominal value and the load current varies significantly. Furthermore, the voltage regulator provided in this application easily achieves a high power supply rejection ratio.

[0081] In a second aspect, this application provides a chip including the voltage regulator described in any of the above embodiments, which exhibits strong robustness under different load capacitances.

[0082] In a third aspect, this application provides an electronic device including the voltage regulator or the chip described in any of the above embodiments, which has high robustness.

[0083] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0084] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0085] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0086] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A voltage regulator characterized by comprising: The voltage stabilizer comprises an error amplifier circuit, a pole compensation circuit, a power tube, a resistance feedback network and a compensation capacitor. The positive input end of the error amplifier circuit is used for inputting a reference voltage, the negative input end is connected with the output end of the resistance feedback network, the output end is connected with the first input end of the pole compensation circuit and grounded through the compensation capacitor, the second input end of the pole compensation circuit is connected with the gate of the power tube, the output end is connected with a voltage stabilizing output end, the source of the power tube is used for inputting an external power supply, and the drain is connected with the voltage stabilizing output end, and the sampling end of the resistance feedback network is connected with the voltage stabilizing output end. The resistance feedback network is used for sampling the output voltage of the voltage stabilizing output end, adjusting the sampled voltage and outputting a feedback voltage to the negative input end of the error amplifier circuit. The error amplifier circuit is used for amplifying the difference between the reference voltage and the feedback voltage, so that the reference voltage and the feedback voltage are equal, and the output of the error amplifier circuit becomes a main pole in cooperation with the compensation capacitor. The pole compensation circuit is used for weakening the output impedance corresponding to the voltage stabilizing output end, so that the output pole becomes a secondary pole. The drain of the power tube serves as the voltage stabilizing output end and is used for voltage stabilizing output. The pole compensation circuit comprises a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a first resistor and a third current source; the gate of the fifteenth MOS tube is connected with the first end of the compensation capacitor, the source is connected with the voltage stabilizing output end, and the drain is connected with the gate of the sixteenth MOS tube and the source of the seventeenth MOS tube respectively and grounded through the third current source; the source of the sixteenth MOS tube is connected with the voltage stabilizing output end, and the drain is grounded; the gate of the seventeenth MOS tube is used for inputting a first preset voltage, the drain is connected with the drain of the eighteenth MOS tube, the gate of the eighteenth MOS tube and the gate of the power tube respectively; the source of the eighteenth MOS tube is connected with the external power supply; and the first resistor is connected between the external power supply and the gate of the eighteenth MOS tube.

2. The voltage regulator of claim 1, wherein The error amplifier circuit comprises a folded common-source common-gate operational amplifier.

3. The voltage regulator of claim 2, wherein, The folded common-source common-gate operational amplifier comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and a first current source. The gate of the first MOS is used for accessing the reference voltage, the drain is connected with the drain of the third MOS and the source of the fifth MOS, the source is connected with the source of the second MOS and grounded through the first current source, the gate of the second MOS is used for accessing the feedback voltage, the drain is connected with the drain of the fourth MOS and the source of the sixth MOS, the gate of the third MOS is connected with the gate of the fourth MOS, the source is connected with the voltage output, the source of the fourth MOS is connected with the voltage output, the gate of the fifth MOS is connected with the gate of the sixth MOS, the drain is connected with the drain of the seventh MOS, the gate of the ninth MOS and the gate of the tenth MOS respectively, the drain of the sixth MOS is connected with the source of the eighth MOS and the first end of the compensation capacitor respectively, the gate of the seventh MOS is connected with the gate of the eighth MOS, the source is connected with the drain of the ninth MOS, the source of the eighth MOS is connected with the drain of the tenth MOS, the source of the ninth MOS is connected with the source of the tenth MOS and the ground respectively.

4. The voltage regulator of claim 1, wherein The error amplification circuit comprises eleventh, twelfth, thirteenth, fourteenth MOS and second current source; The gate of the eleventh MOS is used for accessing the reference voltage, the drain is connected with the drain of the thirteenth MOS, the gate of the thirteenth MOS and the gate of the fourteenth MOS respectively, the source is connected with the source of the twelfth MOS and grounded through the second current source, the gate of the twelfth MOS is used for accessing the feedback voltage, the drain is connected with the drain of the fourteenth MOS and the first end of the compensation capacitor, the source of the thirteenth MOS is connected with the voltage output, and the source of the fourteenth MOS is connected with the voltage output.

5. The voltage regulator of claim 1, wherein, The expression of the output pole comprises: P(D)≈gm1*gmp*R0 / CL; wherein, P(D) represents the output pole, gm1 represents the transconductance of the fifteenth MOS, gmp represents the transconductance of the power tube, R0 represents the resistance value of the first resistor, and CL represents the load capacitor.

6. The voltage regulator of claim 1, wherein, The pole compensation circuit further comprises nineteenth MOS; the gate of the nineteenth MOS is used for accessing the second preset voltage, the source is connected with the gate of the fifteenth MOS, and the drain is connected with the gate of the sixteenth MOS and the source of the seventeenth MOS respectively and grounded through the third current source.

7. The voltage regulator of claim 6, wherein, The expression of the output pole comprises: P(D)≈gm2*gmp*R0 / CL; wherein, P(D) represents the output pole, gm2 represents the transconductance of the fifteenth MOS and the nineteenth MOS together, gmp represents the transconductance of the power tube, R0 represents the resistance value of the first resistor, and CL represents the load capacitor.

8. The voltage regulator of claim 1, wherein, The resistance feedback network comprises a second resistance and a third resistance; a first end of the third resistance is connected to the voltage output end, and a second end thereof is connected to the ground through the second resistance; and the third resistance is further configured to provide the feedback voltage.

9. The voltage regulator of claim 1, wherein, The voltage regulator further comprises an off-chip load unit; the off-chip load unit is connected between the voltage output end and the ground end; and the off-chip load unit is configured to simulate an actual load scenario.

10. The voltage regulator of claim 9, wherein, The off-chip load unit comprises a load capacitor and a fourth resistance; the load capacitor and the fourth resistance are connected in parallel between the voltage output end and the ground end.

11. A chip, characterized by The voltage regulator comprises any one of claims 1 to 10.

12. An electronic device, comprising: The voltage regulator comprises any one of claims 1 to 10 or the chip of claim 11.

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