A double-loop hybrid low-dropout linear voltage regulator based on average algorithm

Abstract

The application discloses a double-loop hybrid low-dropout linear voltage regulator based on an average algorithm and belongs to the technical field of low-dropout linear voltage regulators, comprising a sampling resistor module, a voltage comparator module, an ALDO controller, an average algorithm controller, a DLDO module, an ALDO module and a band gap reference source. The output voltage of the DLDO module or the ALDO module is converted into a sampling voltage through the sampling resistor module, the voltage comparator module compares the sampling voltage with the numerical values of the lower limit reference voltage and the upper limit reference voltage to generate a control word, the ALDO controller generates a control signal and an enable signal according to the control word, the average algorithm controller regulates the to-be-output voltage of the DLDO module, and the ALDO module regulates the output voltage of the DLDO module. Through the double-loop control method of the DLDO module and the ALDO module, the voltage regulator simultaneously has a digital voltage stabilization mode and an analog voltage stabilization mode, and the output voltage is always stabilized at the desired level of the reference voltage through twice voltage regulation.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of low-dropout linear voltage stabilizers, in particular to a double-loop hybrid low-dropout linear voltage stabilizer based on an average value algorithm. BACKGROUND

[0002] With the rapid development of the integrated circuit industry, a system on chip highly integrates a plurality of analog modules and digital modules with different functions, and each module has different requirements for a power rail and is affected by load changes. With the advent of the 5G era, various portable electronic devices will increase substantially, and low-voltage ultra-low-power applications have become the goal of electronic circuit design. In order to improve power utilization and take into account the power voltage requirements of different modules, modern power management circuits use voltage stabilizers to divide the voltage into different voltage domains. A low-dropout linear voltage stabilizer is a core module in a power management circuit and is divided into a digital low-dropout linear voltage stabilizer (DLDO) and an analog low-dropout linear voltage stabilizer (ALDO).

[0003] A traditional ALDO uses a high-gain error amplifier to drive a power tube to adjust an output voltage, has the advantages of simple structure, high bandwidth, low voltage ripple, high power supply rejection ratio, and fast transient response, but a large off-chip compensation capacitor is often needed to achieve stability. The traditional ALDO can achieve high gain and high bandwidth only under high input voltage, and it is difficult for the error amplifier, the core circuit of the ALDO, to achieve high gain and bandwidth under low input power voltage. The ALDO currently has many problems such as a narrow output range and poor portability.

[0004] A traditional DLDO uses a voltage comparator module and digital control logic to control a power adjustment tube array to achieve voltage stabilization. The digital design process of the DLDO can work stably under a low power voltage, and another advantage of the DLDO is that its performance parameters are proportional to the process size, and standard cells are used in digital circuit design, so the portability of the DLDO is better and it is almost not affected by the process. However, the efficiency of the traditional DLDO is not high, because the DLDO only changes one switching state in each cycle, so we usually need hundreds of switches to achieve higher output accuracy, but the increase in switches slows down the response speed of the circuit. In addition, due to the limited output accuracy, the digital control code will oscillate between the nearby code values when the load is constant, thereby causing a limit cycle oscillation phenomenon.

[0005] In actual circuit application, the output voltage of the circuit will change due to the change of the load, and the change of the output voltage can cause the circuit to malfunction or even damage the circuit. Therefore, in order to make up for the shortcomings of the traditional DLDO and ALDO, it is necessary to design a double-loop hybrid low-dropout linear regulator which can suppress the undershoot or overshoot of the output voltage in time when the load of the circuit changes, can quickly respond to the transient state and keep the output voltage stable at the desired level of the reference voltage, and has the advantages of ALDO and DLDO. SUMMARY

[0006] The purpose of the present application is to provide a double-loop hybrid low-dropout linear regulator based on average algorithm to solve the problem that the change of the load will cause the change of the output voltage of the circuit.

[0007] To achieve the above purpose, the present application provides the following scheme:

[0008] A double-loop hybrid low-dropout linear regulator based on average algorithm, comprising: a sampling resistance module, a voltage comparator module, an ALDO controller, an average algorithm controller, a DLDO module, an ALDO module and a bandgap reference source.

[0009] The sampling resistance module is connected with the DLDO module, the ALDO module and the voltage comparator module respectively, and the sampling resistance module is used to convert the output voltage of the DLDO module or the ALDO module into a sampling voltage and deliver it to the input end of the voltage comparator module and the input end of the ALDO module.

[0010] The voltage comparator module is used to compare the numerical values of the sampling voltage with the lower limit reference voltage and the upper limit reference voltage, and output a control word according to the comparison result.

[0011] The input end of the ALDO controller is connected with the output end of the voltage comparator module, the output end of the ALDO controller is connected with the input end of the ALDO module and the input end of the average algorithm controller respectively, the ALDO controller is used to generate a control signal and an enable signal according to the control word, the control signal is used to control the conduction or turn-off of the average algorithm controller, and the enable signal is used to control the conduction or turn-off of the ALDO module.

[0012] The output end of the average algorithm controller is connected with the input end of the DLDO module, and the average algorithm controller is used to regulate the voltage of the output voltage of the DLDO module.

[0013] The input end of the ALDO module is also connected with the output end of the bandgap reference source, for regulating the output voltage of the DLDO module according to the reference voltage output by the bandgap reference source and the sampling voltage.

[0014] Optionally, the sampling resistance module comprises a first sampling resistance and a second sampling resistance.

[0015] One end of the first sampling resistance is connected with the output end of the DLDO module and the output end of the ALDO module respectively, and the other end of the first sampling resistance is connected with one end of the second sampling resistance, the input end of the voltage comparator module and the input end of the ALDO module respectively; the other end of the second sampling resistance is grounded.

[0016] Optionally, the voltage comparator module comprises a first voltage comparator and a second voltage comparator.

[0017] The inverting end of the first voltage comparator inputs the upper limit reference voltage, and the non-inverting end of the first voltage comparator and the inverting end of the second voltage comparator are both connected with the other end of the first sampling resistance; the non-inverting end of the second voltage comparator inputs the lower limit reference voltage; the output end of the first voltage comparator and the output end of the second voltage comparator are both connected with the input end of the ALDO controller.

[0018] Optionally, the first output end of the ALDO controller is connected with the average algorithm controller, and the second output end of the ALDO controller is connected with the input end of the ALDO module.

[0019] Optionally, the average algorithm controller comprises a D flip-flop, an XOR gate, a multiplexer, an adder, a divider, a first register and a second register.

[0020] The input pin of the D flip-flop is connected with the first output end of the ALDO controller and the first input end of the XOR gate respectively, the reset pin of the D flip-flop is connected with a reset signal, the clock pin of the D flip-flop is connected with a clock signal, and the output pin of the D flip-flop is connected with the second input end of the XOR gate.

[0021] The output end of the XOR gate is connected with the first input end of the multiplexer; the second input end of the multiplexer is connected with the output end of the first register and the first input end of the adder respectively, the third input end of the multiplexer is connected with the output end of the second register and the second input end of the adder respectively, and the output end of the multiplexer is connected with the input end of the first register; the reset end of the first register is connected with a reset signal.

[0022] The output end of the adder is connected with the input end of the divider; the output end of the divider is connected with the input end of the second register and the input end of the DLDO module respectively.

[0023] Optionally, the DLDO module comprises a PMOS switch array; the gate of each first PMOS transistor in the PMOS switch array is connected with the output end of the divider, the source of each first PMOS transistor is connected with a power supply voltage, and the drain of each first PMOS transistor is connected with one end of the first sampling resistor.

[0024] Optionally, the ALDO module comprises an error amplifier and a second PMOS transistor.

[0025] The inverting end of the error amplifier is connected with the output end of the bandgap reference source, the non-inverting end of the error amplifier is connected with the other end of the first sampling resistor, the input end of the error amplifier is connected with the second output end of the ALDO controller, and the output end of the error amplifier is connected with the gate of the second PMOS transistor; the source of the second PMOS transistor is connected with a power supply voltage, and the drain of the second PMOS transistor is connected with one end of the first sampling resistor.

[0026] Optionally, the voltage comparator module is used for comparing the numerical values of the sampling voltage, the lower limit reference voltage and the upper limit reference voltage, and outputting a control word according to the comparison result, and specifically comprises:

[0027] When the sampling voltage is less than the lower limit reference voltage, the control word is 01; when the sampling voltage is greater than the lower limit reference voltage and less than the upper limit reference voltage, the control word is 00; and when the sampling voltage is greater than the upper limit reference voltage, the control word is 10.

[0028] Optionally, when the control word is 01 or 10, the control signal controls the average value algorithm controller to be turned on, the enable signal controls the ALDO module to be turned off at a low level, and the double-loop hybrid low-dropout linear voltage regulator works in a digital voltage stabilization mode.

[0029] When the control word is 00, the control signal controls the average value algorithm controller to be turned off, the enable signal controls the ALDO module to be turned on at a high level, and the double-loop hybrid low-dropout linear voltage regulator works in an analog voltage stabilization mode.

[0030] According to the specific embodiments of the present application, the following technical effects are provided:

[0031] This invention provides a dual-loop hybrid low-dropout linear regulator based on an averaging algorithm. A sampling resistor module converts the output voltage of a DLDO or ALDO module into a sampled voltage. A voltage comparator module compares the sampled voltage with lower and upper reference voltages to generate a control word. The ALDO controller generates a control signal and an enable signal based on the control word. The control signal controls the on / off state of the averaging algorithm controller, and the enable signal controls the on / off state of the ALDO module. The averaging algorithm controller regulates the output voltage of the DLDO module, and the ALDO module regulates its output voltage. This invention, through a dual-loop control method using both DLDO and ALDO modules, enables the regulator to simultaneously operate in both digital and analog regulation modes, ensuring the output voltage remains consistently stable at the desired reference voltage level through these two voltage adjustments. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A circuit diagram of a dual-loop hybrid low-dropout linear regulator based on an average value algorithm provided by the present invention;

[0034] Figure 2 A schematic diagram illustrating the principle of the voltage comparator module output control word provided by the present invention;

[0035] Figure 3 A circuit diagram of the average value algorithm controller provided by the present invention;

[0036] Figure 4 A flowchart for searching the target voltage value provided by this invention;

[0037] Figure 5 A circuit diagram of the DLDO module provided by the present invention;

[0038] Figure 6 The circuit diagram of the ALDO module provided by this invention. Detailed Implementation

[0039] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0040] The purpose of the present application is to provide a double-loop hybrid low-dropout linear voltage regulator based on an average value algorithm. Through the double-loop control method of the DLDO module and the ALDO module, the voltage regulator has both digital voltage stabilization mode and analog voltage stabilization mode, and the output voltage is stabilized at the desired level of the reference voltage through twice voltage regulation.

[0041] In order to make the above-mentioned purposes, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] As shown in Figure 1 The double-loop hybrid low-dropout linear voltage regulator based on the average value algorithm provided by the present application comprises a sampling resistance module 1, a voltage comparator module 2, an ALDO controller 3, an average value algorithm controller 4, a DLDO module 5, an ALDO module 6 and a bandgap reference source 7.

[0043] The sampling resistance module 1 is connected with the DLDO module 5, the ALDO module 6 and the voltage comparator module 2 respectively, and is used to convert the output voltage of the DLDO module 5 or the ALDO module 6 into a sampling voltage VC and deliver it to the input end of the voltage comparator module 2 and the input end of the ALDO module 6.

[0044] The voltage comparator module 2 is used to compare the numerical values of the sampling voltage VC, the lower limit reference voltage VREF_L and the upper limit reference voltage VREF_H, and output a control word according to the comparison result. The upper limit reference voltage VREF_H and the lower limit reference voltage VREF_L can be generated by the bandgap reference source 7. The upper limit reference voltage VREF_H and the lower limit reference voltage VREF_L are less affected by temperature changes and have consistent error changes, so they have high accuracy and stability and can provide accurate reference voltage for the voltage comparator module 2.

[0045] The input end of the ALDO controller 3 is connected with the output end of the voltage comparator module 2, the output end of the ALDO controller 3 is connected with the input end of the ALDO module 6 and the input end of the average algorithm controller 4 respectively; the ALDO controller 3 is used for generating a control signal SL and an enable signal EN_A according to a control word; the control signal SL is used for controlling the turn-on or turn-off of the average algorithm controller 4, and the enable signal EN_A is used for controlling the turn-on or turn-off of the ALDO module 6. The first output end of the ALDO controller 3 is connected with the average algorithm controller 4, and the second output end of the ALDO controller 3 is connected with the input end of the ALDO module 6.

[0046] The output end of the average algorithm controller 4 is connected with the input end of the DLDO module 5, and the average algorithm controller 4 is used for regulating the voltage to be output by the DLDO module 5.

[0047] The input end of the ALDO module 6 is also connected with the output end of the bandgap reference source 7, and is used for regulating the output voltage of the DLDO module 5 according to the reference voltage output by the bandgap reference source 7 and the sampling voltage VC.

[0048] Further, the sampling resistance module 1 comprises a first sampling resistance R1 and a second sampling resistance R2. One end of the first sampling resistance R1 is connected with the output end of the DLDO module 5 and the output end of the ALDO module 6 respectively, the other end of the first sampling resistance R1 is connected with one end of the second sampling resistance R2, the input end of the voltage comparator module 2 and the input end of the ALDO module 6 respectively; the other end of the second sampling resistance R2 is grounded.

[0049] Further, the voltage comparator module 2 comprises a first voltage comparator CMP1 and a second voltage comparator CMP2. The inverting end of the first voltage comparator CMP1 inputs an upper limit reference voltage VREF_H, the non-inverting end of the first voltage comparator CMP1 and the inverting end of the second voltage comparator CMP2 are connected with the other end of the first sampling resistance R1; the non-inverting end of the second voltage comparator CMP2 inputs a lower limit reference voltage VREF_L; the output end of the first voltage comparator CMP1 and the output end of the second voltage comparator CMP2 are connected with the input end of the ALDO controller 3.

[0050] Further, as shown in FIG. 1, the sampling resistance module 1 comprises a first sampling resistance R1 and a second sampling resistance R2. Figure 2As shown, the control word CMP[2:1] output by the voltage comparator module 2 is composed of the first control word CP1 output by the first voltage comparator CMP1 and the second control word CP2 output by the second voltage comparator CMP2. When the sampling voltage VC is less than the lower limit reference voltage VREF_L, the first control word CP1 is 0 and the second control word CP2 is 1, and the composed control word is 01; when the sampling voltage VC is greater than the lower limit reference voltage VREF_L and less than the upper limit reference voltage VREF_H, the first control word CP1 is 0 and the second control word CP2 is 0, and the composed control word is 00; when the sampling voltage VC is greater than the upper limit reference voltage VREF_H, the first control word CP1 is 1 and the second control word CP2 is 0, and the composed control word is 10.

[0051] When the control word is 01 or 10, the control signal SL controls the average algorithm controller 4 to turn on, the enable signal EN_A is low to control the ALDO module 6 to turn off; the double-loop hybrid low-dropout linear regulator works in the digital voltage stabilization mode. When the control word is 00, the control signal SL controls the average algorithm controller 4 to turn off, and the enable signal EN_A is high to control the ALDO module 6 to turn on; the double-loop hybrid low-dropout linear regulator works in the analog voltage stabilization mode.

[0052] Further, as shown in the figure, Figure 3 The average algorithm controller 4 includes a D flip-flop DFF, an XOR gate XOR, a multiplexer MUX, an adder, a divider, a first register Reg1 and a second register Reg2.

[0053] The input pin D of the D flip-flop DFF is connected with the first output end of the ALDO controller 3 and the first input end of the XOR gate XOR respectively, the reset pin Rest of the D flip-flop DFF is connected with the reset signal, the clock pin CLK of the D flip-flop DFF is connected with the clock signal, and the output pin Q of the D flip-flop DFF is connected with the second input end of the XOR gate XOR.

[0054] The output end of the XOR gate XOR is connected with the first input end of the multiplexer MUX; the second input end of the multiplexer MUX is connected with the output end of the first register Reg1 and the first input end of the adder respectively, the third input end of the multiplexer MUX is connected with the output end of the second register Reg2 and the second input end of the adder respectively, and the output end of the multiplexer MUX is connected with the input end of the first register Reg1; the reset end of the first register Reg1 is connected with the reset signal.

[0055] The output end of the adder is connected with the input end of the divider; the output end of the divider is connected with the input end of the second register Reg2 and the input end of the DLDO module 5 respectively.

[0056] In the prior art, the successive approximation algorithm provides good performance in time complexity and circuit implementation, however, in the application of the DLDO module, the search logic using the successive approximation algorithm can bring additional voltage drop, and increase the amplitude of the output voltage undershoot or overshoot. In order to avoid similar situations, the application adopts an optimized average algorithm. The average algorithm can quickly search the control word required for the target voltage value, and can achieve faster transient response speed than the traditional ALDO module. When the load changes, the average algorithm starts a new search through the reset signal, and determines the original value of the search region according to the load change. The reset signal selects the original value and the upper and lower boundaries for searching. Compared with full-range search, the average algorithm reduces the large search range.

[0057] As shown in Figure 3 and Figure 4 In each clock cycle, the data stored in the second register Reg2 is replaced by half of the data stored in the first register Reg1 and half of the data stored in the second register Reg2, and the data stored in the first register Reg1 is replaced by the data stored in the first register Reg1 or the second register Reg2 in the previous clock cycle. If the control signal SL remains unchanged in two consecutive adjacent clock cycles, it means that the target voltage value is between half of the data stored in the first register Reg1 and half of the data stored in the second register Reg2 and the data stored in the first register Reg1, then the data stored in the first register Reg1 is kept as the search boundary, if the control signal SL jumps in two consecutive adjacent clock cycles, it means that half of the data stored in the first register Reg1 and half of the data stored in the second register Reg2 have exceeded the target voltage value, at this time, the data stored in the first register Reg1 should be replaced by the data stored in the second register Reg2 to change the search direction of the average search algorithm. The average algorithm has very high response speed, and in the worst case, it only needs 5 clock cycles to search the target voltage value, greatly improving the transient response speed of the DLDO module 5. Among them, Figure 4 Reg1_i in the formula (1) is the data stored in the first register Reg1 in the i th clock cycle, Reg2_i is the data stored in the second register Reg2 in the i th clock cycle, i = 1, 2, 3, 4, 5.

[0058] The optimized average algorithm adopted by the application can be realized by a digital circuit standard unit, so that a digital circuit design method can be used in a circuit front-end design process. By writing corresponding Verilog code, using a circuit synthesis tool and finally automatically laying out and wiring to draw a digital circuit layout, the time for drawing an analog layout is saved and the design efficiency is improved. In addition, the circuit of the average algorithm controller 4 used in the application is not limited by the process, and the use of standard units for physical implementation can make the circuit have good portability.

[0059] Further, as shown in Figure 5 The DLDO module 5 includes a PMOS switch array. The gates of each first PMOS transistor in the PMOS switch array are connected to the output end of the divider, the sources of each first PMOS transistor are connected to a power supply voltage, the drains of each first PMOS transistor are connected to one end of a first sampling resistor R1, and each first PMOS transistor is M0, M1, M2, M3, M4 and M5, respectively.

[0060] As shown in Figure 5 The control word D[5:0] output by the average algorithm controller 4 controls the conduction and cutoff of the PMOS switch array, and further changes the output current size of the PMOS switch array to further adjust the size of the voltage to be output by the DLDO module 5 to achieve the purpose of voltage stabilization. In this embodiment, the PMOS switch array includes six first PMOS transistors, so the control word D[5:0] is a 6-bit control signal SL, which can realize control output from 000000 to 111111, wherein the control word D[5:0] is divided into six independent control signals D[5], D[4], D[3], D[2], D[1] and D[0]. Each control signal D[j] has two states of 1 and 0, i.e. high and low levels. The size of the first PMOS transistor controlled by the highest bit control signal D[5] is twice the size of the first PMOS transistor controlled by the second highest bit control signal D[4], and so on. The size of the current output by each first PMOS transistor when it is turned on is also in a proportional relationship of 2 times. According to Kirchhoff's law, the total current output by the DLDO module 5 is equal to the sum of the currents output by each first PMOS transistor. When the control signal D[i] is high at 1, the corresponding first PMOS transistor is in a conduction state and outputs current; when the control signal D[j] is low at 0, the corresponding PMOS switch is in a cutoff state and does not output current, j is the jth control signal, j=0, 1, 2, 3, 4, 5.

[0061] Further, as shown in Figure 6 The ALDO module 6 includes an error amplifier EA and a second PMOS transistor MA.

[0062] The reverse end of the error amplifier EA is connected with the output end of the bandgap reference source 7, the non-inverting end of the error amplifier EA is connected with the other end of the first sampling resistor R1, the input end of the error amplifier EA is connected with the second output end of the ALDO controller 3, and the output end of the error amplifier EA is connected with the gate of the second PMOS transistor MA; the source of the second PMOS transistor MA is connected with the power voltage, and the drain of the second PMOS transistor MA is connected with one end of the first sampling resistor R1.

[0063] When the double-loop hybrid low-dropout linear voltage regulator works in the analog voltage regulation mode, because the voltage is stabilized by the DLDO module 5 and approaches the reference voltage level, the ALDO module 6 takes over the voltage regulation by enabling, the reference voltage VREF of the error amplifier EA comes from the output of the bandgap reference source 7, the output of the error amplifier EA is the gate voltage of the second PMOS transistor, the gate voltage can control the on-current size of the second PMOS transistor, the output voltage is finely adjusted by adjusting the gate voltage of the second PMOS transistor through the error signal, so that the output voltage is equal to the reference voltage. The ALDO module 6 constitutes a negative feedback loop, so it can adaptively change the size of the gate voltage, thereby more accurately adjusting the size of the output voltage.

[0064] Because the ALDO module 6 has an enabling end, in the digital voltage regulation mode, the ALDO module 6 is directly turned off, unnecessary power consumption is avoided, and the stability of the system is also increased. In the analog voltage regulation mode, the ALDO module 6 completely takes over the voltage regulation work, and the DLDO module 5 is in a holding state, so the limit cycle oscillation phenomenon of the traditional DLDO module 5 is eliminated.

[0065] The double-loop hybrid low-dropout linear voltage regulator based on the average value algorithm provided by the application adopts a double-loop control method, combines the DLDO module and the ALDO module, so that the voltage regulator has both the digital voltage regulation mode and the analog voltage regulation mode.

[0066] The application overcomes the problems of poor voltage regulation precision and low power supply rejection ratio of the DLDO module, eliminates the limit cycle oscillation phenomenon of the DLDO module by introducing the ALDO module, reduces the steady-state output voltage ripple, eliminates the use of load capacitance, and improves the voltage regulation quality. The application overcomes the problem of insufficient gain of the ALDO module at advanced process nodes and low power voltage, and makes the voltage regulator work normally at low voltage by introducing the DLDO module. The DLDO module of the application uses a lower frequency clock, which greatly reduces the power consumption of the overall circuit. The average value search algorithm adopted by the application has a faster transient response speed than the traditional linear search algorithm.

[0067] The application has more extensive application scenarios, and can provide low-power and low-voltage power management for digital SOC, portable electronic devices and the like.The digital circuit in the application has good portability, and to some extent, reduces the dependence on process parameter adjustment.The application overcomes the problem that the minimum output current of the traditional DLDO module is not 0 when the load is light, and the analog LDO can make the minimum output current 0 when the load is light or empty.The ALDO module in the application realizes fine adjustment of voltage, and does not need super-high gain, so that no large capacitor outside the chip is needed for loop compensation to ensure the phase margin, and no capacitor outside the chip greatly reduces the layout area of the circuit and increases the integration of the voltage stabilizer.

[0068] The various embodiments are described in a progressive manner in the specification, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.

[0069] The principles and implementation manners of the application are described by applying specific examples herein, and the above description of the embodiments is only used to help understand the circuit of the application and its core idea; meanwhile, for those skilled in the art, according to the idea of the application, the specific implementation manners and application ranges can be changed.The above description of the specification should not be understood as a limitation of the application.

Claims

1. A dual-loop hybrid low-dropout linear regulator based on an average value algorithm, characterized in that, include: Sampling resistor module, voltage comparator module, ALDO controller, average value algorithm controller, DLDO module, ALDO module and bandgap reference source; The sampling resistor module is connected to the DLDO module, the ALDO module, and the voltage comparator module, respectively. The sampling resistor module is used to convert the output voltage of the DLDO module or the ALDO module into a sampling voltage and send it to the input terminal of the voltage comparator module and the input terminal of the ALDO module; The voltage comparator module is used to compare the sampled voltage with the lower limit reference voltage and the upper limit reference voltage, and output a control word based on the comparison result; The input terminal of the ALDO controller is connected to the output terminal of the voltage comparator module, and the output terminal of the ALDO controller is connected to the input terminal of the ALDO module and the input terminal of the averaging algorithm controller, respectively. The ALDO controller is used to generate control signals and enable signals according to the control word. The control signals are used to control the averaging algorithm controller to turn on or off, and the enable signals are used to control the ALDO module to turn on or off. The output terminal of the average value algorithm controller is connected to the input terminal of the DLDO module, and the average value algorithm controller is used to adjust the output voltage of the DLDO module. The input terminal of the ALDO module is also connected to the output terminal of the bandgap reference source, and is used to adjust the output voltage of the DLDO module according to the reference voltage output by the bandgap reference source and the sampling voltage; The sampling resistor module includes a first sampling resistor and a second sampling resistor; one end of the first sampling resistor is connected to the output terminal of the DLDO module and the output terminal of the ALDO module respectively, and the other end of the first sampling resistor is connected to one end of the second sampling resistor, the input terminal of the voltage comparator module and the input terminal of the ALDO module respectively; the other end of the second sampling resistor is grounded. The voltage comparator module includes a first voltage comparator and a second voltage comparator; the inverting input of the first voltage comparator is input to the upper limit reference voltage, and the non-inverting input of the first voltage comparator and the inverting input of the second voltage comparator are both connected to the other end of the first sampling resistor; the non-inverting input of the second voltage comparator is input to the lower limit reference voltage; the outputs of the first voltage comparator and the second voltage comparator are both connected to the input of the ALDO controller; The first output terminal of the ALDO controller is connected to the average value algorithm controller, and the second output terminal of the ALDO controller is connected to the input terminal of the ALDO module. The average value algorithm controller includes: a D flip-flop, an XOR gate, a multiplexer, an adder, a divider, a first register, and a second register; the output of the adder is connected to the input of the divider; the output of the divider is connected to the input of the second register and the input of the DLDO module, respectively. In each clock cycle, the data stored in the second register is replaced by half of the data stored in the first register plus half of the data stored in the second register, and the data stored in the first register is replaced by the data stored in the first or second register in the previous clock cycle; If the control signal remains unchanged for two consecutive adjacent clock cycles, the target voltage value is between the sum of half the data stored in the first register and half the data stored in the second register, and the data stored in the first register is maintained as the search boundary. If the control signal changes within two consecutive adjacent clock cycles, the sum of half the data stored in the first register and half the data stored in the second register exceeds the target voltage value. In this case, the data stored in the first register is replaced by the data stored in the second register to change the search direction of the average value search algorithm.

2. The dual-loop hybrid low-dropout linear regulator based on the average value algorithm according to claim 1, characterized in that, The connection method of each component of the average value algorithm controller is as follows: The input pins of the D flip-flop are connected to the first output terminal of the ALDO controller and the first input terminal of the XOR gate, respectively. The reset pin of the D flip-flop is connected to the reset signal, the clock pin of the D flip-flop is connected to the clock signal, and the output pin of the D flip-flop is connected to the second input terminal of the XOR gate. The output of the XOR gate is connected to the first input of the multiplexer; the second input of the multiplexer is connected to the output of the first register and the first input of the adder, respectively; the third input of the multiplexer is connected to the output of the second register and the second input of the adder, respectively; the output of the multiplexer is connected to the input of the first register; the reset terminal of the first register is connected to a reset signal.

3. The dual-loop hybrid low-dropout linear regulator based on the average value algorithm according to claim 2, characterized in that, The DLDO module includes a PMOS switch array; the gate of each first PMOS transistor in the PMOS switch array is connected to the output terminal of the divider, the source of each first PMOS transistor is connected to the power supply voltage, and the drain of each first PMOS transistor is connected to one end of the first sampling resistor.

4. The dual-loop hybrid low-dropout linear regulator based on the average value algorithm according to claim 3, characterized in that, The ALDO module includes: an error amplifier and a second PMOS transistor; The inverting terminal of the error amplifier is connected to the output terminal of the bandgap reference source, the non-inverting terminal of the error amplifier is connected to the other end of the first sampling resistor, the input terminal of the error amplifier is connected to the second output terminal of the ALDO controller, and the output terminal of the error amplifier is connected to the gate of the second PMOS transistor; the source of the second PMOS transistor is connected to the power supply voltage, and the drain of the second PMOS transistor is connected to one end of the first sampling resistor.

5. The dual-loop hybrid low-dropout linear regulator based on the average value algorithm according to claim 1, characterized in that, The voltage comparator module is used to compare the sampled voltage with the values ​​of the lower limit reference voltage and the upper limit reference voltage, and outputs a control word based on the comparison result, specifically including: When the sampling voltage is less than the lower limit reference voltage, the control word is 01; when the sampling voltage is greater than the lower limit reference voltage and less than the upper limit reference voltage, the control word is 00; when the sampling voltage is greater than the upper limit reference voltage, the control word is 10.

6. The dual-loop hybrid low-dropout linear regulator based on the average value algorithm according to claim 5, characterized in that, When the control word is 01 or 10, the control signal controls the average value algorithm controller to turn on, and the enable signal is low to control the ALDO module to turn off; the dual-loop hybrid low dropout linear regulator operates in digital regulation mode. When the control word is 00, the control signal controls the average value algorithm controller to turn off, and the enable signal is high to control the ALDO module to turn on; the dual-loop hybrid low dropout linear regulator operates in analog voltage regulation mode.

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