Low-cost flash controller based on open-source RISCV and processing method thereof

Abstract

The application provides a low-cost flash memory controller based on an open-source RISCV and a processing method thereof. The flash memory controller comprises: open-source RISCV cores used for optimizing LDPC algorithm matrix algorithms by using vector instructions, wherein: a plurality of open-source RISCV cores are arranged together, the plurality of open-source RISCV cores are divided into a plurality of size cores, and the plurality of size cores are used for being responsible for general logic control and being responsible for ECC algorithms; and the ECC software error correction algorithm is used for combining a CRC check algorithm and an LDPC error correction algorithm. By using the open-source RISCV cores, combining the vector instructions and the LDPC algorithm matrix algorithm requirements, and giving full play to the advantages of the two, the application optimizes the decoding process by using the software ECC algorithm to replace the algorithm IP, reduces the probability of reading error data as much as possible, reduces the opportunity of entering the error correction algorithm, and makes most of the data execute the shortest calculation path.

Description

Technical Field

[0001] This invention relates to the field of flash memory controller technology, and in particular to a low-cost flash memory controller based on open-source RISCV and its processing method. Background Technology

[0002] Currently, most mobile storage devices use ARM architecture processors and commercial ECC algorithm IP. With the large-scale commercialization of 3D NandFlash, the main control unit needs to support more functions and computing power, and also needs to support the more efficient and powerful LDPC algorithm. The cost of purchasing higher-performance processor IP and algorithm IP will continue to rise.

[0003] Defects and shortcomings of existing technology:

[0004] Commercial processor IP is expensive and may be subject to technology licensing restrictions;

[0005] Commercial algorithm IPs are expensive, and the cost will be even higher if customized requirements are needed to enhance competitiveness.

[0006] While using logic algorithm IP has advantages in power consumption and computing power, it cannot achieve algorithm upgrades and optimizations.

[0007] To address this, a low-cost flash memory controller based on open-source RISCV and its processing method are proposed. Summary of the Invention

[0008] In view of this, embodiments of the present invention aim to provide a low-cost flash memory controller and processing method based on open-source RISCV, in order to solve or alleviate the technical problems existing in the prior art, and at least provide a beneficial option.

[0009] The technical solution of this invention is implemented as follows: a low-cost flash memory controller based on open-source RISC-CV, comprising:

[0010] Based on the open-source RISC-CV multi-core design, the LDPC matrix algorithm is optimized using its vector instructions, where:

[0011] The open-source RISC-CV core hardware supports vector instructions and parallel computation of multiple multiplier units, which can improve the efficiency of matrix operations. The LDPC algorithm is characterized by requiring a large number of matrix operations, and adopts a multi-core design to increase the upper limit of computing power and improve encoding and decoding performance.

[0012] The ECC software error correction algorithm combines the CRC check algorithm and the LDPC error correction algorithm. First, the CRC check algorithm is used to quickly determine the correctness of the data. If the data is incorrect, it is corrected by LDPC and then rewritten, so that the error correction algorithm is not needed when the data is read again, thus reducing unnecessary error correction operations.

[0013] The flash memory controller also includes a three-stage pipeline control module to address the issue of large fluctuations in the processing time of the software ECC error correction algorithm, smoothing the bitstream and improving the parallelism of each stage. Data storage is processed in parallel through a three-stage pipeline: data reading and writing, ECC encoding / decoding, and Flash reading / writing, with FIFO backpressure controlling the data transmission rate.

[0014] Further preferred: the big. and small cores include Core0 core, Core1 core, Core2 core and Core3 core, wherein:

[0015] Core0 and Core1 are small cores that use low-frequency clocks for logic control, while Core2 and Core3 are large cores that use high-frequency clocks to enable continuous transmission of software ECC and SDC data.

[0016] A further preferred embodiment: the big.knock and little.knock processing includes:

[0017] When the FIFO is under backpressure, a transmission interval occurs;

[0018] Software ECC write data latency is fixed;

[0019] When reading data using software ECC, latency is directly proportional to the number of errors.

[0020] The FC processing data interval is used to wait for ECC to complete and for the Program phase.

[0021] A further preferred embodiment: the three-stage flow control module is loaded with the LDPC software ECC algorithm.

[0022] A further preferred embodiment: the LDPC software ECC algorithm includes a verification algorithm and an error correction algorithm;

[0023] The verification algorithm selected is CRC;

[0024] The error correction algorithm selected is LDPC.

[0025] Further preferred: The LDPC software ECC algorithm also includes:

[0026] When writing data, CRC check and LDPC encoding are used;

[0027] When reading data, CRC check is used. If the check is successful, the data without errors is sent through the fast channel and the result is output with zero delay.

[0028] When the verification fails, LDPC error correction is used and bad pixels are isolated. Finally, the data is written back. After the write-back is successful, the result is output.

[0029] A further preferred embodiment: When the verification is successful, data without verification errors is processed through a fast channel, with zero delay in outputting the result, specifically including:

[0030] The verification algorithm, combined with hardware, outputs results immediately upon completion of data copying. Frames without verification errors are specially processed, eliminating the need for error correction algorithms and resulting in zero-delay output.

[0031] A further preferred method: When the verification fails, LDPC error correction is used, bad pixels are isolated, and finally, data is written back. After successful write-back, the result is output, specifically including:

[0032] After completing the error correction, the error correction algorithm marks and isolates the error location, and writes the correct data back to Flash to ensure that there are no errors when reading and writing the data next time. This achieves the goal of ensuring that the data in Flash is correct at all times, reducing the chance of entering the error correction algorithm process and improving the algorithm performance. The LDPC error correction algorithm supports software decoding. When the total number of misaligned locations detected in Flash reaches a certain threshold, it attempts HR and SR1, SR2 software decoding, and increases the Parity length to improve the error correction capability when there are more bad blocks.

[0033] This invention also provides a low-cost flash memory controller based on open-source RISC and a processing method thereof, comprising the following steps:

[0034] Retrieve data from Flash and perform CRC verification. Based on the verification result, send the data to the Host.

[0035] The verification results include:

[0036] S1. The data is correct. Send the data directly to the Host.

[0037] S2. Data error. The LDPC algorithm is used for error correction. Based on the correction result, the following steps are performed:

[0038] S21. Error correction successful. Determine if the error bit is greater than the threshold, and perform the following steps based on the result:

[0039] S211, Greater than the threshold: Increase the Parity length and proceed to step S213;

[0040] S212, If the value is less than the threshold, proceed to step S213;

[0041] S213. Update the error Bit Hash table, write the correct data back to Flash, and return the data to the Host;

[0042] S22. Error correction failed, and the following steps were performed according to the current error correction mode, including:

[0043] S221, Hardware Decoding Mode: Enter software decoding mode, including:

[0044] Read data from Flash using software decoding mode (SR1 / SR2), and return to step S2;

[0045] S222, Soft Decoding Mode: Exit with an error message if soft decoding fails.

[0046] The embodiments of the present invention have the following advantages due to the adoption of the above technical solutions:

[0047] I. This invention optimizes the LDPC matrix algorithm using vector instructions based on the open-source RISC multi-core design. The open-source RISC core hardware supports vector instructions and parallel computation of multiple multiplier units, which can improve the efficiency of matrix operations. The LDPC algorithm requires a large number of matrix operations, and the multi-core design increases the upper limit of computing power and improves encoding and decoding performance.

[0048] Second, this invention uses ECC software error correction algorithm, combined with CRC check algorithm and LDPC error correction algorithm. First, the CRC check algorithm is used to quickly determine the correctness of the data. If the data is wrong, it is corrected by LDPC and then rewritten. This ensures that the data does not need to go through the error correction algorithm the next time it is read, reducing unnecessary error correction operations, minimizing the probability of reading erroneous data, and reducing the chance of entering the error correction algorithm. This allows most data to follow the shortest calculation path.

[0049] Third, this invention solves the problem of large fluctuations in the time consumption of software ECC error correction algorithm through three-stage pipeline control, smooths the bit stream and improves the parallelism of each stage, and processes data storage in parallel through three-stage pipelines of reading and writing data, ECC encoding and decoding, and reading and writing Flash, and uses FIFO backpressure control to control the data transmission rate.

[0050] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the invention will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a structural diagram of the flash memory controller of the present invention;

[0053] Figure 2 This is a flowchart illustrating the data reading and writing process of the LDPC software ECC algorithm in the flash memory controller of this invention.

[0054] Figure 3 This is a flowchart illustrating the message processing mechanism of the flash memory control system of the present invention.

[0055] Figure 4 This is a flowchart of the optimized ECC algorithm in the software of this invention. Detailed Implementation

[0056] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0057] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0058] like Figure 1-4 As shown, this embodiment of the invention provides a low-cost flash memory controller based on open-source RISC-CV, comprising:

[0059] The open-source RISC-V core is used to optimize the LDPC matrix algorithm using its vector instructions, where:

[0060] There are multiple open-source RISC V cores, which are divided into several large and small cores, used to handle general logic control and ECC algorithms.

[0061] The ECC software error correction algorithm combines the CRC check algorithm and the LDPC error correction algorithm, and includes the following steps during error correction:

[0062] The CRC check algorithm is used to determine the correctness of the data. If the data is incorrect, the LDPC error correction algorithm is used to correct the error and then the data is rewritten to ensure that the error correction algorithm is not needed when the data is read again, thus reducing unnecessary error correction operations.

[0063] The big.LITTLE architecture includes Core0, Core1, Core2, and Core3 cores, among which:

[0064] Core0 and Core1 are small cores that use low-frequency clocks to process logic control, while Core2 and Core3 are large cores that use high-frequency clocks to achieve continuous transmission of software ECC and SDC data.

[0065] More specifically: In big and small kernel processing, this includes:

[0066] When the FIFO is under backpressure, a transmission interval occurs;

[0067] Software ECC write data latency is fixed;

[0068] When reading data using software ECC, latency is directly proportional to the number of errors.

[0069] The FC processing data interval is used to wait for ECC completion and the Program phase.

[0070] The flash controller also includes a three-stage pipeline control module, which is used to solve the time fluctuation of the software ECC error correction algorithm, smooth the bit stream to improve the parallelism of each stage, and process data storage in parallel through the three-stage pipeline of reading and writing data, ECC encoding and decoding, and reading and writing Flash. FIFO backpressure is used to control the data transmission rate.

[0071] The three-stage flow control module is equipped with the LDPC software ECC algorithm.

[0072] More specifically: The ECC algorithm in LDPC software includes a verification algorithm and an error correction algorithm;

[0073] The verification algorithm chosen is CRC.

[0074] The error correction algorithm chosen is LDPC.

[0075] Meanwhile, the LDPC software's ECC algorithm also includes:

[0076] When writing data, CRC check and LDPC encoding are used;

[0077] When reading data, CRC check is used. If the check is successful, the data without errors is sent through the fast channel and the result is output with zero delay.

[0078] When the verification fails, LDPC error correction is used and bad pixels are isolated. Finally, the data is written back. After the write-back is successful, the result is output.

[0079] When the verification is successful, data without verification errors are processed through the fast track, with zero delay in outputting the results. Specifically, this includes:

[0080] The verification algorithm, combined with hardware, outputs results immediately upon completion of data copying. Frames without verification errors are specially processed, eliminating the need for error correction algorithms and resulting in zero-delay output.

[0081] When verification fails, LDPC error correction is used, and bad pixels are isolated. Finally, data is written back. After successful write-back, the result is output, including:

[0082] After completing the error correction, the error correction algorithm marks and isolates the error location, and writes the correct data back to Flash to ensure that there are no errors when reading and writing the data next time. This achieves the goal of ensuring that the data in Flash is correct at all times, reducing the chance of entering the error correction algorithm process and improving the algorithm performance. The LDPC error correction algorithm supports software decoding. When the total number of misaligned locations detected in Flash reaches a certain threshold, it attempts to perform HR and SR1 and SR2 software decoding, and automatically increases the Parity length to improve the algorithm's error correction capability.

[0083] like Figure 1 As shown, when this controller is in use, the host computer sends instructions. This flash controller includes several big and small cores, which are responsible for general logic control and ECC algorithm.

[0084] The big.LITTLE architecture includes Core0, Core1, Core2, and Core3 cores, among which:

[0085] Core0 and Core1 are small cores that handle logic control, while Core2 and Core3 are large cores that enable continuous data transmission via software ECC and SDC.

[0086] like Figure 3 As shown, a transmission interval occurs when back pressure occurs in the FIFO; the software ECC write data latency is basically fixed, while the read data latency fluctuates significantly due to the number of errors; the FC data processing interval mainly consists of waiting for ECC to complete and the Program phase.

[0087] During this stage, such as Figure 2 and Figure 4 As shown, CRC check and LDPC encoding are used when writing data;

[0088] When reading data, CRC check is used. If the check is successful, the data without errors is sent through the fast channel and the result is output with zero delay.

[0089] When the verification fails, LDPC error correction is used and bad pixels are isolated. Finally, the data is written back. After the write-back is successful, the result is output.

[0090] When the verification is successful, data without verification errors are processed through the fast track, with zero delay in outputting the results. Specifically, this includes:

[0091] like Figure 4 As shown, the verification algorithm, combined with the hardware, outputs the result as soon as the data copy is completed. Frames without verification errors are specially processed, eliminating the need for error correction algorithms and outputting the result with zero delay.

[0092] When verification fails, LDPC error correction is used, and bad pixels are isolated. Finally, data is written back. After successful write-back, the result is output, including:

[0093] like Figure 4 As shown, after completing the error correction, the error correction algorithm marks and isolates the error location, and writes the correct data back to Flash to ensure that there are no errors when reading and writing the data next time. This achieves the goal of ensuring that the data in Flash is correct at all times, reducing the chance of entering the error correction algorithm process and improving the algorithm performance. The LDPC error correction algorithm supports software decoding. When the total number of misaligned positions detected in Flash reaches a certain threshold, it combines HR and SR1, SR2 software decoding, and automatically increases the Parity length to improve the algorithm's error correction capability.

[0094] Through the above scheme, this flash memory controller uses the fast path for data with no errors and outputs results with zero latency; by writing back correct data, it can ensure that most of the data in the flash is correct, reduce the chance of entering the error correction algorithm process, and improve the overall read and write performance of the system.

[0095] This invention fully leverages the advantages of both by using the open-source RISC-CV core and combining its vector instructions with the matrix algorithm requirements of the LDPC algorithm.

[0096] This invention optimizes the decoding process by replacing the algorithm IP with a software ECC algorithm, minimizing the chance of reading erroneous data and reducing the opportunity to enter the error correction algorithm, so that most data follows the shortest calculation path.

[0097] This invention significantly improves data processing capabilities through a multi-core system and a three-stage pipeline, while its powerful computing power reserves room for future algorithm optimization and upgrades.

[0098] This invention also provides a low-cost flash memory controller based on open-source RISC and a processing method thereof, comprising the following steps:

[0099] Retrieve data from Flash and perform CRC verification. Based on the verification result, send the data to the Host.

[0100] The verification results include:

[0101] S1. The data is correct. Send the data directly to the Host.

[0102] S2. Data error. The LDPC algorithm is used for error correction. Based on the correction result, the following steps are performed:

[0103] S21. Error correction successful. Determine if the error bit is greater than the threshold, and perform the following steps based on the result:

[0104] S211, Greater than the threshold: Increase the Parity length and proceed to step S213;

[0105] S212, If the value is less than the threshold, proceed to step S213;

[0106] S213. Update the error Bit Hash table, write the correct data back to Flash, and return the data to the Host;

[0107] S22. Error correction failed, and the following steps were performed according to the current error correction mode, including:

[0108] S221, Hardware Decoding Mode: Enter software decoding mode, including:

[0109] Read data from Flash using software decoding mode (SR1 / SR2), and return to step S2;

[0110] S222, Soft Decoding Mode: Exit with an error message if soft decoding fails.

[0111] In this embodiment, as shown in Table 1, the present invention also provides an explanation of the technical terms used in embodiments 1-2 of this application.

[0112] Table 1

[0113]

[0114] When this invention is in operation:

[0115] Low-cost solution design: Reduce the use of commercial IP and use open-source RISCCV cores and software ECC algorithms;

[0116] Employing multi-core processors: Flexible allocation of computing power allows for the allocation of independent cores to perform ECC encoding or decoding. To improve the performance of the ECC algorithm, RISC-CV vector extension instructions are used to optimize matrix operations in the ECC algorithm.

[0117] Low power design: It adopts a big.LITTLE design, with the small core responsible for general logic control and the big core responsible for ECC and other algorithms. The big core sleeps during idle periods to reduce power consumption.

[0118] A three-stage pipeline is adopted: reading and writing data, ECC encoding and decoding, and reading and writing Flash data are processed in parallel. FIFO backpressure is used to control the data transmission rate.

[0119] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in the present invention, and these should all be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-cost flash memory controller based on open-source RISC-CV, characterized in that, include: The open-source RISC-CV core supports vector extension instructions, enabling parallel computation by multiple multiplier units. This allows for optimization of matrix operations in the LDPC algorithm using vector extension instructions. The open-source RISCCV cores are configured in multiple ways, and these open-source RISCCV cores are divided into several large and small cores, which are respectively used to handle general logic control and ECC software error correction algorithms. The ECC software error correction algorithm is used to combine the CRC check algorithm and the LDPC error correction algorithm. During error correction, it includes the following steps: first, the CRC check algorithm is used to determine the correctness of the data. If the data is incorrect, the LDPC error correction algorithm is used to correct the error and then the correct data is rewritten to Flash. This ensures that the error correction algorithm is not needed when the data is read next time, thus reducing unnecessary error correction operations. The ECC software error correction algorithm also includes: When writing data, CRC check and LDPC encoding are used; When reading data, CRC check is used. If the check is successful, the data without errors is sent through the fast channel and the result is output with zero delay. When the verification fails, LDPC error correction is used and bad pixels are isolated. Finally, the data is written back. After the write-back is successful, the result is output. The flash memory controller also includes a three-stage pipeline control module. The three-stage pipeline control module is used to build a three-stage pipeline architecture for reading and writing Flash, ECC encoding and decoding, and host computer reading and writing. It is used to solve the time fluctuation of ECC software error correction algorithm, smooth the bit stream and improve the parallelism of each stage. The host computer read and write, ECC encoding and decoding, and Flash read and write three-stage pipelines process data storage in parallel, and use FIFO backpressure to control the data transmission rate.

2. The low-cost flash memory controller based on open-source RISC as described in claim 1, characterized in that: The big. and small cores include Core0, Core1, Core2, and Core3, where: Core0 and Core1 are small cores that use low-frequency clocks to process logic control, while Core2 and Core3 are large cores that use high-frequency clocks to continuously transmit software ECC and SDC data, wherein the SDC data is SD card control unit data.

3. The low-cost flash memory controller based on open-source RISC as described in claim 2, characterized in that: The big and small cores process data according to clock configuration and functional division, including: When the FIFO is under back pressure, a transmission interval occurs; Software ECC write data latency is fixed; When reading data using software ECC, latency is directly proportional to the number of errors. The FC processing data interval is used to wait for ECC to complete and for the Program phase.

4. The low-cost flash memory controller based on open-source RISC as described in claim 1, characterized in that: The three-stage flow control module is equipped with an ECC software error correction algorithm.

5. The low-cost flash memory controller based on open-source RISC as described in claim 1, characterized in that: When the verification is successful, data without verification errors is processed through the fast channel, and the result is output with zero delay. Specifically, this includes: The verification algorithm, combined with hardware, outputs the result as soon as the data copy is completed.

6. The low-cost flash memory controller based on open-source RISC as described in claim 1, characterized in that: When the verification fails, LDPC error correction is used to isolate bad pixels, and finally, data is written back. After successful write-back, the result is output, including: After completing error correction, the error correction algorithm marks and isolates the erroneous locations, while simultaneously writing the correct data back to Flash to ensure that there are no errors when reading or writing the data next time. This achieves the goal of ensuring that the data in Flash is always correct, reducing the chance of entering the error correction algorithm process and improving algorithm performance. The LDPC error correction algorithm supports software decoding. When the total number of misaligned locations detected in Flash reaches a certain threshold, it combines HR and SR1, SR2 software decoding, and automatically increases the Parity length to improve the algorithm's error correction capability. Here, HR is the normal data read by the NAND decoder, SR1 is the left threshold data read by the NAND decoder, and SR2 is the right threshold data read by the NAND decoder.

7. A processing method for a low-cost flash memory controller based on open-source RISCV, wherein the low-cost flash memory controller based on open-source RISCV employs the low-cost flash memory controller based on open-source RISCV as described in claim 1, characterized in that, Includes the following steps: Retrieve data from Flash, perform CRC check on the retrieved data, and send the data to the host computer based on the check result; The verification results include: S1. The data is correct. Send the data directly to the Host. S2. Data error. Error correction is performed using the LDPC algorithm optimized with vector extension instructions on the open-source RISC-CV core. Based on the error correction result, the following steps are executed, including: S21. Error correction successful. Determine if the error bit is greater than the threshold, and perform the following steps based on the result: S211, Greater than the threshold: Increase the Parity length and proceed to step S213; S212, If the value is less than the threshold, proceed to step S213; S213. Update the error Bit Hash table, write the correct data back to Flash, and return the data to the Host; S22. Error correction failed, and the following steps were performed according to the current error correction mode, including: S221, Hardware Decoding Mode: Enter software decoding mode, including: Read data from Flash using software decoding mode SR1 / SR2, then return to step S2; S222, Soft Decryption Mode: Exit with an error message if soft decryption fails.

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