An accurate chip manufacturing process defect detection method
By constructing a depthwise separable convolutional module and a residual network feature extraction module, combined with a multi-layer UNet++ structure, automated detection of chip manufacturing process defects was achieved, solving the problems of low detection efficiency and low accuracy in existing technologies and improving detection accuracy.
Patent Information
- Application Number
- CN202310160561.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-02-22
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2043-02-22
AI Technical Summary
Existing chip manufacturing process defect detection methods rely on manual methods, resulting in low detection efficiency and low accuracy, making them unsuitable for large-scale mass production.
We construct a depthwise separable convolutional module and a feature extraction module based on residual networks, and combine them with a multi-layer UNet++ structure to achieve automated defect detection in chip manufacturing processes.
Automated inspection has been achieved, improving the accuracy of detecting defects in chip manufacturing processes and reducing the consumption of human resources.
Smart Images
Figure CN116485711B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of chip manufacturing, and in particular to a precise chip manufacturing process defect detection method. BACKGROUND
[0002] With the development of artificial intelligence technology, the efficiency of data processing and abnormal phenomenon identification in industrial manufacturing has been greatly improved.
[0003] In integrated circuit chip manufacturing, metal is often used as a conductive material to connect different devices to form a circuit. In very large scale integrated circuits, the quality of the metal layer process and the number and area of defects often have a great impact on the final yield of the chip. In the chip manufacturing industry, after the wafer completes the metal interconnection process, it often needs to be measured in time, and the engineers analyze the measurement data to detect and classify various defects such as particles or scratches in the chip manufacturing process based on the measurement data.
[0004] However, the existing detection and classification methods for chip manufacturing process defects are mostly based on manual methods, which require the experience of detection personnel to detect and classify process defects. This not only consumes a large amount of human resources and is not suitable for large-scale production detection of chips, but also cannot ensure the accuracy of manual detection and classification of chip manufacturing process defects due to the lack of experience of different personnel. SUMMARY
[0005] The technical problem to be solved by the present application is to provide a precise chip manufacturing process defect detection method.
[0006] The technical solution adopted by the present application to solve the above technical problem is: a precise chip manufacturing process defect detection, characterized by comprising the following steps:
[0007] Step 1, constructing a deep separable convolution module for chip manufacturing process defects;
[0008] Step 2, constructing a residual network-based feature extraction module for chip manufacturing process defects;
[0009] Step 3, using the deep separable convolution module to perform feature extraction processing on the input chip picture to obtain a first feature map;
[0010] Step 4, using the residual network-based feature extraction module to perform feature extraction processing on the obtained first feature map to obtain a second feature map;
[0011] Step 5, using the obtained secondary feature map to build a multi-layer UNet++ structure and optimizing the multi-layer UNet++ structure by a feature extraction module based on a residual network, and taking the feature map output by the last layer of the optimized multi-layer UNet++ structure as the chip manufacturing process defect map.
[0012] Further, in the chip manufacturing process defect detection, the construction process of the depth separable convolution module includes the following steps:
[0013] Step a1, using a convolution with a kernel size of 1x1xm as the first convolution, a convolution with a kernel size of 3x3xm as the second convolution, and a convolution with a kernel size of 1x1x6m as the second convolution, wherein m is the total number of layers of the input feature map, the number of convolution kernels with a size of 1x1xm is 6m groups, the number of convolution kernels with a size of 3x3xm is 6m groups, and the number of convolution kernels with a size of 1x1x6m is 3m groups;
[0014] Step a2, using the first convolution to convolve the input feature map, and taking the feature map after the convolution as the first convolution output feature map;
[0015] Step a3, normalizing the obtained first convolution output feature map and activating it using a RELU6 function, and taking the feature map after the activation as the first activation output feature map;
[0016] Step a4, using the second convolution to convolve the first activation output feature map, and taking the feature map after the convolution as the second convolution output feature map;
[0017] Step a5, normalizing the obtained secondary convolution output feature map and activating it using a RELU6 function, and taking the feature map after the activation as the secondary activation output feature map;
[0018] Step a6, using the third convolution to convolve the secondary activation output feature map, and taking the feature map after the convolution as the tertiary convolution output feature map;
[0019] Step a7, normalizing the obtained tertiary convolution output feature map and activating it using a linear activation function, and taking the feature map after the activation as the tertiary activation output feature map; wherein the tertiary activation output feature map is the output feature map of the depth separable convolution module.
[0020] Further, in the chip manufacturing process defect detection, the feature extraction module based on the residual network includes the following steps:
[0021] Step b1, input the feature map to be processed as an input feature map to the deep separable convolution module for convolution processing to obtain a feature map processed by deep separable convolution;
[0022] Step b2, add the feature map to be processed and the obtained feature map processed by deep separable convolution to obtain an added feature map;
[0023] Step b3, perform activation processing on the obtained added feature map by using an activation function, and take the feature map processed by the activation processing as an output feature map of the feature extraction module based on the residual network.
[0024] Optionally, in the chip manufacturing process defect detection, the activation function used in the step b3 is a linear activation function or a nonlinear activation function.
[0025] More preferably, in the chip manufacturing process defect detection, the feature extraction module based on the residual network optimizes the multi-layer UNet++ structure in the following process:
[0026] Step c1, input the initial input feature map to the feature extraction module based on the residual network for feature extraction processing, and take the extracted feature map as a new feature map of the first layer UNet++ structure;
[0027] Step c2, perform maximum pooling sampling processing on the new feature map of the first layer UNet++ structure, and perform interpolation upsampling processing on the feature map processed by the maximum pooling sampling processing, and perform extraction processing on the feature map processed by the sampling processing by the feature extraction module to obtain a first feature map of the second layer UNet++ structure;
[0028] Step c3, perform splicing processing on the first feature map of the second layer UNet++ structure and the new feature map of the first layer UNet++ structure, and take the spliced feature map as a new feature map corresponding to the second layer UNet++ structure;
[0029] Step c4, according to the number of layers of the multi-layer UNet++ structure, sequentially perform maximum pooling sampling processing on the new feature map of the previous layer UNet++ structure, and perform interpolation upsampling processing on the feature map processed by the maximum pooling sampling processing, and perform extraction processing on the feature map processed by the sampling processing by the feature extraction module to obtain a first feature map of the next layer UNet++ structure;
[0030] Step c5, perform splicing processing on the first feature map of the next layer UNet++ structure and the new feature map of the previous layer UNet++ structure, and take the spliced feature map as a new feature map corresponding to the next layer UNet++ structure.
[0031] Compared with the prior art, the chip manufacturing process defect detection method in the application has the advantages that: the chip manufacturing process defect detection method in the application avoids manual participation in the chip manufacturing process defect detection process by constructing a deep separable convolution module and a feature extraction module based on a residual network for chip manufacturing process defects respectively, using the deep separable convolution module to perform feature extraction processing on the input chip picture to obtain a first feature map, using the feature extraction module based on the residual network to perform feature extraction on the first feature map to obtain a second feature map, using the second feature map to build a multi-layer UNet++ structure and using the feature extraction module based on the residual network to optimize the multi-layer UNet++ structure, and using the feature map output by the last layer of the multi-layer UNet++ structure after optimization as a chip manufacturing process defect map, realizes automatic detection, and improves the detection accuracy of process defects. BRIEF DESCRIPTION OF DRAWINGS
[0032] Figure 1 A chip manufacturing process defect detection method flowchart in an embodiment of the application is shown in the figure.
[0033] Figure 2 A multi-layer UNet++ structure diagram in an embodiment of the application is shown in the figure.
[0034] Figure 3 A semiconductor metallization process defect map detected by the chip manufacturing process defect detection method in an embodiment of the application is shown in the figure. DETAILED DESCRIPTION
[0035] The application will be further described in detail below with reference to the accompanying drawings.
[0036] The embodiment provides an accurate chip manufacturing process defect detection method. Figure 1 The accurate chip manufacturing process defect detection method of the embodiment includes the following steps 1-5.
[0037] Step 1: Construct a deep separable convolution module for chip manufacturing process defects.
[0038] Step 2: Construct a feature extraction module based on a residual network for chip manufacturing process defects.
[0039] Step 3: Use the deep separable convolution module to perform feature extraction processing on the input chip picture to obtain a first feature map.
[0040] Step 4: Use the feature extraction module based on the residual network to perform feature extraction processing on the obtained first feature map to obtain a second feature map.
[0041] Step 5, using the obtained secondary feature map to build a multi-layer UNet++ structure and optimizing the multi-layer UNet++ structure by a feature extraction module based on a residual network, and taking the feature map output by the last layer of the optimized multi-layer UNet++ structure as the chip manufacturing process defect map.
[0042] Specifically in this embodiment, the construction process of the deep separable convolution module includes the following steps a1-a7:
[0043] Step a1, using a convolution with a kernel size of 1x1xm as the first convolution, a convolution with a kernel size of 3x3xm as the second convolution, and a convolution with a kernel size of 1x1x6m as the second convolution, wherein m is the total number of layers of the input feature map, the number of convolution kernels with a size of 1x1xm is 6m groups, the number of convolution kernels with a size of 3x3xm is 6m groups, and the number of convolution kernels with a size of 1x1x6m is 3m groups;
[0044] Step a2, using the first convolution to convolve the input feature map, and taking the feature map after the convolution as the primary convolution output feature map;
[0045] Step a3, normalizing the obtained primary convolution output feature map and activating it using a RELU6 function, and taking the feature map after the activation as the primary activation output feature map;
[0046] Step a4, using the second convolution to convolve the primary activation output feature map, and taking the feature map after the convolution as the secondary convolution output feature map;
[0047] Step a5, normalizing the obtained secondary convolution output feature map and activating it using a RELU6 function, and taking the feature map after the activation as the secondary activation output feature map;
[0048] Step a6, using the third convolution to convolve the secondary activation output feature map, and taking the feature map after the convolution as the tertiary convolution output feature map;
[0049] Step a7, normalizing the obtained tertiary convolution output feature map and activating it using a linear activation function, and taking the feature map after the activation as the tertiary activation output feature map; wherein the tertiary activation output feature map is the output feature map of the deep separable convolution module.
[0050] It should be noted that in this embodiment, compared with the traditional convolution module, the deep separable convolution module has less data operation amount and faster operation speed, which is used to improve the network operation efficiency and prevent overfitting phenomenon.
[0051] More specifically, in this embodiment, the above-mentioned feature extraction module based on residual network comprises the following steps b1-b3:
[0052] Step b1, input the to-be-processed feature map as the to-be-input feature map into the deep separable convolution module for convolution processing to obtain a feature map processed by deep separable convolution;
[0053] Step b2, add the to-be-processed feature map and the obtained feature map processed by deep separable convolution to obtain an added feature map;
[0054] Step b3, perform activation processing on the obtained added feature map by using an activation function, and take the feature map processed by the activation processing as the output feature map of the feature extraction module based on residual network. According to needs, the activation function here is a linear activation function or a nonlinear activation function.
[0055] It should be noted that, unlike ordinary convolution network or convolution module, in the feature extraction module based on residual network in this embodiment, the picture or feature map input is added to the picture or feature map output by the convolution module to retain the shallow feature map information, which can reduce the model overfitting phenomenon.
[0056] In addition, referring to FIG. 6, Figure 2 As shown in the figure, in this embodiment, the process of optimizing the multi-layer UNet++ structure by the above-mentioned feature extraction module based on residual network comprises the following c1-c5:
[0057] Step c1, input the initial input feature map into the feature extraction module based on residual network for feature extraction processing, and take the extracted feature map as the new feature map of the first layer UNet++ structure;
[0058] Step c2, perform maximum pooling sampling processing on the new feature map of the first layer UNet++ structure, and perform interpolation upsampling processing on the feature map processed by the maximum pooling sampling processing, and perform extraction processing on the feature map processed by the sampling processing by the feature extraction module to obtain the first feature map of the second layer UNet++ structure;
[0059] Step c3, perform splicing processing on the first feature map of the second layer UNet++ structure and the new feature map of the first layer UNet++ structure, and take the spliced feature map as the new feature map corresponding to the second layer UNet++ structure;
[0060] Step c4, according to the number of layers of the multi-layer UNet++ structure, sequentially performing maximum pooling sampling processing on the new feature map of the previous UNet++ structure, and performing interpolation upsampling processing on the feature map after the maximum pooling sampling processing, and extracting the feature map after the sampling processing through the feature extraction module to obtain the first feature map of the next UNet++ structure;
[0061] Step c5, splicing the first feature map of the next UNet++ structure with the new feature map of the previous UNet++ structure, and taking the spliced feature map as the new feature map of the corresponding next UNet++ structure.
[0062] In this embodiment, by adopting UNet++ as the overall architecture of the network, the depth of the network is improved while ensuring that the information of the shallow network is not ignored, and the operation speed and accuracy of the network are improved.
[0063] Although the preferred embodiments of the present application are described in detail above, it should be clearly understood that the present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. An accurate chip manufacturing process defect detection, characterized by, Comprising the following steps: Step 1, constructing a deep separable convolution module for chip manufacturing process defects; Step 2, constructing a residual network-based feature extraction module for chip manufacturing process defects; Step 3, using the deep separable convolution module to perform feature extraction processing on the input chip picture to obtain a first feature map; Step 4, using the residual network-based feature extraction module to perform feature extraction processing on the obtained first feature map to obtain a second feature map; Step 5, using the obtained second feature map to build a multi-layer UNet++ structure and optimizing the multi-layer UNet++ structure by the residual network-based feature extraction module, and taking the feature map output by the last layer of the optimized multi-layer UNet++ structure as the chip manufacturing process defect map; wherein: In step 4, the residual network-based feature extraction module comprises the following steps: Step b1, inputting the feature map to be processed as the input feature map into the deep separable convolution module for convolution processing to obtain a feature map processed by deep separable convolution; Step b2, adding the feature map to be processed and the obtained feature map processed by deep separable convolution to obtain an added feature map; Step b3, using an activation function to activate the obtained added feature map, and taking the feature map processed by the activation as the output feature map of the residual network-based feature extraction module; In step 5, the residual network-based feature extraction module optimizes the multi-layer UNet++ structure as follows: Step c1, inputting the initial input feature map into the residual network-based feature extraction module for feature extraction processing, and taking the extracted feature map as the new feature map of the first layer UNet++ structure; Step c2, performing maximum pooling sampling processing on the new feature map of the first layer UNet++ structure, and performing interpolation upsampling processing on the feature map processed by maximum pooling sampling, and extracting the feature map processed by sampling through the feature extraction module to obtain the first feature map of the second layer UNet++ structure; Step c3, splicing the first feature map of the second layer UNet++ structure and the new feature map of the first layer UNet++ structure, and taking the spliced feature map as the new feature map corresponding to the second layer UNet++ structure; Step c4, according to the number of layers of the multi-layer UNet++ structure, sequentially performing maximum pooling sampling processing on the new feature map of the previous layer UNet++ structure, and performing interpolation upsampling processing on the feature map processed by maximum pooling sampling, and extracting the feature map processed by sampling through the feature extraction module to obtain the first feature map of the next layer UNet++ structure; Step c5, splicing the first feature map of the next layer UNet++ structure and the new feature map of the previous layer UNet++ structure, and taking the spliced feature map as the new feature map corresponding to the next layer UNet++ structure.
2. The chip manufacturing process defect detection of claim 1, wherein, The construction process of the deep separable convolution module comprises the following steps: Step a1, using a convolution kernel size of 1x1xm as the first convolution, using a convolution kernel size of 3x3xm as the second convolution, and using a convolution kernel size of 1x1x6m as the second convolution, wherein m is the total number of layers of the input feature map, the number of convolution kernels with a size of 1x1xm is 6m groups; the number of convolution kernels with a size of 3x3xm is 6m groups; the number of convolution kernels with a size of 1x1x6m is 3m groups; Step a2, using the first convolution to perform convolution processing on the input feature map, and taking the convolution-processed feature map as a first convolution output feature map; Step a3, performing normalization processing on the obtained first convolution output feature map and using a RELU6 function for activation, and taking the activated feature map as a first activation output feature map; Step a4, using the second convolution to perform convolution processing on the first activation output feature map, and taking the convolution-processed feature map as a second convolution output feature map; Step a5, performing normalization processing on the obtained second convolution output feature map and using a RELU6 function for activation, and taking the activated feature map as a second activation output feature map; Step a6, using the third convolution to perform convolution processing on the second activation output feature map, and taking the convolution-processed feature map as a third convolution output feature map; Step a7, performing normalization processing on the obtained third convolution output feature map and using a linear activation function for activation, and taking the activated feature map as a third activation output feature map; wherein the third activation output feature map is the output feature map of the depth separable convolution module.
3. The chip manufacturing process defect detection of claim 1, wherein, The activation function used in step b3 is a linear activation function or a nonlinear activation function.