Anti-fuse memory

Abstract

The application provides a kind of antifuse memory, the reverse input end of operational amplifier is connected with the feedback end of bias voltage generation module, and the second input end voltage can be obtained according to the feedback end voltage, the second input end is electrically connected with the output end of operational amplifier, and the second input end voltage is used as the bias voltage of reading circuit;The circuit between the second power supply end and the feedback end is equivalent to the circuit between the first power supply end and the monitoring end, the circuit between the feedback end and the adjustable resistance is equivalent to the circuit between the monitoring end and the antifuse memory unit, in this way, the bias voltage generated by bias voltage generation module can effectively provide accurate bias voltage for reading module.After reading module receives bias voltage, if the breakdown resistance value of antifuse memory unit is equal to the adjustable resistance value, the critical voltage of monitoring end is equal to the reverse voltage;According to the state of level signal output by reading module, the relationship between monitoring end voltage and reverse voltage can be judged, and then whether antifuse memory unit is effectively broken down can be judged.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to an antifuse memory. Background Technology

[0002] An antifuse memory is a one-time programmable device (OTP) that can be programmed to store data.

[0003] An antifuse memory includes an antifuse storage cell. When the antifuse storage cell is not broken down, it exhibits a high resistance state. When the antifuse storage cell is broken down, it exhibits a low resistance state. Therefore, the resistance value of the antifuse storage cell can be detected by the reading circuit to determine whether the antifuse storage cell is broken down.

[0004] However, when reading the resistance value of the antifuse memory cell, a more accurate bias voltage is required to accurately measure the breakdown state of the antifuse memory cell. Summary of the Invention

[0005] This application provides an antifuse memory to provide a more accurate bias voltage in order to accurately measure the breakdown state of the antifuse memory cell.

[0006] One embodiment of this application provides an antifuse memory, comprising:

[0007] An antifuse memory array, which contains multiple antifuse memory cells;

[0008] The read module includes a first power supply terminal, a first input terminal, and a monitoring terminal. The first power supply terminal is used to receive a power supply voltage, the first input terminal is used to receive a bias voltage, and the monitoring terminal is connected to the input terminal of the antifuse memory array. The read module is used to output a level signal based on the voltage of the monitoring terminal to characterize the breakdown state of the antifuse memory cell. The level signal has an inverted voltage.

[0009] A bias voltage generation module includes a second power supply terminal, a second input terminal, and a feedback terminal. An adjustable resistor is provided inside the module. The adjustable resistor is used to simulate the critical resistance value after the antifuse memory cell breaks down. The circuit between the second power supply terminal and the feedback terminal is equivalent to the equivalent circuit between the monitoring terminal and the first power supply terminal. The circuit between the feedback terminal and the adjustable resistor is equivalent to the circuit between the monitoring terminal and the antifuse memory cell.

[0010] An operational amplifier has a positive input terminal for receiving a reference voltage equal to the inverted voltage, an inverted input terminal connected to the feedback terminal, an output terminal connected to the second input terminal, and an output voltage serving as the bias voltage.

[0011] In one embodiment, the reading module further includes a reference circuit, one end of which is connected to the monitoring terminal, and the reference circuit is equivalent to the circuit between the monitoring terminal and the antifuse storage unit.

[0012] In one embodiment, the bias voltage generation module includes a first equivalent module connected in series between the second power supply terminal and the feedback terminal. The first equivalent module includes a first equivalent transistor, the drain of the first equivalent transistor is electrically connected to the second power supply terminal, the source is electrically connected to the feedback terminal, and the gate serves as the second input terminal.

[0013] In one embodiment, the first equivalent module includes an equivalent element group connected in series between the first equivalent transistor and the feedback terminal.

[0014] In one embodiment, the equivalent element group includes a second equivalent transistor, a third equivalent transistor, and a fourth equivalent transistor. The drains of the second and third equivalent transistors are electrically connected to the source of the first equivalent transistor, the sources of the second and third equivalent transistors are electrically connected to the drain of the fourth equivalent transistor, and the source of the fourth equivalent transistor is electrically connected to the feedback terminal.

[0015] In one embodiment, the bias voltage generation module includes a second equivalent module connected in series between the feedback terminal and the adjustable resistor.

[0016] In one embodiment, the second equivalent module includes a fifth equivalent transistor and a sixth equivalent transistor, wherein the drain of the fifth equivalent transistor is electrically connected to the feedback terminal, the source of the fifth equivalent transistor is electrically connected to the drain of the sixth equivalent transistor, and the source of the sixth equivalent transistor is electrically connected to the adjustable resistor.

[0017] In one embodiment, it further includes:

[0018] A compensation circuit, which is electrically connected to the feedback terminal of the bias voltage generation module, is used to provide compensation current to the bias voltage generation module.

[0019] In one embodiment, the compensation circuit includes a bandgap reference circuit for providing the compensation current, the magnitude of which is proportional to the absolute temperature.

[0020] In one embodiment, the compensation circuit further includes:

[0021] A current mirror circuit, connected in series between the bandgap reference circuit and the feedback terminal, is used to adjust the compensation current provided by the bandgap reference circuit to provide a correction current that is linearly related to the absolute temperature.

[0022] In one embodiment, the reading module includes a first control module connected in series between the first power supply terminal and the monitoring terminal. The first control module includes a first control transistor, the drain of which is electrically connected to the first power supply terminal, the source of which is electrically connected to the monitoring terminal, and the gate of which serves as the first input terminal.

[0023] In one embodiment, the first control module includes a group of control elements connected in series between the first control transistor and the monitoring terminal.

[0024] In one embodiment, the control element group includes a second control transistor, a third control transistor, and a fourth control transistor. The drains of the second and third control transistors are electrically connected to the source of the first control transistor, the sources of the second and third control transistors are electrically connected to the drain of the fourth control transistor, and the source of the fourth control transistor is electrically connected to the monitoring terminal.

[0025] In one embodiment, the reference circuit includes a fifth control transistor and a sixth control transistor, the drain of the fifth control transistor being electrically connected to the monitoring terminal, and the source of the fifth control transistor being electrically connected to the drain of the sixth control transistor.

[0026] In one embodiment, the antifuse storage array includes a gating module having a first end and a second end, the first end being connected to the monitoring end and the second end being connected to the antifuse storage unit.

[0027] In one embodiment, the gating module includes a plurality of first gating units, a first end of each first gating unit is electrically connected to the monitoring end, a second end of each first gating unit is electrically connected to the first ends of a plurality of second gating units, and a second end of each gating module is electrically connected to an antifuse storage unit.

[0028] The antifuse memory provided in this application includes an antifuse memory array, a read module, a bias voltage generation module, and an operational amplifier. The antifuse memory array includes multiple antifuse memory cells. The read module includes a first power supply terminal, a first input terminal, and a monitoring terminal. The bias voltage generation module includes a second power supply terminal, a second input terminal, and a feedback terminal, and includes an adjustable resistor that simulates the critical resistance value after the antifuse memory cell breaks down. The positive input terminal of the operational amplifier receives a reference voltage equal to the inverted voltage in the level signal output by the read module. The inverting input terminal is connected to the feedback terminal of the bias voltage generation module. Based on the feedback terminal voltage and the resistance value of the adjustable resistor, the bias current of the bias voltage generation module can be obtained, thereby obtaining the voltage at the second input terminal. The second input terminal is electrically connected to the output terminal of the operational amplifier, and the voltage at the second input terminal is equal to the voltage at the output terminal of the operational amplifier. This voltage is used as the bias voltage. Since the circuit between the second power supply terminal and the feedback terminal is equivalent to the equivalent circuit between the monitoring terminal and the first power supply terminal, and the circuit between the feedback terminal and the adjustable resistor is equivalent to the circuit between the monitoring terminal and the antifuse storage cell, after the read module receives the bias voltage, if the breakdown resistance threshold of the antifuse storage cell is equal to the resistance value of the adjustable resistor, then the monitoring terminal has a threshold voltage equal to the reverse voltage. In practice, if the antifuse storage cell is effectively broken down, the actual breakdown resistance is less than the threshold value, the monitoring terminal voltage is pulled down, and the actual monitoring terminal voltage is less than the reverse voltage. If the antifuse storage cell is not effectively broken down, the actual breakdown resistance is greater than the threshold value, the monitoring terminal voltage is raised, and the actual monitoring terminal voltage is greater than the reverse voltage. Based on this, the relationship between the monitoring terminal voltage and the reverse voltage can be determined according to the state of the level signal output by the read module, thereby determining whether the antifuse storage cell has been effectively broken down. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A circuit diagram of an antifuse memory array provided in one embodiment of this application;

[0031] Figure 2 A circuit diagram of a reading module provided in one embodiment of this application;

[0032] Figure 3 A circuit diagram of another reading module provided in one embodiment of this application;

[0033] Figure 4A bias voltage generation circuit diagram provided in one embodiment of this application;

[0034] Figure 5 Another bias voltage generation circuit diagram provided in an embodiment of this application;

[0035] Figure 6 Another bias voltage generation circuit diagram provided in an embodiment of this application;

[0036] Figure 7 A circuit diagram of another antifuse memory array provided in an embodiment of this application.

[0037] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0038] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0039] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the foregoing claims.

[0040] Figure 1 This is a circuit diagram of an antifuse memory array provided in one embodiment of this application. Figure 2 This application provides a circuit diagram of a reading module according to one embodiment. Figure 3 A circuit diagram of another reading module provided in one embodiment of this application; Figure 4 This is a circuit diagram illustrating a bias voltage generation method according to an embodiment of this application. Figures 1-4 As shown, an embodiment of this application provides an antifuse memory, comprising:

[0041] Antifuse memory array 101, which includes multiple antifuse memory cells 1011;

[0042] The reading module 102 includes a first power supply terminal 120, a first input terminal 121, and a monitoring terminal 122. The first power supply terminal 120 is used to receive the power supply voltage, the first input terminal 121 is used to receive the bias voltage, and the monitoring terminal 122 is connected to the input terminal of the antifuse storage array 101. The reading module 102 is used to output a level signal according to the voltage of the monitoring terminal 122 to characterize the breakdown state of the antifuse storage cell 1011. The level signal has an inverted voltage.

[0043] The bias voltage generation module 103 includes a second power supply terminal 130, a second input terminal 131, and a feedback terminal 132. It is equipped with an adjustable resistor R, which is used to simulate the critical resistance value after the anti-fuse storage unit 1011 breaks down. The circuit between the second power supply terminal 130 and the feedback terminal 132 is equivalent to the equivalent circuit between the monitoring terminal 122 and the first power supply terminal 120. The circuit between the feedback terminal 132 and the adjustable resistor R is equivalent to the circuit between the monitoring terminal 122 and the anti-fuse storage unit 1011.

[0044] Operational amplifier 104 has a positive input terminal for receiving a reference voltage equal to the inverting voltage, an inverting input terminal connected to a feedback terminal 132, an output terminal connected to a second input terminal 132, and an output voltage used as a bias voltage.

[0045] refer to Figure 1 As shown, the antifuse memory array 101 includes multiple antifuse memory cells 1011. Each antifuse memory cell 1011 can be a transistor. When a transistor is broken down, it exhibits a low-resistance state, and when it is not broken down, it exhibits a high-resistance state.

[0046] refer to Figure 2As shown, the read module 102 includes a first power supply terminal 120, a first input terminal 121, and a monitoring terminal 122. The monitoring terminal 122 is connected to the input terminal of the antifuse storage array 101, and the circuit between the second power supply terminal 120 and the feedback terminal 132 is equivalent to the circuit between the first power supply terminal 120 and the monitoring terminal 122. The circuit between the feedback terminal 132 and the adjustable resistor R is equivalent to the circuit between the monitoring terminal 122 and the antifuse storage cell 1011. After the read module 102 receives the bias voltage, if the breakdown resistance threshold value of the antifuse storage cell 1011 is equal to the resistance value of the adjustable resistor, then the monitoring terminal 122 has a threshold voltage equal to the reverse voltage. In practice, if the antifuse storage cell 1011 in the antifuse storage array 101 is effectively broken down, the actual breakdown resistance is less than the critical value, the voltage at the monitoring terminal 122 is pulled down, and the actual voltage at the monitoring terminal 122 is less than the reverse voltage. If the antifuse storage cell 1011 in the antifuse storage array 101 is not effectively broken down, the actual breakdown resistance is greater than the critical value, the voltage at the monitoring terminal 122 is raised, and the actual voltage at the monitoring terminal 122 is greater than the reverse voltage. Thus, the relationship between the voltage at the monitoring terminal 122 and the reverse voltage can be determined based on the level signal output by the reading module 102, thereby determining whether the antifuse storage cell 1011 has been effectively broken down.

[0047] Specifically, the reading module 102 includes an inverter 1024. The input terminal of the inverter 1024 is connected to the monitoring terminal 122 and the input terminal of the antifuse storage array 101. After the reading module 102 receives the bias voltage and the supply voltage, if the breakdown resistance of the antifuse storage cell is in a critical state, the input terminal of the inverter 1024 has a critical voltage equal to the inversion voltage. When the antifuse storage cell 1011 in the antifuse storage array 101 is effectively broken down, the actual breakdown resistance of the antifuse storage cell 1011 is less than the breakdown resistance value in the critical state, which pulls down the voltage at the input terminal of the inverter 1024. The inverter 1024 outputs a level signal 1, indicating that the antifuse storage cell 1011 is effectively broken down. When the antifuse storage cell 1011 in the antifuse storage array 101 is not effectively broken down, the actual breakdown resistance of the antifuse storage cell 1011 is greater than the breakdown resistance value in the critical state, which raises the voltage at the input terminal of the inverter 1024 and the inverter 1024 outputs a level signal of 0, indicating that the antifuse storage cell 1011 has not been broken down.

[0048] In some embodiments, reference Figure 2As shown, the reading module 102 includes a first control module 1021, which is connected in series between the first power supply terminal 120 and the monitoring terminal 122. The first control module 1021 includes a first control transistor M0. The drain of the first control transistor M0 is electrically connected to the first power supply terminal 120, and the source is electrically connected to the monitoring terminal 122. The gate serves as the first input terminal 121 of the reading module 102. The first input terminal 121 receives a bias voltage, that is, the gate of the first control transistor M0 receives a bias voltage, and the first control transistor M0 is turned on under the action of the bias voltage.

[0049] The first control module 1021 may include a control element group 1022, which is connected in series between the first control transistor M0 and the monitoring terminal 122. The control element group 1022 may include multiple transistors, as shown in the reference diagram. Figure 2 and Figure 3 As shown, for example, it may include a second control transistor M1, a third control transistor M2 and a fourth control transistor M3, and the first control transistor M0, the second control transistor M1, the third control transistor M2 and the fourth control transistor M3 may all be P-type transistors.

[0050] In some embodiments, the drains of the second control transistor M1 and the third control transistor M2 are electrically connected to the source of the first control transistor M0, the sources of the second control transistor M1 and the third control transistor M2 are electrically connected to the drain of the fourth control transistor M3, and the source of the fourth control transistor M3 is electrically connected to the monitoring terminal 122. It is understood that when the first control transistor M0 is turned on under the action of a bias voltage, it is necessary to control the second control transistor M1, the third control transistor M2, and the fourth control transistor M3 to be turned on simultaneously, so that when the breakdown resistance threshold of the antifuse storage cell 1011 is equal to the adjustable resistance value, the monitoring terminal 122 has a voltage equal to the reverse voltage threshold.

[0051] The reading module 102 may also include a reference circuit 1023, one end of which is connected to the monitoring terminal 122. The reference circuit 1023 is equivalent to the circuit between the monitoring terminal 122 and the antifuse storage unit 1011. Thus, by replicating the reading module 102 and setting an adjustable resistor on the basis of the reading module 102, the bias voltage of the reading module 102 can be accurately obtained. This helps to reduce the design difficulty of the bias voltage generation module 103. In addition, by adjusting the resistance value of the adjustable resistor R to zero, without blowing the antifuse storage unit 1011, the reading module 102 can be used to verify whether the bias voltage generation module 103 and the operational amplifier 104 are working according to the preset conditions, that is, to verify whether the voltage of the monitoring terminal 122 is equal to the reference voltage that the voltage value received at the positive input terminal of the operational amplifier 104 is equal to the inverted voltage.

[0052] Reference circuit 1023 may include multiple transistors, such as a fifth transistor M4 and a sixth transistor M5. The drain of the fifth control transistor M4 is connected to the monitoring terminal 122, and the source of the fifth control transistor M4 is connected to the drain of the sixth control transistor M6. The source of the sixth control transistor M6 may be electrically connected to a third power supply terminal or grounded. The voltage of the third power supply terminal is less than the voltage of the first power supply terminal 120. The fifth control transistor M4 and the sixth control transistor M5 may be N-type transistors. When the second control transistor M1 and the third control transistor M2 are P-type transistors, the gate of the fifth control transistor M4 may be electrically connected to the gate of the third control transistor M2, and the gate of the sixth control transistor M5 may be electrically connected to the gate of the second control transistor M1. Therefore, when the second control transistor M1 and the third control transistor M2 are on, the fifth control transistor M4 and the sixth control transistor M5 are off; when the fifth control transistor M4 and the sixth control transistor M5 are on, the second control transistor M1 and the third control transistor M2 are off. The applicant discovered that the read module 102 requires a relatively accurate bias voltage to detect the breakdown state of the antifuse storage cell 1011, therefore, a bias voltage generation module 103 was set up, referring to... Figure 4 As shown, the bias voltage generation module 103 includes a second power supply terminal 130, a second input terminal 131, and a feedback terminal 132. An adjustable resistor R is provided within it. The adjustable resistor R simulates the critical resistance value after the antifuse storage cell 1011 breaks down. Since the characteristics of different antifuses may differ, setting an adjustable resistor R facilitates timely adjustment and ensures the equivalent relationship when testing different antifuse storage cells 1011. The circuit between the second power supply terminal 130 and the feedback terminal 132 of the bias voltage generation module 103 is equivalent to the equivalent circuit between the monitoring terminal 122 and the first power supply terminal 120. The circuit between the feedback terminal 132 and the adjustable resistor R is equivalent to the circuit between the monitoring terminal 122 and the antifuse storage cell 1011. Therefore, the bias voltage generation module 103 is equivalent to a portion of the circuit in the reading module 102 and a portion of the circuit in the antifuse storage array 101, thereby generating an accurate bias voltage.

[0053] refer to Figure 4As shown, the feedback terminal 132 of the bias voltage generation module 103 is connected to the inverting input terminal of the operational amplifier 104. The non-inverting input terminal of the operational amplifier 104 is used to receive a reference voltage that is equal to the inverted voltage in the level signal output by the reading module 102. When the operational amplifier 104 has a large gain, it can be approximately considered that the voltages at the non-inverting and inverting input terminals of the operational amplifier 104 are equal. That is, after the non-inverting input terminal of the operational amplifier 104 receives a reference voltage equal to the inverted voltage, the voltage at its inverting input terminal is also the reference voltage, and the voltage at the feedback terminal 132 is also the reference voltage. Then, the bias current of the bias voltage generation module 103 is obtained based on the voltage at feedback terminal 132 and the resistance value of the adjustable resistor R connected to feedback terminal 132. The voltage at the second input terminal 131 is obtained based on the bias current, the resistance of the component between the second input terminal 131 and the adjustable resistor R, and the adjustable resistor R itself. Since the output terminal of operational amplifier 104 is connected to the second input terminal 131, the voltage at the output terminal can be obtained and used as the bias voltage. The positive input terminal of operational amplifier 104 can also be connected to the reference voltage generation module 105. Figure 5 As shown, the reference voltage generation module 105 is used to generate a reference voltage equal to the reverse voltage.

[0054] In some embodiments, reference Figure 5 As shown, the bias voltage generation module 103 includes a first equivalent module 1031, connected in series between the second power supply terminal 130 and the feedback terminal 132. The first equivalent module 1031 is equivalent to the circuit between the first power supply terminal 120 and the monitoring terminal 122 in the reading module 102, that is, the first equivalent module 1031 is equivalent to the first control module 1021. The first equivalent module 1031 includes a first equivalent transistor M01, which is equivalent to a first control transistor M0. The drain of the first equivalent transistor M01 is electrically connected to the second power supply terminal 130, the source is electrically connected to the feedback terminal 132, and the gate serves as the second input terminal 131. After obtaining the bias current of the bias voltage generation module 103, the source terminal voltage of the first equivalent transistor M01 can be obtained according to the components between the first equivalent transistor M01 and the adjustable resistor R and the resistance value of the adjustable resistor R. Then, the gate terminal voltage of the first equivalent transistor M01 can be obtained according to the turn-on voltage and the source terminal voltage of the first equivalent transistor M01. The gate terminal voltage is the voltage of the second input terminal 131, which is the output terminal voltage of the operational amplifier, i.e., the bias voltage.

[0055] refer to Figure 5 and Figure 6As shown, the first equivalent module 1031 may include an equivalent element group 1032, which is connected in series between the first equivalent transistor M01 and the feedback terminal 132. The equivalent element group 1032 is equivalent to the circuit elements between the first control transistor M0 and the monitoring terminal 122, i.e., equivalent to the control element group 1022. The equivalent element group 1032 includes other elements, which may be equivalent to the resistors of the transistors in the read module 102, and these resistors are used to read the source-drain voltage drop of the transistors in the read module 102. The equivalent element group 1032 may include, for example, multiple transistors, such as a second equivalent transistor M11, a third equivalent transistor M21, and a fourth equivalent transistor M31. In this case, the second equivalent transistor M11 is equivalent to the second control transistor M1, the third equivalent transistor M21 is equivalent to the third control transistor M2, and the fourth equivalent transistor M31 is equivalent to the fourth equivalent transistor M3. The drains of the second equivalent transistor M11 and the third equivalent transistor M21 are electrically connected to the source of the first equivalent transistor M01. The sources of the second equivalent transistor M11 and the third equivalent transistor M21 are electrically connected to the drain of the fourth equivalent transistor M31. The source of the fourth equivalent transistor M31 is electrically connected to the feedback terminal 132.

[0056] The bias voltage generation module 103 may further include a second equivalent module 1033 connected in series between the feedback terminal 132 and the adjustable resistor R. The second equivalent module 1033 is equivalent to the reference circuit 1023 in the readout circuit 101. In some embodiments, the second equivalent module 1033 may include a fifth equivalent transistor M41 and a sixth equivalent transistor M51. The fifth equivalent transistor M41 is equivalent to a fifth control transistor M4, and the sixth equivalent transistor M51 is equivalent to a sixth control transistor M5. The drain of the fifth equivalent transistor M41 is electrically connected to the feedback terminal 132, the source of the fifth equivalent transistor M41 is electrically connected to the source of the sixth equivalent transistor M51, and the drain of the sixth equivalent transistor M51 is electrically connected to the adjustable resistor R.

[0057] Since the circuit between the second power supply terminal 130 and the feedback terminal 132 of the bias voltage generation module 103 is equivalent to the circuit between the monitoring terminal 122 and the first power supply terminal 120, and the circuit between the feedback terminal 132 and the adjustable resistor R is equivalent to the circuit between the monitoring terminal 122 and the antifuse storage cell 1011, and the adjustable resistor R simulates the critical resistance value after the antifuse storage cell breaks down, the voltage of the feedback terminal 132 is a reference voltage equal to the reverse voltage, thus an accurate bias voltage can be generated.

[0058] The applicant discovered that, due to the temperature characteristics of the adjustable resistor, its resistance value varies at different temperatures, resulting in different bias voltages. This could affect the accuracy of detecting the breakdown state of antifuse memory cells. For example, during high-temperature testing, the bias current Ires is I1, and the generated bias voltage is vfsread1. The adjustable resistor R simulates the breakdown resistance range of the antifuse memory array as R1. Due to the temperature characteristics of the adjustable resistor R, during low-temperature testing, the resistance value of the adjustable resistor R decreases, the bias current is I2 and I2 > I1, and the generated bias voltage is vfsread2 and vfsread2 is less than vfsread1. The adjustable resistor R simulates the breakdown resistance range of the antifuse memory array as R2, and R2 > R1. This could lead to antifuse memory arrays with resistance values ​​greater than R1 being mistakenly identified as broken down. Therefore, compensation circuit 106 was added, referencing... Figure 6 As shown, the adjustable resistor compensates for the resistance change caused by temperature, thereby enabling the bias voltage generation module 103 to generate a stable bias voltage.

[0059] The compensation circuit 106 is electrically connected to the feedback terminal 132 of the bias voltage generation module 103, and is used to provide a compensation current Icom to the bias voltage generation module 103. A new bias voltage can be obtained through the compensation current Icom and the bias current Ires. The compensation current provided by the compensation circuit 106 is different when performing tests at different temperatures. For example, when performing a high-temperature test, the bias current is I1, and with the addition of the compensation current Icom1, the total bias current is I1 + Icom1; when performing a low-temperature test, the bias current is I2, and with the addition of the compensation current Icom2, the total bias current is I2 + Icom2. Since I1 > I2 and Icom1 < Icom2, the difference between I1 + Icom1 and I2 + Icom2 is small, resulting in a smaller difference between their bias voltages, thereby reducing the influence of resistor temperature on the bias voltage.

[0060] In some embodiments, the compensation circuit 106 includes a bandgap reference circuit 1061, which provides a compensation current that is proportional to the absolute temperature. In other words, the bandgap reference circuit 1061 provides a current that is proportional to the absolute temperature (PTAT) to reduce the effect of the resistor temperature on the bias voltage.

[0061] The compensation circuit 106 may also include a current mirror circuit 1062, which is connected in series between the bandgap reference circuit 1061 and the feedback terminal 132 of the bias voltage generation module 103. The current mirror circuit 1062 is used to adjust the compensation current provided by the bandgap reference circuit 1061 to provide a correction current that is linearly related to the absolute temperature. Thus, after the bandgap reference circuit 1061 provides a current that is proportional to the absolute temperature, the current mirror circuit 1062 adjusts the current value of the bias voltage generation module 103.

[0062] In some embodiments, reference Figure 7 As shown, the antifuse storage array 101 may further include a gating module 1012. The first end of the gating module 1012 is electrically connected to the monitoring end 122 of the reading module 102, and the second end of the gating module 1012 is electrically connected to a plurality of antifuse storage cells 1011. The gating module 1012 is used to control the conduction of the antifuse storage cells 1011 in the breakdown state to be detected. The gating module 1012 is equivalent to the reference circuit 1023 in the reading module 102.

[0063] In one embodiment, the gating module 1012 may include a plurality of first gating units 1013. The first end of each first gating unit 1013 is electrically connected to the monitoring end 122, and the second end of each first gating unit 1013 is electrically connected to the first ends of a plurality of second gating units 1014. The second end of each second gating unit 1014 is electrically connected to an antifuse storage unit 1011. Then, a first gating unit 1013 and a second gating unit 1014 can control an antifuse storage array 1011 to conduct, thereby detecting the breakdown state of an antifuse storage array 1011. Then, a first gating unit 1013 and a second gating unit 1014 are equivalent to the reference circuit 1023 in the read module 102. The first gating unit 1013 is equivalent to the fifth control transistor M4, and the second gating unit 1014 is equivalent to the sixth control transistor M5. That is, the first gating unit 1013 and the second gating unit 1014 can be transistors, such as N-type transistors.

[0064] It should be noted that this disclosure does not limit the number of gating units connected in series between the antifuse storage unit 1011 and the monitoring terminal in the gating module 1012, nor does it limit the type of gating units. Accordingly, the circuit in the reference circuit 1023 can be adjusted according to the number and type of gating units connected in series in the gating module 1012.

[0065] In the above technical solution, the positive input terminal of the operational amplifier receives a reference voltage equal to the inverted voltage, and the inverting input terminal is connected to the feedback terminal of the bias voltage generation module. When the operational amplifier is in a stable state, the voltage at the inverting input terminal is equal to the voltage at the positive input terminal, thus making the voltage at the feedback terminal equal to the reference voltage. Therefore, the bias voltage of the bias voltage generation module is obtained using the adjustable resistor and the reference voltage, thereby obtaining the voltage at the output terminal connected to the first input terminal, i.e., the bias voltage. Since the circuit between the second power supply terminal and the feedback terminal of the bias voltage generation module is equivalent to the circuit between the monitoring terminal and the first power supply terminal, and the circuit between the feedback terminal and the adjustable resistor is equivalent to the circuit between the monitoring terminal and the antifuse, and the adjustable resistor simulates the critical resistance value after the antifuse breaks down, an accurate bias voltage is obtained. After the bias voltage is input to the first input terminal of the reading module, the reading module is turned on. After receiving the power supply voltage at the first power supply terminal of the reading module, if the breakdown resistance critical value of the antifuse storage cell is equal to the resistance value of the adjustable resistor, the monitoring terminal of the reading module has a critical voltage equal to the reverse voltage. The reading module outputs a level signal through the monitoring terminal voltage. The state of the level signal can reflect the relationship between the monitoring terminal voltage and the reverse voltage, thereby determining whether the antifuse storage cell has been effectively broken down.

[0066] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An antifuse memory, characterized in that, include: An antifuse memory array, which contains multiple antifuse memory cells; The read module includes a first power supply terminal, a first input terminal, and a monitoring terminal. The first power supply terminal is used to receive a power supply voltage, the first input terminal is used to receive a bias voltage, and the monitoring terminal is connected to the input terminal of the antifuse memory array. The read module is used to output a level signal based on the voltage of the monitoring terminal to characterize the breakdown state of the antifuse memory cell. The level signal has an inverted voltage. A bias voltage generation module includes a second power supply terminal, a second input terminal, and a feedback terminal. An adjustable resistor is provided inside the module. The adjustable resistor is used to simulate the critical resistance value after the antifuse storage cell breaks down. The circuit between the second power supply terminal and the feedback terminal is equivalent to the circuit between the monitoring terminal and the first power supply terminal. The circuit between the feedback terminal and the adjustable resistor is equivalent to the circuit between the monitoring terminal and the antifuse storage cell. An operational amplifier has a positive input terminal for receiving a reference voltage equal to the inverted voltage, an inverted input terminal connected to the feedback terminal, an output terminal connected to the second input terminal, and an output voltage serving as the bias voltage.

2. The antifuse memory according to claim 1, characterized in that, The reading module further includes a reference circuit, one end of which is connected to the monitoring terminal. The reference circuit is equivalent to the circuit between the monitoring terminal and the antifuse storage unit.

3. The antifuse memory according to claim 1, characterized in that, The bias voltage generation module includes a first equivalent module connected in series between the second power supply terminal and the feedback terminal. The first equivalent module includes a first equivalent transistor. The drain of the first equivalent transistor is electrically connected to the second power supply terminal, the source is electrically connected to the feedback terminal, and the gate serves as the second input terminal.

4. The antifuse memory according to claim 3, characterized in that, The first equivalent module includes an equivalent element group connected in series between the first equivalent transistor and the feedback terminal.

5. The antifuse memory according to claim 4, characterized in that, The equivalent element group includes a second equivalent transistor, a third equivalent transistor, and a fourth equivalent transistor. The drains of the second and third equivalent transistors are electrically connected to the source of the first equivalent transistor. The sources of the second and third equivalent transistors are electrically connected to the drain of the fourth equivalent transistor. The source of the fourth equivalent transistor is electrically connected to the feedback terminal.

6. The antifuse memory according to claim 1, characterized in that, The bias voltage generation module includes a second equivalent module, which is connected in series between the feedback terminal and the adjustable resistor.

7. The antifuse memory according to claim 6, characterized in that, The second equivalent module includes a fifth equivalent transistor and a sixth equivalent transistor. The drain of the fifth equivalent transistor is electrically connected to the feedback terminal, the source of the fifth equivalent transistor is electrically connected to the drain of the sixth equivalent transistor, and the source of the sixth equivalent transistor is electrically connected to the adjustable resistor.

8. The antifuse memory according to claim 1, characterized in that, Also includes: A compensation circuit, which is electrically connected to the feedback terminal of the bias voltage generation module, is used to provide compensation current to the bias voltage generation module.

9. The antifuse memory according to claim 8, characterized in that, The compensation circuit includes a bandgap reference circuit, which provides the compensation current, the magnitude of which is proportional to the absolute temperature.

10. The antifuse memory according to claim 9, characterized in that, The compensation circuit further includes: A current mirror circuit, connected in series between the bandgap reference circuit and the feedback terminal, is used to adjust the compensation current provided by the bandgap reference circuit to provide a correction current that is linearly related to the absolute temperature.

11. The antifuse memory according to claim 1, characterized in that, The reading module includes a first control module connected in series between the first power supply terminal and the monitoring terminal. The first control module includes a first control transistor, the drain of which is electrically connected to the first power supply terminal, the source of which is electrically connected to the monitoring terminal, and the gate of which serves as the first input terminal.

12. The antifuse memory according to claim 11, characterized in that, The first control module includes a control element group connected in series between the first control transistor and the monitoring terminal.

13. The antifuse memory according to claim 12, characterized in that, The control element group includes a second control transistor, a third control transistor, and a fourth control transistor. The drains of the second and third control transistors are electrically connected to the source of the first control transistor, the sources of the second and third control transistors are electrically connected to the drain of the fourth control transistor, and the source of the fourth control transistor is electrically connected to the monitoring terminal.

14. The antifuse memory according to claim 2, characterized in that, The reference circuit includes a fifth control transistor and a sixth control transistor. The drain of the fifth control transistor is electrically connected to the monitoring terminal, and the source of the fifth control transistor is electrically connected to the drain of the sixth control transistor.

15. The antifuse memory according to claim 1, characterized in that, The antifuse storage array includes a gate module, which has a first end and a second end. The first end is connected to the monitoring end, and the second end is connected to the antifuse storage unit.

16. The antifuse memory according to claim 15, characterized in that, The gating module includes multiple first gating units. The first end of each first gating unit is electrically connected to the monitoring end. The second end of each first gating unit is electrically connected to the first ends of multiple second gating units. The second end of each gating module is electrically connected to an antifuse storage unit.

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