A dynamic random access memory test method, system, device and storage medium

Abstract

The present application discloses a dynamic random access memory test method, system, device and storage medium, wherein the method comprises the following steps: in response to a chip test instruction input by a user, sending serial port data to a device end so that the device end parses the serial port data so that the device end runs a test program and sends feedback information; and displaying the chip test status according to the feedback information. The present application can shorten the test time and improve the test capacity. The present application can be widely used in the field of memory chip test technology.

Description

Technical Field

[0001] The present application relates to the field of memory chip testing technology, and in particular to a dynamic random access memory testing method, system, device and storage medium. Background Art

[0002] In the prior art, for chip testing, a hardware circuit is often used to perform specific tests on the chip through the built hardware circuit, and the test status and test results of the chip are displayed through display devices in the circuit, such as display screens and LED lights. However, this method has the following two defects that need to be solved: first, the hardware circuit has poor adaptability, and for different models or different series of chips, the hardware circuit needs to be constantly changed; second, the display logic of the display screen and the LED light also needs to be changed accordingly, resulting in a relatively long test time, which affects the test capacity. Therefore, a new dynamic random access memory test method is urgently needed. Summary of the invention

[0003] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of an embodiment of the present application is to provide a dynamic random access memory testing method, system, device and storage medium, which can shorten the testing time and improve the testing capacity.

[0005] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present application include:

[0006] In response to a chip test instruction input by a user, the serial port data is sent to the device end, so that the device end parses the serial port data, so that the device end runs a test program and sends feedback information;

[0007] According to the feedback information, the chip test status is displayed.

[0008] In addition, the method for testing a dynamic random access memory according to the above embodiment of the present invention may also have the following additional technical features:

[0009] Furthermore, in an embodiment of the present application, the test chip instructions include at least a test algorithm determination instruction, a test number determination instruction, and a capacity determination instruction for the dynamic random access memory to be tested.

[0010] Further, in an embodiment of the present application, the serial port data includes multiple sub-data, and the step of parsing the serial port data on the device side specifically includes: for any serial data, determining that the first data received of the serial port data is '#' and the second data is 'M', and determining that the data received between the start character and the end character of the first sub-data is 1, then determining that the program running on the device side is the test program corresponding to the chip test instruction input by the user; determining that the first data received between the start character and the end character of the second sub-data is the first preset character, then determining the test capacity of the chip; determining that the previous character of the end character between the start character and the end character of the second sub-data is the second preset character, then determining the target number of chip tests.

[0011] Furthermore, in an embodiment of the present application, the serial port data includes multiple sub-data, and the step of the device side parsing the serial port data specifically includes: if it is determined that the first data received from the serial port data is not '#' or the second data is not 'M', the device side stops parsing the current serial port data.

[0012] Further, in an embodiment of the present application, the preset characters include numbers or English characters, and the step of determining that the first data received between the start character and the end character of the second sub-data is the first preset character, then determining the test capacity of the chip specifically includes: determining that the first data received between the start character and the end character of the second sub-data is a number, then determining the test capacity of the chip as the sum of a preset multiple of the number of tests corresponding to the number and the user input capacity; determining that the first data received between the start character and the end character of the second sub-data is an English character, and determining the test capacity of the chip as the test capacity corresponding to the English character.

[0013] Further, in an embodiment of the present application, the step of determining the previous character of the end character between the start character and the end character of the second sub-data is a second preset character, then determining the target test number of the chip specifically includes: determining that the previous character of the end character between the start character and the end character of the second sub-data is a number, then determining the target test number of the chip for this test to be the sum of a preset multiple of the numerical value corresponding to the number and the number of user inputs received.

[0014] Furthermore, in an embodiment of the present application, the step of displaying the chip test status according to the feedback information specifically includes: determining that the feedback information is a heartbeat packet, then determining that the chip test status is a first state, and the first state is used to characterize that the chip test status is under testing.

[0015] On the other hand, an embodiment of the present application further provides a dynamic random access memory test system, comprising:

[0016] A sending module, used for sending serial port data to a device end in response to a chip test instruction input by a user, so that the device end can parse the serial port data, run a test program, and send feedback information;

[0017] The display module is used to display the chip test status according to the feedback information.

[0018] On the other hand, the present application also provides a dynamic random access memory test device, comprising:

[0019] at least one processor;

[0020] at least one memory for storing at least one program;

[0021] When the at least one program is executed by the at least one processor, the at least one processor implements a dynamic random access memory testing method as described in any one of the invention contents.

[0022] In addition, the present application also provides a storage medium, in which processor-executable instructions are stored. When the processor-executable instructions are executed by the processor, they are used to execute a dynamic random access memory testing method as described in any of the above items.

[0023] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0024] This application can test different chips based on the instructions input by the user. The host computer can send serial port data to the device side, and the device side can parse the serial port data, and then run the test program and send feedback information based on the analysis results. The host computer can display the test status based on the feedback information chip; through the interaction between the host computer and the device side, the chip test can be implemented through the instructions on the user side, and the test status can be fed back to the user side. The host computer feeds back the test results to the user side. This application can shorten the test time and improve the test capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the steps of a dynamic random access memory testing method in a specific embodiment of the present invention;

[0026] Figure 2 This is a display interface diagram of a test state in a specific embodiment of the present invention;

[0027] Figure 3 A display interface diagram for inputting chip test instructions in a specific embodiment of the present invention;

[0028] Figure 4It is a structural schematic diagram of a dynamic random access memory test system in a specific embodiment of the present invention;

[0029] Figure 5 The figure is a schematic diagram of the structure of a dynamic random access memory testing device in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings to illustrate the principles and processes of the dynamic random access memory testing method, system, device and storage medium in the embodiments of the present invention.

[0031] Reference Figure 1 The present invention provides a dynamic random access memory testing method for testing a memory chip, comprising the following steps:

[0032] S1. In response to a chip test instruction input by a user, serial port data is sent to a device end, so that the device end parses the serial port data, so that the device end runs a test program and sends feedback information;

[0033] S2. Display chip test status according to the feedback information.

[0034] In this embodiment, in response to the chip test instructions input by the user, the host computer sends serial port data to the device end, the device end receives the serial port data from the host computer and parses it, and after the analysis, the device end runs the test program and sends feedback information to the host computer. The host computer can display the test status of the chip based on the feedback information. The test status of the chip can be one of the three states: testing, test success, and test failure; and the chip test instructions may include but are not limited to test instructions for determining the test algorithm, the number of tests, and the test capacity.

[0035] Further, in some embodiments of the present application, the test chip instruction may at least include a test algorithm determination instruction, a test number determination instruction and a capacity determination instruction for the dynamic random access memory to be tested; in the present embodiment, the test may include a test algorithm determination instruction, a test number determination instruction and a capacity determination instruction for the dynamic random access memory to be tested, the test algorithm determination instruction may be a plurality of preset test algorithms, the test number determination instruction may be the number of tests specifically executed by the subsequent device end, and the number of tests specifically executed by the subsequent device end may also be a number corresponding to a certain mathematical relationship with the test number determination instruction, the capacity determination instruction for the dynamic random access memory to be tested may be the test capacity specifically executed by the subsequent device end, and the test capacity specifically executed by the subsequent device end may also be a capacity corresponding to a certain mathematical relationship with the test capacity determination instruction.

[0036] Further, in some embodiments of the present application, the step of parsing the serial port data on the device side may specifically include:

[0037] S12, for any serial data, when it is determined that the first data of the serial port data received is '#' and the second data is 'M', and when it is determined that the data received between the start character and the end character of the first sub-data is 1, it is determined that the program running on the device side is the test program corresponding to the chip test instruction input by the user;

[0038] S13, determining that the first received data between the start character and the end character of the second sub-data is the first preset character, and then determining the test capacity of the chip;

[0039] S14, determining that the character before the end character between the start character and the end character of the second sub-data is a second preset character, and then determining the target number of chip tests;

[0040] In this embodiment, the serial port data may include the first data, the second data and one or more sub-data. The first data may be the first data transmitted through the serial protocol, and the sub-data may be a string of data consisting of a start character and an end character. In this embodiment, it can be determined that the first data received from the serial port data is '#' and then the second data is 'M', and then the data received between the start character and the end character of the first sub-data is 1. When the above three conditions are met, it is determined that the program running on the device side is the test program corresponding to the chip test instruction input by the user; for the second sub-data, it can be determined that the first data received between the start character and the end character of the second sub-data is the first preset character, and then the test capacity of the chip is determined; then it is determined that the previous character of the end character between the start character and the end character of the second sub-data is the second preset character, and then the target number of chip tests is determined.

[0041] Furthermore, in some embodiments of the present application, the serial port data includes a plurality of sub-data, and the step of the device side parsing the serial port data may further include:

[0042] If it is determined that the first data of the received serial port data is not '#' or the second data is not 'M', the device stops parsing the current serial port data;

[0043] Specifically, when it is determined that the first data of the received serial port data is not '#' or the second data is not 'M', the device stops parsing the current serial port data until the next serial port data is '#' and the second data is 'M'.

[0044] Further, in some embodiments of the present application, the preset characters may include numbers or English characters, and the step of determining that the first received data between the start character and the end character of the second sub-data is the first preset character, and determining the test capacity of the chip may specifically include:

[0045] Determine that the first data received between the start character and the end character of the second sub-data is a number, and then determine that the test capacity of the chip is the sum of a preset multiple of the number of tests corresponding to the number and the user input capacity;

[0046] Determine that the first received data between the start character and the end character of the second sub-data is an English character, and determine that the test capacity of the chip is the test capacity corresponding to the English character;

[0047] Specifically, if the received data is within the range of >='0'&&<='9', the test capacity = test capacity*10+received data, and other data are not processed. Until the end symbol '#' is received, if the previous character of the end symbol '#' is 'G' or 'g' or 'K' or 'k' or 'B' or 'b', the capacity needs to be converted, and then the subsequent data can be received.

[0048] Further, the step of determining that the character before the end character between the start character and the end character of the second sub-data is a second preset character, then determining the number of target chip tests specifically includes: determining that the character before the end character between the start character and the end character of the second sub-data is a number, then determining the number of target chip tests for this test to be the sum of a preset multiple of the numerical value corresponding to the number and the number of times input by the user received;

[0049] Specifically, if the received data is a value within the range of >='0' &&<='9', the number of tests = number of tests*10+received data, and other data are not processed until the end symbol '#' is received.

[0050] Further, in some embodiments of the present application, the step of displaying the chip test status according to the feedback information may specifically include:

[0051] Determining that the feedback information is a heartbeat packet, determining that the chip test state is a first state, the first state is used to indicate that the chip test state is under testing;

[0052] Specifically, refer to Figure 2ac diagram, in this embodiment, if the host computer determines that the feedback information is a heartbeat packet, it can determine that the chip test state is the first state, and the first state is used to characterize that the chip test state is testing. If it is determined that the chip test fails, the host computer can display a test success or a test failure interface, and remind the user of the chip test result through different interface display contents; Figure 2 The AC can display different test status display interfaces, and the test results of the chip can be determined through different display interfaces.

[0053] Specifically, the method of this application is as follows:

[0054] Reference Figure 3 , Step 1, the user selects different test algorithms, sets the number of tests and capacity through the host computer, and the host computer sends data to the device through the serial port; Figure 3 It can be seen that the interface of the host computer can select different test algorithms, such as "stuck adress", "compare and", etc. The column corresponding to time can display the number of tests, and the column corresponding to capacity can display the test capacity.

[0055] Step 2: The device receives and parses the data;

[0056] Determine whether the first data received is '#' and whether the next data is 'M'. If so, receive and parse the subsequent data; if not, continue to wait for receiving data until the conditions are met;

[0057] When the received data is 1, the test algorithm is selected by default; if the received data is 0, the test algorithm is not selected; other characters are ignored and not processed until the end symbol '#' is received; the received 0 and 1 data are stored in a one-dimensional array in sequence.

[0058] Continue to receive data. If the received data is >='0' && <='9', the test capacity = test capacity * 10 + received data, and other data will not be processed. Until the end symbol '#' is received, if the previous character of the end symbol '#' is 'G' or 'g' or 'K' or 'k' or 'B' or 'b', the capacity needs to be converted; specifically, it is converted to the ASCII code value corresponding to 'G' or 'g' or 'K' or 'k' or 'B' or 'b'.

[0059] Continue to receive data. If the received data is a value >= '0' && <= '9', the number of tests = number of tests * 10 + received data. Other data will not be processed until the end symbol '#' is received.

[0060] If the '#' character is received and the next character is 'E', the entire data reception and parsing ends;

[0061] Step 3: The device runs the corresponding test program according to the parsed data;

[0062] Step 4: The device will feed back the test results to the host computer in real time. During the test, the device will send heartbeat packets to the host computer, and after the test is completed, the test results will be fed back to the host computer and displayed.

[0063] In addition, refer to Figure 4 ,and Figure 1 Corresponding to the method, an embodiment of the present application also provides a dynamic random access memory test system, including: a sending module 101 and a display module 102; wherein the sending module 101 can be used to respond to a chip test instruction input by a user, send serial port data to a device end, so that the device end parses the serial port data, so that the device end runs a test program and sends feedback information; the display module 102 can be used to display the chip test status according to the feedback information.

[0064] The contents of the above-mentioned dynamic random access memory test method embodiment are all applicable to the test system embodiment of the present dynamic random access memory. The functions specifically implemented by the test system embodiment of the present dynamic random access memory are the same as those of the above-mentioned dynamic random access memory test method embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned dynamic random access memory test method embodiment.

[0065] and Figure 1 Corresponding to the method, the embodiment of the present application also provides a dynamic random access memory test device, the specific structure of which can be referred to Figure 5 ,include:

[0066] at least one processor;

[0067] at least one memory for storing at least one program;

[0068] When the at least one program is executed by the at least one processor, the at least one processor implements the dynamic random access memory testing method.

[0069] The contents of the above method embodiments are all applicable to the present device embodiments. The functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0070] and Figure 1Corresponding to the method, an embodiment of the present application further provides a storage medium, in which processor-executable instructions are stored. When the processor-executable instructions are executed by the processor, they are used to execute the dynamic random access memory testing method.

[0071] The contents of the above-mentioned dynamic random access memory test method embodiment are all applicable to the present storage medium embodiment. The functions specifically implemented by the present storage medium embodiment are the same as those of the above-mentioned dynamic random access memory test method embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned dynamic random access memory test method embodiment.

[0072] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the application is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are expected, wherein the order of various operations is changed and the sub-operation described as a part of a larger operation is performed independently.

[0073] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present application. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional techniques of the engineer. Therefore, those skilled in the art can implement the present application set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the attached claims and their equivalents.

[0074] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several programs to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0075] The logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable programs for implementing the logical functions, and may be embodied in any computer-readable medium for use by a program execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch and execute a program from a program execution system, device or apparatus), or in conjunction with such program execution systems, devices or apparatuses. For purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by a program execution system, device or apparatus, or in conjunction with such program execution systems, devices or apparatuses.

[0076] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0077] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0078] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0079] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0080] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A method for testing a dynamic random access memory, characterized in that: Used to test memory chips, including the following steps: In response to a chip test instruction input by a user, serial port data is sent to a device end so that the device end parses the serial port data, so that the device end runs a test program and sends feedback information; the serial port data includes a plurality of sub-data, and the step of the device end parsing the serial port data specifically includes: For any serial data, when it is determined that the first data received from the serial port data is '#' and the second data is 'M', and when it is determined that the data received between the start character and the end character of the first sub-data is 1, it is determined that the program running on the device side is the test program corresponding to the chip test instruction input by the user; Determine that the first received data between the start character and the end character of the second sub-data is the first preset character, and then determine the test capacity of the chip; Determine that the character before the end character between the start character and the end character of the second sub-data is the second preset character, and then determine the target test times of the chip; According to the feedback information, the chip test status is displayed.

2. A method for testing a dynamic random access memory according to claim 1, characterized in that: The test chip instructions at least include a test algorithm determination instruction, a test number determination instruction and a capacity determination instruction of a dynamic random access memory to be tested.

3. A method for testing a dynamic random access memory according to claim 1, characterized in that: The serial port data includes a plurality of sub-data, and the step of parsing the serial port data by the device end specifically includes: If it is determined that the first data of the received serial port data is not '#' or the second data is not 'M', the device stops parsing the current serial port data.

4. A method for testing a dynamic random access memory according to claim 1, characterized in that: The preset characters include numbers or English characters, and the step of determining that the first received data between the start character and the end character of the second sub-data is the first preset character, then determining the test capacity of the chip specifically includes: Determine that the first data received between the start character and the end character of the second sub-data is a number, and then determine that the test capacity of the chip is the sum of a preset multiple of the number of tests corresponding to the number and the user input capacity; It is determined that the first data received between the start character and the end character of the second sub-data is an English character, and the test capacity of the chip is determined to be the test capacity corresponding to the English character.

5. A method for testing a dynamic random access memory according to claim 1, characterized in that: The step of determining that the character before the end character between the start character and the end character of the second sub-data is the second preset character and then determining the target number of chip tests specifically includes: If it is determined that the character before the end character between the start character and the end character of the second sub-data is a number, the target number of chip tests for this test is determined to be the sum of a preset multiple of the numerical value corresponding to the number and the number of user inputs received.

6. A method for testing a dynamic random access memory according to claim 1, characterized in that: The step of displaying the chip test status according to the feedback information specifically includes: If it is determined that the feedback information is a heartbeat packet, then it is determined that the chip test state is a first state, and the first state is used to indicate that the chip test state is under testing.

7. A dynamic random access memory test system, characterized in that: include: A sending module, used for sending serial port data to a device end in response to a chip test instruction input by a user, so that the device end can parse the serial port data, run a test program, and send feedback information; The serial port data includes a plurality of sub-data, and the step of parsing the serial port data by the device end specifically includes: For any serial data, when it is determined that the first data received from the serial port data is '#' and the second data is 'M', and when it is determined that the data received between the start character and the end character of the first sub-data is 1, it is determined that the program running on the device side is the test program corresponding to the chip test instruction input by the user; Determine that the first received data between the start character and the end character of the second sub-data is the first preset character, and then determine the test capacity of the chip; Determine that the character before the end character between the start character and the end character of the second sub-data is the second preset character, and then determine the target test times of the chip; The display module is used to display the chip test status according to the feedback information.

8. A dynamic random access memory test device, characterized in that include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements a dynamic random access memory testing method as described in any one of claims 1 to 6.

9. A storage medium storing instructions executable by a processor, characterized in that: The processor-executable instructions are used to execute a dynamic random access memory testing method as described in any one of claims 1-6 when executed by the processor.

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