Semiconductor device and method of manufacturing the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-12
- Publication Date
- 2026-07-07
AI Technical Summary
In the existing process flow of high dielectric constant metal gate semiconductor devices, the barrier layer in the film stack structure affects the formation of the high dielectric constant metal gate, resulting in a higher threshold voltage and affecting the performance of the semiconductor device.
By adjusting the ratio of metal and non-metal elements in different barrier layers, the semiconductor processing can be optimized, atomic diffusion in the work function layer can be controlled, the voltage threshold of the transistor can be stabilized, and different process effects can be achieved by using different barrier layer ratios.
The semiconductor device fabrication process was optimized, and the device performance was improved. By adjusting the ratio of metal and non-metal elements in the barrier layer, the interfacial interaction between the dielectric layers was controlled, and the voltage threshold of the transistor was stabilized.
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Figure CN116487331B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] High k metal gate (HKMG) stacking technology has been introduced at the 45nm process node to address the technical obstacles faced by traditional gates.
[0003] In the existing process flow of high dielectric constant metal gate semiconductor devices, after each layer is stacked, the stacked structure is subjected to high-temperature annealing to reduce defects in the metal gate. However, in the metal gate process, the barrier layer in the stacked structure can affect the formation of the high dielectric constant metal gate, resulting in a higher threshold voltage and thus affecting the performance of the semiconductor device.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a semiconductor device and a method for manufacturing the same. This semiconductor manufacturing method can change the ratio of metal elements and non-metal elements in different barrier film layers, thereby optimizing the semiconductor processing.
[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of this disclosure.
[0007] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising:
[0008] A substrate is provided, the substrate including an array region and a peripheral region, the peripheral region including a first region and a second region;
[0009] A first dielectric layer, a second dielectric layer, a first barrier layer, a first work function layer, and a second barrier layer are sequentially formed on the substrate.
[0010] After removing the second barrier layer and the first work function layer of the first region, a second work function layer, a third barrier layer and a first conductive layer are sequentially formed on the substrate.
[0011] The substrate is heat-treated to allow atoms in the second work function layer in the first region to diffuse into the second dielectric layer, and atoms in the first work function layer in the second region to diffuse into the second dielectric layer, and interfacial interactions occur between the second dielectric layer and the first dielectric layer.
[0012] Remove the first conductive layer, the third blocking layer, the second work function layer, and the first blocking layer in the first region, and remove the first conductive layer, the third blocking layer, the second work function layer, the second blocking layer, the first work function layer, and the first blocking layer in the array region and the second region;
[0013] A fourth barrier layer and a second conductive layer are formed on the first region and the second region;
[0014] The ratio of metal element content to non-metal element content in the first barrier layer is less than the ratio of metal element content to non-metal element content in the second barrier layer and the third barrier layer.
[0015] In some embodiments of this disclosure, based on the aforementioned scheme, the ratio of metal element content to non-metal element content in the first barrier layer is less than 1, and the ratio of metal element content to non-metal element content in the second barrier layer and the third barrier layer is greater than 1.
[0016] In some embodiments of this disclosure, based on the foregoing scheme, the ratio of metal element content to non-metal element content in the first barrier layer ranges from 0.5 to 0.95, and the ratio of metal element content to non-metal element content in the second barrier layer and the third barrier layer ranges from 1.05 to 1.5.
[0017] In some embodiments of this disclosure, based on the foregoing scheme, the ratio of metal element content to non-metal element content in the fourth barrier layer is greater than 1.
[0018] In some embodiments of this disclosure, based on the foregoing scheme, the ratio of metal element content to non-metal element content in the fourth barrier layer is the same as the ratio of metal element content to non-metal element content in the second barrier layer.
[0019] In some embodiments of this disclosure, based on the foregoing scheme, in the first region, atomic diffusion in the work function layer occurs between the second work function layer and the second dielectric layer, and in the second region, atomic diffusion in the work function layer occurs between the first work function layer and the second dielectric layer.
[0020] In some embodiments of this disclosure, based on the foregoing scheme, the first region includes an N region for forming an N-type device, the N region including a first N region and a second N region; the second region includes a P region for forming a P-type device, the P region including a first P region and a second P region.
[0021] In some embodiments of this disclosure, based on the foregoing scheme, the thickness of the first dielectric layer in the second N region is greater than the thickness of the first dielectric layer in the first N region, and the thickness of the first dielectric layer in the second P region is greater than the thickness of the first dielectric layer in the first P region.
[0022] In some embodiments of this disclosure, based on the foregoing scheme, before the first dielectric layer, second dielectric layer, first barrier layer, first work function layer, and second barrier layer are sequentially formed on the substrate, the following steps are included:
[0023] A strain layer is formed on the substrate in the first P region.
[0024] In some embodiments of this disclosure, based on the foregoing scheme, the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.
[0025] In some embodiments of this disclosure, based on the foregoing scheme, the step of sequentially forming a second work function layer, a third barrier layer, and a first conductive layer on the substrate further includes:
[0026] The second work function layer and the third barrier layer in the second region are removed, and a first conductive layer is formed on the substrate.
[0027] In some embodiments of this disclosure, based on the foregoing scheme, before the first dielectric layer, second dielectric layer, first barrier layer, first work function layer, and second barrier layer are sequentially formed on the substrate, the method further includes:
[0028] A barrier material layer and an isolation layer are sequentially formed on the substrate of the array region.
[0029] In some embodiments of this disclosure, based on the foregoing scheme, the step of sequentially forming a first dielectric layer, a second dielectric layer, a first barrier layer, a first work function layer, and a second barrier layer on the substrate further includes:
[0030] Remove the first dielectric layer of the array region.
[0031] In some embodiments of this disclosure, based on the foregoing scheme, the heat treatment of the substrate includes:
[0032] A first gas is introduced and maintained at a first temperature for a first preset time;
[0033] A second gas is introduced, and the first temperature is raised to a second temperature within a second preset time.
[0034] Annealing process, maintaining the third preset time.
[0035] In some embodiments of this disclosure, based on the foregoing scheme, the first preset time is greater than the second preset time and the third preset time, and the second preset time is less than the third preset time.
[0036] In some embodiments of this disclosure, based on the foregoing scheme, the first gas includes an inert gas, the second gas includes an oxidizing gas, and the flow rate of the first gas is greater than the flow rate of the second gas.
[0037] In some embodiments of this disclosure, based on the foregoing scheme, removing the second blocking layer and the first work function layer of the first region includes:
[0038] Form a photoresist covering the substrate and pattern the photoresist;
[0039] The second blocking layer and the first work function layer in the first region are removed by etching with patterned photoresist.
[0040] According to another aspect of this disclosure, a semiconductor device is provided, comprising:
[0041] A substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a first region and a second region;
[0042] A first dielectric layer is located on the peripheral region;
[0043] A second dielectric layer is located on the first dielectric layer and the array region, and interfacial interactions occur at the interface between the first dielectric layer and the second dielectric layer.
[0044] A barrier layer is located on the second dielectric layer;
[0045] A conductive layer is located on the barrier layer;
[0046] The ratio of metal element content to non-metal element content in the barrier layer is greater than 1.
[0047] In some embodiments of this disclosure, based on the foregoing scheme, the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.
[0048] The semiconductor device manufacturing method disclosed herein plays a different role in the semiconductor device fabrication process because different barrier layers have different positions in the stacked layer structure. By changing the ratio of metal elements to non-metal elements in different barrier layers, different process effects can be achieved. When the ratio of metal elements to non-metal elements in the barrier layer is large, the resistance of the barrier layer decreases, making it easier to capture oxygen atoms, while increasing the difficulty of metal diffusion in the work function layer. When the ratio of metal elements to non-metal elements in the barrier layer is small, the resistance of the barrier layer increases, and the metal in the work function layer diffuses more easily. By utilizing the above characteristics, different barrier layers can have different ratios of metal elements to non-metal elements, thereby optimizing the semiconductor processing technology during semiconductor manufacturing.
[0049] On the other hand, the semiconductor device manufacturing method provided in this disclosure can control the diffusion of atoms in the work function layer into the dielectric layer by changing the ratio of metal elements and non-metal elements in the barrier layer, thereby controlling the interfacial interactions between different dielectric film layers in the dielectric layer, so as to stabilize the voltage threshold of the transistor in the semiconductor device and thus improve the performance of the semiconductor device.
[0050] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0051] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0052] Figure 1 This is a schematic diagram of the manufacturing process of a semiconductor device manufacturing method according to an exemplary embodiment of the present disclosure.
[0053] Figures 2 to 10 This is a schematic diagram of the film stacking of a semiconductor structure in an exemplary embodiment of the present disclosure.
[0054] Figure 11 This is a schematic diagram of a first film removal method in a first region of a semiconductor device manufacturing method according to an exemplary embodiment of the present disclosure.
[0055] Figure 12 This is a schematic diagram of a heat treatment method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.
[0056] The reference numerals in the attached figures are explained as follows:
[0057] 10: Array area; 20: Peripheral area;
[0058] 100: Substrate; 101: Trench; 1011: Barrier material layer;
[0059] 102: Storage structure; 1021: Gate isolation layer;
[0060] 1022: Gate conductive layer; 201: First dielectric layer;
[0061] 202: Second dielectric layer; 203: Strain layer;
[0062] 301: First barrier layer; 302: Second barrier layer;
[0063] 303: Third barrier layer; 304: Fourth barrier layer;
[0064] 401: First work function layer; 402: Second work function layer;
[0065] 501: First conductive layer; 502: Second conductive layer; 600: Isolation layer;
[0066] A: First area; B: Second area;
[0067] N1: First N-zone; N2: Second N-zone;
[0068] P1: First P region; P2: Second P region;
[0069] PR: Photoresist. Detailed Implementation
[0070] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0071] In the following description of various exemplary embodiments of this disclosure, reference is made to the accompanying drawings, which form part of this disclosure, and which illustrate by way of example different exemplary structures, systems, and steps that can implement various aspects of this disclosure. It should be understood that other specific embodiments of the components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of this disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of this disclosure, these terms are used herein only for convenience, such as the orientation according to the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of this disclosure.
[0072] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.
[0073] In DRAM (Dynamic Random Access Memory), the existing process flow for high-dielectric-constant metal-gate semiconductor devices, taking CMOS (Complementary Metal Oxide Semiconductor) devices as an example, includes NMOS (Negative Channel Metal Oxide Semiconductor) and PMOS (Positive Channel Metal Oxide Semiconductor) regions. A shallow trench isolation (STI) structure is formed between the NMOS and PMOS regions. With the miniaturization of semiconductor devices and the increasing demands on gate performance, a metal gate is formed. To further improve the performance of semiconductor devices, existing technologies perform high-temperature annealing after forming the metal gate structure, such as 1000°C spike annealing, which can reduce metal gate defects.
[0074] However, in the aforementioned fabrication process of high dielectric constant metal gate semiconductor devices, since the barrier layer, as a different layer in the stacked film structure, has different functions, the barrier layer will affect the performance of the high dielectric constant metal gate semiconductor device. Therefore, this disclosure proposes a semiconductor device and its fabrication method based on the influence of different metal and non-metal element ratios in the barrier layer on the fabrication process of high dielectric constant semiconductor devices, in order to optimize the fabrication process of high dielectric constant semiconductor devices and improve the performance of semiconductor devices.
[0075] The semiconductor device manufacturing method provided in this disclosure is illustrated using an application to dynamic random access memory as an example. It is readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below in order to apply the relevant designs of this disclosure to other types of semiconductor structures. These changes are still within the scope of the principles of the semiconductor structure manufacturing method proposed in this disclosure.
[0076] This disclosure provides a method for manufacturing a semiconductor device, such as... Figure 1 As shown, the method includes:
[0077] Step S10: Provide a substrate 100, which includes an array region 10 and a peripheral region 20. The peripheral region 20 includes a first region A and a second region B.
[0078] Step S20: A first dielectric layer 201, a second dielectric layer 202, a first barrier layer 301, a first work function layer 401 and a second barrier layer 302 are sequentially formed on the substrate 100;
[0079] Step S30: After removing the second barrier layer 302 and the first work function layer 401 of the first region A, the second work function layer 402, the third barrier layer 303 and the first conductive layer 501 are sequentially formed on the substrate 100.
[0080] Step S40: Heat treatment is performed on the substrate 100 to allow atoms in the second work function layer 402 in the first region A to diffuse into the second dielectric layer 202, and atoms in the first work function layer 401 in the second region B to diffuse into the second dielectric layer 202, and interfacial interaction occurs between the second dielectric layer 202 and the first dielectric layer 201.
[0081] Step S50: Remove the first conductive layer 501, the third blocking layer 303, the second work function layer 402 and the first blocking layer 301 in the first region A, and remove the first conductive layer 501, the third blocking layer 303, the second work function layer 402, the second blocking layer 302, the first work function layer 401 and the first blocking layer 301 in the array region 10 and the second region B.
[0082] Step S60: A fourth barrier layer 304 and a second conductive layer 502 are formed on the first region A and the second region B; wherein, the ratio of metal element content to non-metal element content in the first barrier layer 301 is less than the ratio of metal element content to non-metal element content in the second barrier layer 302 and the third barrier layer 303.
[0083] Unlike existing technologies that use a constant ratio of metal to non-metal elements in different barrier layers, this disclosure employs different ratios of metal to non-metal elements in different barrier layers. By utilizing these varying element ratios, different process effects can be achieved. For example, with a titanium nitride barrier layer, a higher titanium-nitrogen ratio results in reduced resistance and higher oxygen trapping capacity, making it difficult for atoms in the work function layer above or below the titanium nitride layer to diffuse. Conversely, a lower titanium-nitrogen ratio increases resistance, facilitating the diffusion of atoms in the work function layer above or below the titanium nitride layer. Based on these barrier layer characteristics, different ratios of metal to non-metal elements are used in different barrier layers during semiconductor fabrication to control the diffusion of atoms from the work function layer into the dielectric layer. This, in turn, controls the interfacial interactions between different dielectric layers, thereby stabilizing the voltage threshold of transistors in semiconductor devices, optimizing semiconductor device fabrication processes, and improving semiconductor device performance.
[0084] Combination Figures 2 to 10 , Figures 2 to 10 The accompanying drawings illustrate several steps of an exemplary embodiment of a semiconductor structure fabrication method, including a schematic diagram of the film layer stacking structure of the semiconductor structure. The process steps of the semiconductor device fabrication method proposed in this disclosure will be described in detail below with reference to the above drawings.
[0085] In step S10, a substrate 100 is provided, which includes an array region 10 and a peripheral region 20. The peripheral region 20 includes a first region A and a second region B.
[0086] like Figure 2As shown, the semiconductor device manufacturing method provided in this disclosure, taking a CMOS device as an example, includes an array region 10 and a peripheral region 20 on a substrate 100. The peripheral region 20 includes a first region A and a second region B. Multiple shallow trench isolation structures are formed inside the substrate 100. These shallow trench isolation structures are formed by filling the trenches 101 with an isolation material after trenches 101 are formed in the substrate 100. The isolation material can include at least one of silicon nitride, silicon oxide, or silicon carbonitride, without special limitation. A memory structure 102 is embedded in the array region 10. The memory structure 102 includes at least a gate isolation layer 1021 and a gate conductive layer 1022. The material of the gate isolation layer 1021 can include at least one of silicon nitride, silicon oxide, or silicon carbonitride, and the material of the gate conductive layer 1022 can include at least one of tungsten, titanium nitride, or polysilicon. However, the specific layers of the memory structure 102 are determined according to the actual structure. The memory structure 102 is used for writing, erasing, or storing data.
[0087] The peripheral region 20 includes a first region A and a second region B. The first region A includes an N region forming an N-type device, which includes a first N region N1 and a second N region N2. The second region B includes a P region forming a P-type device, which includes a first P region P1 and a second P region P2.
[0088] The substrate 100 may be silicon or other semiconductor materials, and this disclosure does not impose any special restrictions on the material of the substrate 100.
[0089] In step S20, a first dielectric layer 201, a second dielectric layer 202, a first barrier layer 301, a first work function layer 401, and a second barrier layer 302 are sequentially formed on the substrate 100.
[0090] like Figure 2 , Figure 3 and Figure 4 As shown, a first dielectric layer 201 and a second dielectric layer 202, a first barrier layer 301, a first work function layer 401 and a second barrier layer 302 are deposited on a substrate 100. The thickness of the first dielectric layer 201 in the second N region N2 is greater than the thickness of the first dielectric layer 201 in the first N region N1, and the thickness of the first dielectric layer 201 in the second P region P2 is greater than the thickness of the first dielectric layer 201 in the first P region P1.
[0091] Before forming the first dielectric layer 201 and the second dielectric layer 202, the first barrier layer 301, the first work function layer 401, and the second barrier layer 302 on the substrate 100, a strain layer 203 needs to be formed on the substrate 100 of the first P region P1. Before forming the first dielectric layer 201 and the second dielectric layer 202, the first barrier layer 301, the first work function layer 401, and the second barrier layer 302 on the substrate 100, a barrier material layer 1011 and an isolation layer 600 are sequentially formed on the substrate 100 of the array region 10. After forming the first dielectric layer 201 and the second dielectric layer 202, the first barrier layer 301, the first work function layer 401, and the second barrier layer 302 on the substrate 100, the first dielectric layer 201 in the array region 10 is removed. The removal of the first dielectric layer 201 in the array region 10 can be done by etching, which can include dry etching or wet etching. The specific etching method can be selected according to the actual processing technology.
[0092] The material of the first dielectric layer 201 can be silicon oxide, silicon oxynitride, etc., and the material of the second dielectric layer 202 (HK layer) can be hafnium oxynitride, barium strontium titanate, barium strontium titanate, barium strontium tantalate, etc., and the dielectric constant of the second dielectric layer 202 is greater than the dielectric constant of the first dielectric layer 201. The material of the strain layer 203 can be a germanium silicon compound, i.e., SiGe. The material of the isolation layer 600 can be silicon nitride, silicon oxide, etc. The materials of the above-mentioned film layers disclosed herein are not limited to these, and this disclosure does not make specific limitations.
[0093] In the first region A (N1 and N2 regions), the work function layer is mainly composed of lanthanum oxide (LaO), and in the second region B (P1 and P2 regions), the work function layer is mainly composed of aluminum oxide (AlO). The first work function layer 401 is an aluminum oxide layer. After the second dielectric layer 202 is formed on the first region A and the second region B, the first work function layer 401 is deposited on the first region A and the second region B. The first work function layer 401 can be an aluminum oxide layer. A first barrier layer 301 and a second barrier layer 302 are deposited below and above the first work function layer 401, respectively. The materials of the first barrier layer 301 and the second barrier layer 302 can be titanium nitride (TiN), thallium nitride, etc., but are not limited to the above materials.
[0094] Since the first work function layer 401 contains metal oxides, the diffusion capacity of oxygen and metal elements in the work function layer needs to be considered in subsequent processing. To block the first work function layer 401 from the second dielectric layer 202, a first barrier layer 301 is deposited between the first work function layer 401 and the second dielectric layer 202. Since the first barrier layer 301 needs to have a diffusion effect on the atoms in the work function layer, in order to increase the diffusion capacity of the first barrier layer 301 on the atoms in the work function layer, this disclosure sets the ratio of metal elements and non-metal elements in the first barrier layer 301 to be less than 1, and the ratio range can include 0.5-0.95, so as to improve the diffusion capacity of atoms in the work function layer. Taking the first barrier layer 301 as a titanium nitride layer as an example, the ratio of titanium to nitrogen in the first barrier layer 301 can be set to 0.8, that is, the first barrier layer 301 is a nitrogen-rich layer. In subsequent processing, the atoms in the first work function layer 401 can more easily diffuse through the titanium nitride layer with a titanium-nitrogen ratio of 0.8.
[0095] In this disclosure, the ratio of metallic elements to non-metallic elements in the first barrier layer 301 is less than 1, and its range can be 0.5-0.95. However, this disclosure does not specifically limit the above ratio range, and it can be selected according to actual usage requirements.
[0096] In step S30, after removing the second barrier layer 302 and the first work function layer 401 of the first region A, the second work function layer 402, the third barrier layer 303 and the first conductive layer 501 are sequentially formed on the substrate 100.
[0097] Since the work function layer of the first region A (N1 and N2 regions) is mainly composed of lanthanum oxide (LaO), it is necessary to remove the first work function layer 401 and the second barrier layer 302 for the first region A. Figure 11 As shown, the specific removal method is as follows:
[0098] Step S301: Form a photoresist PR covering the first region A, and pattern the first photoresist PR;
[0099] Step S302: Use patterned photoresist PR to etch and remove the second blocking layer 302 and the first work function layer 401 of the first region A.
[0100] like Figure 5 As shown and Figure 6 As shown, photoresist PR is used to etch the first region A to remove the second barrier layer 302 and the first work function layer 401. The etching method can be dry etching, wet etching, or a combination of dry etching and wet etching. The specific etching method can be selected according to actual needs, and this disclosure does not make specific limitations.
[0101] like Figure 7 As shown, after etching away the second barrier layer 302 and the first work function layer 401 in the first region A, the second work function layer 402, the third barrier layer 303, and the first conductive layer 501 are sequentially formed on the substrate 100. The material of the second work function layer 402 can be a lanthanum oxide layer. After the above steps, in the first region A, the second work function layer 402 is located between the first barrier layer 301 and the third barrier layer 303. In the second region B, the second work function layer 402 is located between the second barrier layer 302 and the third barrier layer 303. The first conductive layer 501 is deposited on the third barrier layer 303. The material of the first conductive layer 501 can be undoped polysilicon.
[0102] In this disclosure, taking a titanium nitride layer as the barrier layer as an example, a first barrier layer 301 is disposed below the second work function layer 402 (LaO layer) in the first region A (N1 region and N2 region). In order to facilitate the diffusion of atoms in the work function layer, the titanium-nitrogen ratio in the first barrier layer 301 is selected to be 0.8. A third barrier layer 303 is disposed between the second work function layer 402 (LaO layer) and the first conductive layer 501. In order to prevent the second work function layer 402 (LaO layer) from diffusing upward into the first conductive layer 501, the titanium-nitrogen ratio in the third barrier layer 303 is set to 1.2, which is a titanium-rich layer. Since the metal element content in the third barrier layer 303 is higher than the non-metal element content, the energy for capturing oxygen elements is higher, the resistance value is reduced, and the atoms in the work function layer are not easy to diffuse. In subsequent processing, it is difficult for the atoms in the first work function layer 401 and the second work function layer 402 located on both sides of the third barrier layer 303 to diffuse, thus playing a barrier role.
[0103] Within the second region B (regions P1 and P2), from top to bottom, are the first conductive layer 501, the third barrier layer 303, the second work function layer 402, the second barrier layer 302, the first work function layer 401, and the first barrier layer 301. Similar to the processing principle of the first region A, the titanium-nitrogen ratio in the first barrier layer 301 is set to 0.8, and the titanium-nitrogen ratio in the second barrier layer 302 and the third barrier layer 303 is set to 1.2. When the ratio of metal elements to non-metal elements in the second barrier layer 302 and the third barrier layer 303 is greater than 1, the barrier layer's ability to capture oxygen elements increases, the resistance decreases, and metal diffusion in the work function layer becomes more difficult. When the ratio of metal elements to non-metal elements in the first barrier layer 301 is less than 1, the resistance in the barrier layer increases, and metal diffusion in the work function layer becomes easier. The functions of each film layer in the second region B are as described above and will not be repeated here.
[0104] In this disclosure, the ratio of metal element content to non-metal element content in the first barrier layer 301 is less than the ratio of metal element content to non-metal element content in the second barrier layer 302 and the third barrier layer 303. Furthermore, the ratio of metal element content to non-metal element content in the first barrier layer 301 is less than 1, while the ratio of metal element content to non-metal element content in the second barrier layer 302 and the third barrier layer 303 is greater than 1. Further, the ratio of metal element content to non-metal element content in the first barrier layer 301 ranges from 0.5 to 0.95, and the ratio of metal element content to non-metal element content in the second barrier layer 302 and the third barrier layer 303 ranges from 1.05 to 1.5. This disclosure includes, but is not limited to, the above-mentioned range values, and the ratio of metal element content to non-metal element content in the barrier layer can be determined according to actual usage needs.
[0105] In step S40, the substrate 100 is heat-treated to allow atoms in the second work function layer 402 in the first region A to diffuse into the second dielectric layer 202, and atoms in the first work function layer 401 in the second region B to diffuse into the second dielectric layer 202, and interfacial interaction occurs between the second dielectric layer 202 and the first dielectric layer 201.
[0106] like Figure 8 As shown, after the above-mentioned film layer is formed on the substrate 100, the substrate 100 is heat-treated to cause interfacial interaction between the interface between the first dielectric layer 201 and the second dielectric layer 202. For example, the interface between the first dielectric layer 201 and the second dielectric layer 202 is subjected to dipole interaction. Dipole interaction is an interaction between polar molecules, that is, the attraction between the end of a polar molecule with a partial positive charge and the end of another molecule with a partial negative charge. Polar molecules generate dipole moments due to uneven charge distribution. When polar molecules approach each other, they will cause electrostatic attraction.
[0107] In the semiconductor manufacturing method provided in this disclosure, the preferred heat treatment process employs RTA (Rapid Thermal Annealing) to heat treat the substrate 100, such as... Figure 12 As shown, the heat treatment method includes:
[0108] Step S401: Introduce the first gas and maintain it at the first temperature for a first preset time;
[0109] Step S402: Introduce the second gas, and simultaneously raise the first temperature to the second temperature within a second preset time.
[0110] Step S403: Annealing process, hold for the third preset time.
[0111] In steps S401 to S403, the first preset time is greater than the second preset time and the third preset time, and the second preset time is less than the third preset time. That is, the three preset times are arranged from smallest to largest as follows: second preset time, third preset time, and first preset time. The first gas includes an inert gas, the second gas includes an oxidizing gas, and the flow rate of the first gas is greater than the flow rate of the second gas.
[0112] In the above heat treatment process, the first gas can be an inert gas such as nitrogen or helium, and the flow rate of the first gas ranges from 10,000 to 3,000 sccm (standard milliliters / minute). The second gas can be an oxidizing gas such as oxygen, and the flow rate of the second gas ranges from 300 to 1,000 sccm. The flow rate of the first gas is greater than that of the second gas. The first temperature ranges from 300℃ to 800℃, and the second temperature ranges from 400℃ to 1,500℃. The heating rate can be 50℃ / s to 150℃ / s, and the second temperature is greater than the first temperature. The first preset time can be 10s to 30s (seconds), the second preset time can be 3.3s to 7.3s, and the third preset time can be 5s to 15s. The preset times, from smallest to largest, are the second preset time, the third preset time, and the first preset time.
[0113] Specifically, in the heat treatment process, a first gas, nitrogen, is introduced at a flow rate of 20,000 sccm and maintained at a first temperature (550°C) for a first preset time (20 seconds). Then, a second gas, oxygen, is introduced at a flow rate of 650 sccm, while the first gas (nitrogen) is maintained at 20,000 sccm, raising the temperature from the first temperature (550°C) to a second temperature (950°C). The heating rate is 75°C / second, and the heating time is the second preset time, approximately 5.3 seconds. The substrate 100 undergoes a peak annealing treatment, maintaining the second temperature at a third preset time (950°C) for 10 seconds, while simultaneously introducing the first gas (nitrogen) at 20,000 sccm and the second gas (oxygen) at 650 sccm.
[0114] It should be noted that the parameter values in the above heat treatment process steps are merely illustrative. The selection of parameter values in specific processing steps can be determined according to actual process requirements, and this disclosure does not impose any specific limitations.
[0115] In step S50, the first conductive layer 501, the third blocking layer 303, the second work function layer 402, and the first blocking layer 301 in the first region A are removed, and the first conductive layer 501, the third blocking layer 303, the second work function layer 402, the second blocking layer 302, the first work function layer 401, and the first blocking layer 301 in the array region 10 and the second region B are also removed.
[0116] like Figure 9 As shown, the substrate 100 is subjected to a high-temperature rapid heat treatment process. After the rapid heat treatment, the first conductive layer 501, the third barrier layer 303, the second work function layer 402, and the first barrier layer 301 in the first region A are removed. At the same time, the first conductive layer 501, the third barrier layer 303, the second work function layer 402, the second barrier layer 302, the first work function layer 401, and the first barrier layer 301 in the array region 10 and the second region B are also removed.
[0117] In step S60, a fourth barrier layer 304 and a second conductive layer 502 are formed on the first region A and the second region B. The ratio of metal element content to non-metal element content in the fourth barrier layer 304 is the same as the ratio of metal element content to non-metal element content in the second barrier layer 302 and the third barrier layer 303.
[0118] After steps S10-S50 are completed, as follows Figure 10 As shown, a fourth barrier layer 304 is deposited on the first region A and the second region B, and a second conductive layer 502 is deposited on the fourth barrier layer 304. The ratio of metal elements to non-metal elements in the fourth barrier layer 304 needs to be greater than 1. Since the function of the fourth barrier layer 304 is to capture more oxygen elements and at the same time ensure that metals are difficult to diffuse, for example, the fourth barrier layer 304 is a titanium nitride layer, and the titanium-nitrogen ratio can be 1.2. This ensures that after the metal gate of the semiconductor device is formed, the fourth barrier layer 304 can prevent the diffusion of metal elements in other film layers.
[0119] The ratio of metal element content to non-metal element content in the fourth barrier layer 304 can be the same as that in the second barrier layer 302. This simplifies the semiconductor device manufacturing process, saves processing time, and improves processing efficiency.
[0120] In addition, the ratio of metallic elements to non-metallic elements in the fourth barrier layer 304 is greater than 1. The ratio of metallic elements to non-metallic elements can be in the range of 1.05-1.5, but this disclosure does not specifically limit the range of the above ratio.
[0121] The second conductive layer 502 can be a doped polycrystalline silicon layer or other materials suitable for semiconductor films; this disclosure does not impose any specific limitations.
[0122] The first barrier layer 301, the second barrier layer 302, the third barrier layer 303, and the fourth barrier layer 304 mentioned above can all be deposited using PVD (Physical Vapor Deposition). Among them, physical vapor deposition methods include vacuum evaporation, sputtering deposition, arc plasma deposition, ion deposition, and molecular beam epitaxy. The preferred method of this disclosure is RFPVD (Radio Frequency Physical Vapor Deposition) to adjust the ratio of metal elements to non-metal elements in each barrier film layer, but it is not limited to this method.
[0123] The semiconductor device manufacturing method disclosed herein enhances the functionality of different barrier layers by adjusting the ratio of metal to non-metal elements in the semiconductor processing. For example, when the diffusion capability needs to be increased in the work function layer near the barrier layer, the ratio of metal to non-metal elements can be adjusted to less than 1, making it easier for metal elements to diffuse. When the barrier effect needs to be increased, the ratio of metal to non-metal elements in the barrier layer can be adjusted to greater than 1, making the barrier layer more capable of capturing oxygen and making it less likely for atoms in the work function layer to diffuse. By selecting different ratios according to the different functions of the barrier layers during semiconductor processing, the semiconductor processing technology can be optimized, and device performance can be improved.
[0124] It should be noted that although the steps of the semiconductor device manufacturing method of this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0125] This disclosure also provides a semiconductor device manufactured using the above-described semiconductor device manufacturing method, such as... Figure 9 As shown, the semiconductor device includes a substrate 100, a first dielectric layer 201, a second dielectric layer 202, a barrier layer 304, and a conductive layer 502.
[0126] The substrate 100 includes an array region 10 and a peripheral region 20, the peripheral region 20 including a first region A and a second region B; a first dielectric layer 201 is located on the peripheral region 20; a second dielectric layer 202 is located on the first dielectric layer 201 and the array region 10, and interfacial interaction occurs at the interface between the first dielectric layer 201 and the second dielectric layer 202; a barrier layer 304 is located on the second dielectric layer 202; a conductive layer 502 is located on the barrier layer 304; wherein the ratio of metal element content to non-metal element content in the barrier layer 304 is greater than 1.
[0127] The first dielectric layer 201 can be a silicon oxide layer, the second dielectric layer 202 can be a hafnium oxysilicon layer (HK layer), the dielectric constant of the second dielectric layer 202 is greater than the dielectric constant of the first dielectric layer 201, the barrier layer 304 can be a silicon nitride layer, and the conductive layer 502 can be a doped polysilicon layer. However, the materials of the films disclosed herein include, but are not limited to, the above-mentioned materials. Appropriate materials can be selected according to the structure and processing engineering of the actual semiconductor device. This disclosure does not impose specific limitations.
[0128] The semiconductor device disclosed herein is manufactured using the aforementioned semiconductor fabrication method. During the processing, a barrier layer with different proportions of metal and non-metal elements is used, which further optimizes the function of the barrier layer, optimizes the processing technology of the high dielectric constant metal gate, and further improves the performance of the semiconductor device.
[0129] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate including an array region and a peripheral region, the peripheral region including a first region and a second region; A first dielectric layer, a second dielectric layer, a first barrier layer, a first work function layer, and a second barrier layer are sequentially formed on the substrate. After removing the second barrier layer and the first work function layer of the first region, a second work function layer, a third barrier layer and a first conductive layer are sequentially formed on the substrate. The substrate is heat-treated to allow atoms in the second work function layer in the first region to diffuse into the second dielectric layer, and atoms in the first work function layer in the second region to diffuse into the second dielectric layer, and interfacial interactions occur between the second dielectric layer and the first dielectric layer. Remove the first conductive layer, the third blocking layer, the second work function layer, and the first blocking layer in the first region, and remove the first conductive layer, the third blocking layer, the second work function layer, the second blocking layer, the first work function layer, and the first blocking layer in the array region and the second region; A fourth barrier layer and a second conductive layer are formed on the first region and the second region; The ratio of metal element content to non-metal element content in the first barrier layer is less than the ratio of metal element content to non-metal element content in the second barrier layer and the third barrier layer.
2. The semiconductor device manufacturing method according to claim 1, characterized in that, The ratio of metal element content to non-metal element content in the first barrier layer is less than 1, while the ratio of metal element content to non-metal element content in the second barrier layer and the third barrier layer is greater than 1.
3. The semiconductor device manufacturing method according to claim 2, characterized in that, The ratio of metal element content to non-metal element content in the first barrier layer ranges from 0.5 to 0.95, and the ratio of metal element content to non-metal element content in the second and third barrier layers ranges from 1.05 to 1.
5.
4. The semiconductor device manufacturing method according to claim 1, characterized in that, The ratio of metallic element content to non-metallic element content in the fourth barrier layer is greater than 1.
5. The semiconductor device manufacturing method according to claim 1, characterized in that, The ratio of metal element content to non-metal element content in the fourth barrier layer is the same as that in the second barrier layer.
6. The semiconductor device manufacturing method according to claim 1, characterized in that, In the first region, atomic diffusion in the work function layer occurs between the second work function layer and the second dielectric layer; in the second region, atomic diffusion in the work function layer occurs between the first work function layer and the second dielectric layer.
7. The semiconductor device manufacturing method according to claim 1, characterized in that, The first region includes an N region for forming an N-type device, the N region including a first N region and a second N region; the second region includes a P region for forming a P-type device, the P region including a first P region and a second P region.
8. The semiconductor device manufacturing method according to claim 7, characterized in that, The thickness of the first dielectric layer in the second N region is greater than the thickness of the first dielectric layer in the first N region, and the thickness of the first dielectric layer in the second P region is greater than the thickness of the first dielectric layer in the first P region.
9. The semiconductor device manufacturing method according to claim 8, characterized in that, Before the first dielectric layer, the second dielectric layer, the first barrier layer, the first work function layer, and the second barrier layer are sequentially formed on the substrate, the process includes: A strain layer is formed on the substrate in the first P region.
10. The semiconductor device manufacturing method according to claim 1, characterized in that, The dielectric constant of the second dielectric layer is greater than that of the first dielectric layer.
11. The semiconductor device manufacturing method according to claim 1, characterized in that, The method of sequentially forming a second work function layer, a third barrier layer, and a first conductive layer on the substrate further includes: The second work function layer and the third barrier layer in the second region are removed, and a first conductive layer is formed on the substrate.
12. The semiconductor device manufacturing method according to claim 1, characterized in that, Before the first dielectric layer, the second dielectric layer, the first barrier layer, the first work function layer, and the second barrier layer are sequentially formed on the substrate, the method further includes: A barrier material layer and an isolation layer are sequentially formed on the substrate of the array region.
13. The semiconductor device manufacturing method according to claim 1, characterized in that, The method of sequentially forming a first dielectric layer, a second dielectric layer, a first barrier layer, a first work function layer, and a second barrier layer on the substrate further includes: Remove the first dielectric layer of the array region.
14. The semiconductor device manufacturing method according to claim 1, characterized in that, The heat treatment of the substrate includes: A first gas is introduced and maintained at a first temperature for a first preset time; A second gas is introduced, and the first temperature is raised to a second temperature within a second preset time. Annealing process, maintaining the third preset time.
15. The semiconductor device manufacturing method according to claim 14, characterized in that, The first preset time is greater than the second preset time and the third preset time, and the second preset time is less than the third preset time.
16. The semiconductor device manufacturing method according to claim 14, characterized in that, The first gas includes an inert gas, the second gas includes an oxidizing gas, and the flow rate of the first gas is greater than the flow rate of the second gas.
17. The semiconductor device manufacturing method according to claim 1, characterized in that, The removal of the second blocking layer and the first work function layer in the first region includes: Form a photoresist covering the substrate and pattern the photoresist; The second blocking layer and the first work function layer in the first region are removed by etching with patterned photoresist.
18. A semiconductor device, formed using the semiconductor device manufacturing method according to any one of claims 1-17, characterized in that, include: A substrate, the substrate comprising an array region and a peripheral region, the peripheral region comprising a first region and a second region; A first dielectric layer is located on the peripheral region; A second dielectric layer is located on the first dielectric layer and the array region, and interfacial interactions occur at the interface between the first dielectric layer and the second dielectric layer. A barrier layer is located on the second dielectric layer; A conductive layer is located on the barrier layer; The ratio of metal element content to non-metal element content in the barrier layer is greater than 1.
19. The semiconductor device according to claim 18, characterized in that, The dielectric constant of the second dielectric layer is greater than that of the first dielectric layer.