Single-supply step-up multi-level inverter

Abstract

This invention discloses a single-supply boost multilevel inverter, including a DC power supply V. D Inductor L1, inductor L2 and module SM i (i = 1…2N); where module SM1 to module SM N Connect sequentially, module SM N+1 ~Module SM 2N Connected sequentially; wherein, modules SM1 to SM N Connect sequentially, adjacent modules SM1 to SM2. N A switching transistor S is connected between them. j (j = 1, 2, ..., N-1); Module SM N+1 ~Module SM 2N Connect sequentially, adjacent modules SM N+1 ~Module SM 2N A switching transistor S is connected between them. j (j = N, N+1, ..., 2N-2); Module SM1 ~ Module SM N‑1 The second end is connected to modules SM2 to SM3 respectively. N The first end connection; the module SM N+1 ~Module SM 2N‑1 The second end is connected to module SM in sequence. N+2 ~Module SM 2N Connection; solves problems such as complex structure, weak boost capability, and poor capacitor voltage self-balancing capability of current multilevel inverters.

Description

Technical Field

[0001] This invention relates to the field of multilevel inverter technology, and in particular to a single-supply boost multilevel inverter. Background Technology

[0002] Wireless power transfer technology offers advantages over traditional contact-based power supply, including higher security and wider application range, making it an important method for power transmission in recent years. Multilevel inverters, compared to traditional inverters, have advantages such as lower output voltage harmonic content, lower device switching frequency, lower switching losses, and lower device stress, and have received widespread attention and application in the field of wireless power transfer in recent years.

[0003] Currently, the main types of multilevel inverters used in wireless power transmission systems include diode-clamped multilevel inverters, flying capacitor multilevel inverters, and cascaded H-bridge multilevel inverters. Diode-clamped and flying capacitor multilevel inverters contain a large number of components, have poor capacitor voltage self-balancing capability, and weak boost capability. Cascaded H-bridge multilevel inverters are composed of multiple cascaded H-bridge units, each with an identical structure, making modular design and packaging easy. However, each unit requires an independent DC power supply, increasing system complexity, and they also lack boost capability. Therefore, designing novel multilevel inverter topologies suitable for wireless power transmission systems is one of the important directions in wireless power transmission technology. Summary of the Invention

[0004] This invention provides a single-supply boost-type multilevel inverter to solve the problems of complex structure, weak boost capability, and poor capacitor voltage self-balancing capability of current multilevel inverters.

[0005] To achieve the above effects, the technical solution of the present invention is as follows:

[0006] A single-supply boost multilevel inverter is used in a wireless power transmission system. The inverter includes a DC power supply V. D Inductor L1, inductor L2 and module SM i (i = 1…2N); where module SM1 to module SM N Connect sequentially, adjacent modules SM1 to SM2. N A switching transistor S is connected between them. j (j = 1, 2, ..., N-1); Module SM N+1 ~Module SM 2N Connect sequentially, adjacent modules SM N+1 ~Module SM 2N A switching transistor S is connected between them. j (j = N, N+1, ..., 2N-2);

[0007] Among them, modules SM1 to SM N-1 The second end is connected to modules SM2 to SM3 respectively. N The first end connection; the module SM N+1 ~Module SM 2N-1 The second end is connected to module SM in sequence. N+2 ~Module SM 2N Connection; the DC power supply V D The positive terminals are connected to the second terminal of inductor L1 and the first terminal of inductor L2, respectively, and the DC power supply V D The negative terminals and module SM are respectively N The second end, module SM 2N The second end is connected; the first end of inductor L1 and the second end of inductor L2 are respectively connected to the first end of module SM1 and module SM N+1 The first end is connected.

[0008] Furthermore, the module SM i (i = 1…2N) is determined by capacitor C i and switching transistor SM i1 SM switching transistor i2 Composition; the switching transistor SM i1 SM switching transistor i2 Series connection, switching transistor SM i1 The second terminal and the switching transistor SM i2 The first terminal is connected; capacitor C i and series-connected switching transistor SM i1 SM switching transistor i2 Parallel connection, capacitor C i One end and the switching transistor SM i1 The first terminal is connected to capacitor C. i The other end and the switching transistor SM i2 The second end connection; module SM i The first, second, and third terminals are respectively the switching transistor SM i1 The second terminal, the switching transistor SM i2 The second terminal, the switching transistor SM i1 The first end.

[0009] Furthermore, the first end of module SM1, module SM N+1 An inductor L is connected in series between the first terminals. P Capacitor C P The first end of module SM1, module SM N+1 The first terminal is connected to the inductor L respectively P The first terminal, capacitor C P The second end is connected to the inductor L. P The second terminal and capacitor C PThe first end is connected;

[0010] Inductor L P Inductor L S These are the transmitting coil and the picking coil of the wireless power transfer system, respectively, with capacitor C. P Capacitor C S These are the series compensation capacitors at the transmitter and receiver ends of the wireless power transmission system, respectively, and M is the inductor L. S Inductor L P The mutual inductance between them, R is the load resistance, and L is the inductance. S Load resistor R, capacitor C S Series connection; the AC power generated by the above multilevel inverter is transmitted through the transmitting coil L P Transmitted to pickup coil L S And it is ultimately consumed by the load resistor R, realizing contactless energy transfer.

[0011] Furthermore, when module SM i When connected to the circuit, capacitor C i Through the switching transistor SM i1 When connected to inductor L1 or inductor L2, the energy released by the inductor is the capacitance C. i Charging; when all modules are not connected to the circuit, inductors L1 and L2 are connected to the DC power supply V. D Parallel connection and energy storage; under steady-state conditions, each module SM i The duty cycle of the access circuit is D, and the SM of each module. i Capacitor C i The voltage at both ends is V D / ND, Module SM1 ~ Module SM N Module SM N+1 ~Module SM 2N After superposition, they form unipolar multilevel voltages, which are combined with the SM modules on both sides. i This enables the inverter to generate multi-level AC output.

[0012] Furthermore, the adjacent module SM i A switching transistor S is connected between them. j The specific connection structure of (j = 1, 2, ..., 2N-2) is as follows: module SM1 ~ module SM N Switch S1 to switch S are connected in sequence. N-1 Module SM N+1 ~Module SM 2N A switching transistor S is connected in sequence between them. N ~Switching transistor S 2N-2 Switch S1 to switch S N-1 The first poles are respectively with modules SM1 to SM N-1 The third terminal is connected to the switching transistor S1 to the switching transistor S2.N-1 The second poles are respectively connected to modules SM2 to SM3. N The third terminal is connected; the switching transistor S N ~Switching transistor S 2N-2 The first pole and module SM N+1 ~Module SM 2N-1 The third terminal is connected to the switching transistor S. N ~Switching transistor S 2N-2 The second pole and module SM respectively N+2 ~Module SM 2N The third terminal is connected; each switch S j The third pole is connected to the control signal.

[0013] Furthermore, during the inverter's duty cycle, all modules SM i The duty cycles of the access circuits are equal, and each module SM i The phase difference between the circuits connected to each other is equal.

[0014] Furthermore, the switching transistor S j It is an NPN transistor, and the switching transistor is S. j The first electrode is the collector, and the switching transistor S j The second electrode is the emitter, and the switch S j The third pole is the base pole.

[0015] Furthermore, the switching transistor S j All are IGBT transistors; switching transistor S j The first electrode is the collector of the IGBT, the second electrode is the emitter of the IGBT, and the switching transistor S is the collector. j The third electrode is the gate electrode.

[0016] Furthermore, the switching transistor S j All are MOSFETs; the switching transistor S j The first electrode is the drain of the MOSFET, the second electrode is the source of the MOSFET, and the switch S is the source of the MOSFET. j The third electrode is the gate electrode.

[0017] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0018] Compared to existing multilevel inverters, which suffer from complex structures, weak boost capabilities, and poor capacitor voltage self-balancing, the multilevel inverter of this invention has a relatively simple topology, good boost capabilities, and can achieve capacitor voltage balancing, making it widely applicable in the field of wireless power transmission. Attached Figure Description

[0019] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the invention. To better illustrate this embodiment, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0020] Figure 1 This is a schematic diagram of a multilevel inverter topology provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the five-level inverter topology provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the main operating waveforms of the five-level inverter provided in this embodiment of the invention;

[0023] Figure 4 The inverter operating mode V provided in the embodiments of the present invention is the first operating mode. pi Schematic diagram when = 0;

[0024] Figure 5 The second operating mode V of the inverter provided in the embodiments of the present invention pi =-V D Schematic diagram in 2D format;

[0025] Figure 6 The third operating mode V of the inverter provided in the embodiments of the present invention pi =-V D Schematic diagram in 2D format;

[0026] Figure 7 The fourth operating mode V of the inverter provided in the embodiments of the present invention pi =-V D Schematic diagram at / D;

[0027] Figure 8 The fifth operating mode V of the inverter provided in the embodiments of the present invention pi =V D Schematic diagram in 2D format;

[0028] Figure 9 The sixth operating mode V of the inverter provided in the embodiments of the present invention pi =V D Schematic diagram in 2D format;

[0029] Figure 10 The seventh operating mode V of the inverter provided in the embodiments of the present invention pi =V D Schematic diagram at / D;

[0030] Figure 11This is a schematic diagram of the simulation waveform of the switching transistor drive signal provided in an embodiment of the present invention;

[0031] Figure 12 This is a schematic diagram of the simulation waveforms of inverter output voltage, current, and system pickup terminal current provided in an embodiment of the present invention;

[0032] Figure 13 This is a schematic diagram of the simulated voltage waveform of the inverter capacitor provided in an embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Example 1

[0035] For easier understanding, please refer to Figure 1 This invention provides a single-supply boost-type multilevel inverter for use in wireless power transmission systems. The inverter includes a DC power supply V. D Inductor L1, inductor L2 and module SM i (i = 1…2N); where module SM1 to module SM N Connect sequentially, adjacent modules SM1 to SM2. N A switching transistor S is connected between them. j (j = 1, 2, ..., N-1); Module SM N+1 ~Module SM 2N Connect sequentially, adjacent modules SM N+1 ~Module SM 2N A switching transistor S is connected between them. j (j = N, N+1, ..., 2N-2);

[0036] Among them, modules SM1 to SM N-1 The second end is connected to modules SM2 to SM3 respectively. N The first end connection; the module SM N+1 ~Module SM 2N-1 The second end is connected to module SM in sequence. N+2 ~Module SM 2N Connection; the DC power supply V D The positive terminals are connected to the second terminal of inductor L1 and the first terminal of inductor L2, respectively, and the DC power supply V D The negative terminals and module SM are respectivelyN The second end, module SM 2N The second end is connected; the first end of inductor L1 and the second end of inductor L2 are respectively connected to the first end of module SM1 and module SM N+1 The first end is connected.

[0037] In the specific implementation process, the module SM i (i = 1…2N) is determined by capacitor C i and switching transistor SM i1 SM switching transistor i2 Composition; the switching transistor SM i1 SM switching transistor i2 Series connection, switching transistor SM i1 The second terminal and the switching transistor SM i2 The first terminal is connected; capacitor C i and series-connected switching transistor SM i1 SM switching transistor i2 Parallel connection, capacitor C i One end and the switching transistor SM i1 The first terminal is connected to capacitor C. i The other end and the switching transistor SM i2 The second end connection; module SM i The first, second, and third terminals are respectively the switching transistor SM i1 The second terminal, the switching transistor SM i2 The second terminal, the switching transistor SM i1 The first terminal. When the switching transistor SM i1 Turn on, switching transistor SM i2 When shut down, module SM i Access circuit; when the switching transistor SM i1 Turn off, switching transistor SM i2 When activated, module SM i The circuit is not connected.

[0038] In the specific implementation process, the first end of module SM1, module SM N+1 An inductor L is connected in series between the first terminals. P Capacitor C P The first end of module SM1, module SM N+1 The first terminal is connected to the inductor L respectively P The first terminal, capacitor C P The second end is connected to the inductor L. P The second terminal and capacitor C P The first end is connected;

[0039] The inductor L P Inductor L SThese are the transmitting coil and the picking coil of the wireless power transfer system, respectively, with capacitor C. P Capacitor C S These are the series compensation capacitors at the transmitter and receiver ends of the wireless power transmission system, respectively, and M is the inductor L. S Inductor L P The mutual inductance between them, R is the load resistance, and L is the inductance. S Load resistor R, capacitor C S Series connection; the AC power generated by the above multilevel inverter is transmitted through the transmitting coil L P Transmitted to pickup coil L S And it is ultimately consumed by the load resistor R, realizing contactless energy transfer.

[0040] In the specific implementation process, when module SM i When connected to the circuit, capacitor C i Through the switching transistor SM i1 When connected to inductor L1 or inductor L2, the energy released by the inductor is the capacitance C. i Charging; when all modules are not connected to the circuit, inductors L1 and L2 are connected to the DC power supply V. D Parallel connection and energy storage; under steady-state conditions, each module SM i The duty cycle of the access circuit is D, and the SM of each module. i Capacitor C i The voltage at both ends is V D / ND, Module SM1 ~ Module SM N Module SM N+1 ~Module SM 2N After superposition, they form unipolar multilevel voltages, which are combined with the SM modules on both sides. i This enables the inverter to generate multi-level AC output.

[0041] In the specific implementation process, the adjacent module SM i A switching transistor S is connected between them. j The specific connection structure of (j = 1, 2, ..., 2N-2) is as follows: module SM1 ~ module SM N Switch S1 to switch S are connected in sequence. N-1 Module SM N+1 ~Module SM 2N A switching transistor S is connected in sequence between them. N ~Switching transistor S 2N-2 Switch S1 to switch S N-1 The first poles are respectively with modules SM1 to SM N-1 The third terminal is connected to the switching transistor S1 to the switching transistor S2. N-1 The second poles are respectively connected to modules SM2 to SM3. N The third terminal is connected; the switching transistor SN ~Switching transistor S 2N-2 The first pole and module SM N+1 ~Module SM 2N-1 The third terminal is connected to the switching transistor S. N ~Switching transistor S 2N-2 The second pole and module SM respectively N+2 ~Module SM 2N The third terminal is connected; each switch S j The third pole is connected to the control signal.

[0042] In the specific implementation process, due to module SM i The capacitance values ​​of the capacitors in the middle cannot be exactly the same, although the SM values ​​of each module... i Although the circuit connection time is the same, there will still be SM in each module. i The problem of capacitor voltage imbalance, therefore, in adjacent module SM i Add a charging switch S between them j and in two modules SM i When the capacitors in the inverter are grounded, they are turned on simultaneously, forming a charging circuit between the capacitors to achieve capacitor voltage balance.

[0043] Example 2

[0044] In the specific implementation process, this embodiment uses a five-level inverter as an example to illustrate the working principle of the single-supply boost multilevel inverter. The five-level inverter includes a DC power supply V. D Inductor L1, inductor L2 and module SM i (i = 1, 2, 3, 4);

[0045] The second terminal of module SM1 is connected to the first terminal of module SM2, and the second terminal of module SM3 is connected to module SM4; the DC power supply V D The positive terminals are connected to the second terminal of inductor L1 and the first terminal of inductor L2, respectively, and the DC power supply V D The negative terminals are connected to the second terminals of module SM2 and module SM4, respectively; the first terminals of inductor L1 and inductor L2 are connected to the first terminals of module SM1 and module SM3, respectively.

[0046] The module SM i (i = 1, 2, 3, 4) are obtained from capacitor C i and switching transistor SM i1 SM switching transistor i2 Composition; the switching transistor SM i1 SM switching transistor i2 Series connection, switching transistor SM i1 The second terminal and the switching transistor SMi2 The first terminal is connected; capacitor C i and series-connected switching transistor SM i1 SM switching transistor i2 Parallel connection, capacitor C i One end and the switching transistor SM i1 The first terminal is connected to capacitor C. i The other end and the switching transistor SM i2 The second end connection; module SM i The first, second, and third terminals are respectively the switching transistor SM i1 The second terminal, the switching transistor SM i2 The second terminal, the switching transistor SM i1 The first end;

[0047] A switching transistor S1 is connected between modules SM1 and SM2. 11 The first terminal is connected to the first terminal of the switching transistor S1, and the switching transistor SM 21 The first terminal is connected to the second terminal of the switching transistor S1; a switching transistor S2 is connected between modules SM3 and SM4. 31 The first terminal is connected to the first terminal of the switching transistor S2, and the switching transistor SM 41 The first terminal is connected to the second terminal of the switching transistor S2;

[0048] An inductor L is connected in series between the first terminal of module SM1 and the first terminal of module SM3. P Capacitor C P The first terminal of module SM1 and the first terminal of module SM3 are respectively connected to inductor L P The first terminal, capacitor C P The second end is connected to the inductor L. P The second terminal and capacitor C P The first end is connected. The inductor L P Inductor L S These are the transmitting coil and the picking coil of the wireless power transfer system, respectively, with capacitor C. P Capacitor C S These are the series compensation capacitors at the transmitter and receiver ends of the wireless power transmission system, respectively, and M is the inductor L. S Inductor L P The mutual inductance between them, R is the load resistance, and L is the inductance. S Load resistor R, capacitor C S Series connection; the AC power generated by the above multilevel inverter is transmitted through the transmitting coil L P Transmitted to pickup coil L S And it is ultimately consumed by the load resistor R, realizing contactless energy transfer.

[0049] In practical implementation, the working principle of the five-level inverter is as follows:

[0050] The working principle of an inverter is explained in detail using a five-level inverter as an example. Figure 2 This is a topology diagram of a five-level inverter. Figure 3 These are the main operating waveforms of the inverter. Figures 4 to 10 These are the operating modes of a five-level inverter and their corresponding equivalent circuit diagrams, where V pi The inverter output voltage flows through capacitor C. P The current flowing through resistor R is the transmitting current, and the current flowing through resistor R is the pickup current. The control method of the five-level inverter is as follows:

[0051] First working mode: such as Figure 4 As shown; control switch SM 12 SM 22 SM 32 SM 42 When switches S1 and S2 are turned on and the remaining switches are turned off, all modules are not connected to the circuit; at this time, inductor L1 passes through switch SM. 12 SM 22 With DC power supply V D Connects and stores energy; inductor L2 connects to switch SM. 32 SM 42 With DC power supply V D Connect and store energy; since there are no modules connected to the circuit on either side, the voltage on both sides is equal and 0, i.e., V. pi =0; In this mode, capacitors C1 and C2 share a common ground, capacitors C3 and C4 share a common ground, and switching transistors S1 and S2 are turned on, achieving voltage balance between capacitors C1 and C2, and voltage balance between capacitors C3 and C4.

[0052] Second working mode: such as Figure 5 As shown; control switch SM 11 SM 22 SM 32 SM 42 With S2 turned on, the other switches are turned off, meaning module SM1 is connected to the circuit, while modules SM2, SM3, and SM4 are not connected. Capacitor C1 is connected to switch SM. 11 SM 22 With inductor L1 and DC power supply V D When connected, inductor L1 releases energy and charges capacitor C1. At this time, inductor L1 and module SM1 can be regarded as the boost section, and the voltage amplitude across capacitor C1 is V. D / 2D, meaning the circuit on the left generates an amplitude of V D / 2D unipolar voltage; simultaneously, since modules SM3 and SM4 are not connected to the circuit, the voltage on the right side is 0, at which point the output voltage V pi =-V D / 2D; In this mode, capacitors C1 and C2 are not grounded, while capacitors C3 and C4 are grounded. Therefore, switch S1 is turned off and switch S2 is turned on, achieving voltage balance between capacitors C3 and C4.

[0053] Third working mode: such as Figure 6 As shown; control switch SM 12 SM 21 SM 32 SM 42 With S2 turned on, the other switches are turned off, meaning module SM2 is connected to the circuit, while modules SM1, SM3, and SM4 are not connected. Capacitor C1 is connected to switch SM2. 12 SM 21 With inductor L1 and DC power supply V D When connected, inductor L1 releases energy and charges capacitor C1. At this time, inductor L1 and module SM2 can be regarded as the boost section, and the voltage amplitude across capacitor C2 is V. D / 2D, meaning the circuit on the left generates an amplitude of V D / 2D unipolar voltage; simultaneously, since modules SM3 and SM4 are not connected to the circuit, the voltage on the right side is 0, at which point the output voltage V pi =-V D / 2D; In this mode, capacitors C1 and C2 are not grounded, while capacitors C3 and C4 are grounded. Therefore, switch S1 is turned off and switch S2 is turned on, achieving voltage balance between capacitors C3 and C4.

[0054] Fourth working mode: such as Figure 7 As shown; control switch SM 11 SM 21 SM 32 SM 42 With S2 turned on, the other switches are turned off, meaning modules SM1 and SM2 are connected to the circuit, while modules SM3 and SM4 are not connected. Capacitors C1 and C2 are connected through switch SM. 11 and SM 21 With inductor L1 and DC power supply V D When connected, inductor L1 releases energy to charge capacitors C1 and C2. At this time, inductor L1 and modules SM1 and SM2 can be regarded as the boost section, and the voltage amplitude across capacitors C1 and C2 is V. D / 2D, because modules SM1 and SM2 are cascaded, the circuit on the left generates an amplitude of V. D / D's unipolar voltage; simultaneously, since modules SM3 and SM4 are not connected to the circuit, the voltage on the right side is 0, at which point the output voltage V pi =-V D / D; In this mode, capacitors C1 and C2 are not grounded, while capacitors C3 and C4 are grounded. Therefore, switch S1 is turned off and switch S2 is turned on, achieving voltage balance between capacitors C3 and C4.

[0055] Fifth working mode: such as Figure 8 As shown; control switch SM 12 SM 22 SM 31 SM 42 With S1 turned on, the other switches are turned off, meaning module SM3 is connected to the circuit, while modules SM1, SM2, and SM4 are not connected. Capacitor C3 is connected to switch SM. 31 SM 42 With inductor L2 and DC power supply V D When connected, inductor L2 releases energy and charges capacitor C3. At this time, inductor L2 and module SM3 can be regarded as the boost section, and the voltage amplitude across capacitor C2 is V. D / 2D, meaning the circuit on the right generates an amplitude of V. D / 2D unipolar voltage; simultaneously, since modules SM1 and SM2 are not connected to the circuit, the voltage on the left side is 0, at which point the output voltage V pi =V D / 2D; In this mode, capacitors C1 and C2 share a common ground, while capacitors C3 and C4 do not share a common ground. Therefore, switch S1 is turned on and switch S2 is turned off, achieving voltage balance between capacitors C1 and C2.

[0056] Sixth working mode: such as Figure 9 As shown; control switch SM 12 SM 22 SM 32 SM 41 With S1 turned on, the other switches are turned off, meaning module SM4 is connected to the circuit, while modules SM1, SM2, and SM3 are not connected. Capacitor C4 is connected to switch SM. 32 SM 41 With inductor L2 and DC power supply V D When connected, inductor L2 releases energy and charges capacitor C4. At this time, inductor L2 and module SM4 can be regarded as the boost section, and the voltage amplitude across capacitor C2 is V. D / 2D, meaning the circuit on the right generates an amplitude of V. D / 2D unipolar voltage; simultaneously, since modules SM1 and SM2 are not connected to the circuit, the voltage on the left side is 0, at which point the output voltage V pi =V D / 2D; In this mode, capacitors C1 and C2 share a common ground, while capacitors C3 and C4 do not share a common ground. Therefore, switch S1 is turned on and switch S2 is turned off, achieving voltage balance between capacitors C1 and C2.

[0057] Seventh working mode: such as Figure 10 As shown; control switch SM 12 SM 22 SM 31 SM 41 With S1 turned on, the other switches are turned off, meaning modules SM3 and SM4 are connected to the circuit, while modules SM1 and SM2 are not connected. Capacitors C3 and C4 are connected through switch SM. 31 and SM 41 With inductor L2 and DC power supply V D When connected, inductor L2 releases energy to charge capacitors C3 and C4. At this time, inductor L2 and modules SM3 and SM4 can be regarded as the boost section, and the voltage amplitude across capacitors C3 and C4 is V. D / 2D, because modules SM1 and SM2 are cascaded, the circuit on the right generates an amplitude of V. D / D's unipolar voltage; simultaneously, since modules SM1 and SM2 are not connected to the circuit, the voltage on the left side is 0, at which point the output voltage V pi =V D / D; In this mode, capacitors C1 and C2 share a common ground, while capacitors C3 and C4 do not. Therefore, switch S1 is turned on and switch S2 is turned off, achieving voltage balance between capacitors C1 and C2.

[0058] Example 3

[0059] Specifically, based on Example 1, the solution will be described in conjunction with specific embodiments to further demonstrate its technical effects. Specifically:

[0060] In the specific implementation process, the switching transistor S j Select an NPN transistor, with the switching transistor S... j The first electrode is the collector, and the switching transistor S j The second electrode is the emitter, and the switch S j The third pole is the base pole.

[0061] When the switching transistor S j When all transistors are IGBTs; the switching transistor S j The first electrode is the collector of the IGBT, the second electrode is the emitter of the IGBT, and the switching transistor S is the collector. j The third electrode is the gate electrode.

[0062] When the switching transistor S j When all are MOSFETs; switch Sj The first electrode is the drain of the MOSFET, the second electrode is the source of the MOSFET, and the switch S is the source of the MOSFET. j The third electrode is the gate electrode.

[0063] Example 4

[0064] Simulation verification of the present invention

[0065] To verify the performance of the multilevel inverter of this invention, a simulation model of a wireless power transfer system based on a five-level inverter was built in the Matlab / Simulink simulation platform and simulated. The parameters were set as follows: capacitor C1 = 88μF, capacitor C2 = 80μF, capacitor C4 = 80μF, capacitor C3 = 70μF, inductor L1 = L2 = 430μH, and power supply voltage V. D =100V, duty cycle D=0.3, L S =L P =220μH, M=44μH, capacitance C S = Capacitor C P =16.188nF, R=10Ω, inverter switching frequency is 85kHz.

[0066] Figures 11-13 The horizontal axis in the waveform graph represents the test time (unit: s). Since the simulation verification mainly observes the periodic changes of the waveform, the specific value of the test time is hidden. Figure 11 Simulated waveforms of the drive signals for each switching transistor, including SM. 11 and SM 12 Complementary, SM 21 and SM 22 Complementary, SM 31 and SM 32 Complementary, SM 41 and SM 42 Complementary, consistent with theoretical analysis

[0067] Figure 12 Simulated waveforms of the inverter output voltage and current, and the current at the system pickup terminal, show that the inverter output voltage is a five-level waveform. The output voltage is approximately 167V in the second, third, fifth, and sixth operating modes, and approximately 334V in the fourth and seventh operating modes. These results are consistent with the theoretical analysis, verifying the proposed inverter's boost capability. Furthermore, the inverter output current is sinusoidal and at the same potential as the inverter output voltage; the current at the system pickup terminal is also sinusoidal, indicating that the system achieves wireless power transmission. Figure 13The voltage waveforms across capacitors C1, C2, C3, and C4 are shown. Measurements show that the voltages across capacitors C1 and C2 are essentially the same, and the voltages across capacitors C3 and C4 are essentially the same, thus achieving capacitor voltage balance in the inverter of this invention.

[0068] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A single-supply boost multilevel inverter, applied in a wireless power transmission system, characterized in that, The inverter includes a DC power supply V. D Inductor L1, inductor L2 and module SM i (i = 1…2N); where module SM1 to module SM N Connect sequentially, adjacent modules SM1 to SM2. N A switching transistor S is connected between them. j (j = 1, 2, ..., N-1); Module SM N+1 ~Module SM 2N Connect sequentially, adjacent modules SM N+1 ~Module SM 2N A switching transistor S is connected between them. j (j = N, N+1, ..., 2N-2); Among them, modules SM1 to SM N-1 The second end is connected to modules SM2 to SM3 respectively. N The first end connection; the module SM N+1 ~Module SM 2N-1 The second end is connected to module SM in sequence. N+2 ~Module SM 2N Connection; the DC power supply V D The positive terminals are connected to the second terminal of inductor L1 and the first terminal of inductor L2, respectively, and the DC power supply V D The negative terminals and module SM are respectively N The second end, module SM 2N The second terminal is connected; the first terminal of inductor L1 and the second terminal of inductor L2 are respectively connected to the first terminal of module SM1 and module SM N+1 The first end is connected.

2. The single-supply boost multilevel inverter according to claim 1, characterized in that, The module SM i (i = 1…2N) is determined by capacitor C i and switching transistor SM i1 SM switching transistor i2 Composition; the switching transistor SM i1 SM switching transistor i2 Series connection, switching transistor SM i1 The second terminal and the switching transistor SM i2 The first terminal is connected; capacitor C i and series-connected switching transistor SM i1 SM switching transistor i2 Parallel connection, capacitor C i One end and the switching transistor SM i1 The first terminal is connected to capacitor C. i The other end and the switching transistor SM i2 The second end connection; module SM i The first, second, and third terminals are respectively the switching transistor SM i1 The second terminal, the switching transistor SM i2 The second terminal, the switching transistor SM i1 The first end.

3. The single-supply boost multilevel inverter according to claim 2, characterized in that, The first end of module SM1, module SM N+1 An inductor L is connected in series between the first terminals. P Capacitor C P The first end of module SM1, module SM N+1 The first terminal is connected to the inductor L respectively P The first terminal, capacitor C P The second end is connected to the inductor L. P The second terminal and capacitor C P The first end is connected; The inductor L P Inductor L S These are the transmitting coil and the picking coil of the wireless power transfer system, respectively, with capacitor C. P Capacitor C S These are the series compensation capacitors at the transmitter and receiver ends of the wireless power transmission system, respectively, and M is the inductor L. S Inductor L P The mutual inductance between them, R is the load resistance, and L is the inductance. S Load resistor R, capacitor C S Series connection; the AC power generated by the above multilevel inverter is transmitted through the transmitting coil L P Transmitted to pickup coil L S And it is ultimately consumed by the load resistor R, realizing contactless energy transfer.

4. The single-supply boost multilevel inverter according to claim 3, characterized in that, When module SM i When connected to the circuit, capacitor C i Through the switching transistor SM i1 When connected to inductor L1 or inductor L2, the energy released by the inductor is the capacitance C. i Charging; when all modules SM i When neither inductor L1 nor inductor L2 is connected to the DC power supply V, D Parallel connection and energy storage; under steady-state conditions, each module SM i The duty cycle of the access circuit is D, and the SM of each module. i Capacitor C i The voltage at both ends is V D / ND, Module SM1 ~ Module SM N Module SM N+1 ~Module SM 2N After superposition, they form unipolar multilevel voltages, which are combined with the SM modules on both sides. i This enables the inverter to generate multi-level AC output.

5. The single-supply boost multilevel inverter according to claim 4, characterized in that, The adjacent module SM i A switching transistor S is connected between them. j The specific connection structure of (j = 1, 2, ..., 2N-2) is as follows: module SM1 ~ module SM N Switch S1 to switch S are connected in sequence. N-1 Module SM N+1 ~Module SM 2N A switching transistor S is connected in sequence between them. N ~Switching transistor S 2N-2 Switch S1 to switch S N-1 The first poles are respectively with modules SM1 to SM N-1 The third terminal is connected to the switching transistor S1 to the switching transistor S2. N-1 The second poles are respectively with module SM2 to module SM N The third terminal is connected; the switching transistor S N ~Switching transistor S 2N-2 The first pole and module SM N+1 ~Module SM 2N-1 The third terminal is connected to the switching transistor S. N ~Switching transistor S 2N-2 The second pole and module SM respectively N+2 ~Module SM 2N The third terminal is connected; each switch S j The third pole is connected to the control signal.

6. The single-supply boost multilevel inverter according to claim 5, characterized in that, During the inverter's duty cycle, all modules SM i The duty cycles of the access circuits are equal, and each module SM i The phase difference between the circuits connected to each other is equal.

7. The single-supply boost multilevel inverter according to claim 5, characterized in that, The switching transistor S j It is an NPN transistor, and the switching transistor is S. j The first electrode is the collector, and the switching transistor S j The second electrode is the emitter, and the switch S j The third pole is the base pole.

8. The single-supply boost multilevel inverter according to claim 5, characterized in that, The switching transistor S j All are IGBT transistors; switching transistor S j The first electrode is the collector of the IGBT, the second electrode is the emitter of the IGBT, and the switching transistor S is the collector. j The third electrode is the gate electrode.

9. A single-supply boost multilevel inverter according to claim 5, characterized in that, The switching transistor S j All are MOSFETs; the switching transistor S j The first electrode is the drain of the MOSFET, the second electrode is the source of the MOSFET, and the switch S is the source of the MOSFET. j The third electrode is the gate electrode.

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