SRAM sense amplifier anti-flip redundancy structure

Abstract

The application discloses an SRAM sensitive amplifier anti-inversion redundancy structure and belongs to the field of integrated circuits, comprising two structure-same sensitive amplifiers and a digital state machine. Each sensitive amplifier comprises a main amplification structure and a redundancy circuit; the main amplification structure realizes comparison and amplification of a differential signal, and the redundancy circuit is connected with the main amplification structure; the digital state machine is used to judge the working state of the sensitive amplifier and output a control signal to control whether the two redundancy circuits intervene or not, so that the differential signal is amplified in the reverse direction or the same direction. The application adds an auxiliary structure on the basis of the original SA circuit, uses a judgment mechanism to confirm whether inversion occurs in the initial mode of the SA, adopts a redundancy structure to re-invert the SA output data if inversion occurs, and finally realizes normal output of the SA in the current stage after twice inversion, and the working state of other SAs is not affected.

Description

An anti-flip redundancy structure for SRAM sensitive amplifiers Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an anti-flip redundancy structure for an SRAM sensitive amplifier. Background Technology

[0002] In SRAM (Static Random-Access Memory), when reading from the memory array, the information from the memory array is amplified (with increased swing) in two stages to retrieve the data and achieve the final high or low level output. The high or low level output drives the push-pull structure of the ODT to achieve the data output (high or low level) of the port.

[0003] During the two-stage data amplification process, an SA (Sensitive Amplifier) ​​is used to compare the differential data output from the 6T unit. In this process, the first stage of the two-stage SA may be reversed due to the input of the 6T unit, resulting in the SA output data and logic value being reversed, leading to abnormal data extraction. Summary of the Invention

[0004] The purpose of this invention is to provide an anti-flip redundancy structure for SRAM sensitive amplifiers to solve the problem of SA inversion in the prior art.

[0005] To address the aforementioned technical problems, this invention provides an anti-flip redundancy structure for an SRAM sensitive amplifier, comprising:

[0006] Two identical sensitive amplifiers are used, each of which includes a main amplification structure and a redundant circuit. The main amplification structure compares and amplifies the differential signals, and the redundant circuit is connected to the main amplification structure.

[0007] A digital state machine is used to determine the operating state of the sensitive amplifier and output control signals to control whether two redundant circuits are engaged, thereby amplifying the differential signal in either the reverse or the same direction.

[0008] In one embodiment, the sensitive amplifier includes PMOS transistors MP1 to MP2 and NMOS transistors MN1 to MN9;

[0009] The gates of PMOS transistors MP1 and MP2 are both connected to a low level GS, and their sources are both connected to a high level VS. Their drains are connected to the drains of NMOS transistors MN5 and MN6, respectively. The drains of PMOS transistors MP1 and MP2 are connected to the source and drain of PMOS transistor MP3, respectively. The gates of NMOS transistors MN5 and MN6 are connected to the positive input terminal IP and the negative input terminal IN, respectively, and their sources are connected to the drains of NMOS transistors MN3 and MN4, respectively. The sources of NMOS transistors MN5 and MN6 are connected to the source and drain of PMOS transistor MP4, respectively. The gate of PMOS transistor MP3 is connected to the signal Equal, and the gate of PMOS transistor MP4 is connected to the signal AMP_Start.

[0010] The drain of NMOS transistor MN3 is connected to the drain of NMOS transistor MN1 and the gate of NMOS transistor MN4; the drain of NMOS transistor MN4 is connected to the drain of NMOS transistor MN2 and the gate of NMOS transistor MN3; the sources of NMOS transistors MN3 and MN4 are connected to the drain of NMOS transistor MN8.

[0011] The gate of NMOS transistor MN1 is connected to its own drain, and its source is connected to the drain of NMOS transistor MN7; the gate of NMOS transistor MN2 is connected to its own drain, and its source is connected to the drain of NMOS transistor MN9; the gates of NMOS transistors MN7 and MN9 are both connected to the signal Re.Ctrl, and the gate of NMOS transistor MN8 is connected to the signal AMP_Start; the sources of NMOS transistors MN7 to MN9 are all connected to a low level GS.

[0012] In one embodiment, the digital state machine includes comparators Comp1 to Comp2, selectors MUX1 to MUX3, AND gates AND1 to AND2, NOT gates NOT1 to NOT7, NAND gates NAND1 to NAND3, NMOS transistors MN31 to MN32, and D flip-flops;

[0013] The two inputs of comparator Comp1 are connected to the outputs of the first-stage sensitive amplifier. The output of comparator Comp1 and the signal VH are both connected to the inputs of selector MUX1. The output of selector MUX1 is connected to one input of NAND gate NAND1. The drain of NMOS transistor MN31 is connected to the input of NOT gate NOT1, the gate is connected to the output of NOT gate NOT1, and the source is connected to a low level. The output of NOT gate NOT1 is connected to the other input of NAND gate NAND1. The output of NAND gate NAND1 is simultaneously connected to the input of NOT gate NOT4, the output of NOT gate NOT2, the input of NOT gate NOT3, one input of NAND gate NAND3, and the D terminal of D flip-flop. The output of NOT gate NOT4 is simultaneously connected to the CP terminal and the RST terminal of D flip-flop.

[0014] The two inputs of the second-stage sensitive amplifier are connected to the outputs of the first-stage sensitive amplifier, and the output of the second-stage sensitive amplifier is connected to the input of comparator Comp2. The output of comparator Comp2 and the signal VH are both connected to the inputs of selector MUX2, and the output of selector MUX2 is connected to the first input of NAND gate NAND2. The two inputs of AND gate AND1 are connected to nodes N1 and N3, and the output of AND gate AND1 and the signal VH are both connected to the inputs of selector MUX3. The output of selector MUX3 is connected to the second input of NAND gate NAND2, and the third input of NAND gate NAND2 is connected to node N4.

[0015] The output of NAND gate NAND2, the other input of NAND gate NAND3, the output of NOT gate NOT5, and the input of NOT gate NOT6 are all connected to node N2. The output of NOT gate NOT6 is connected to the input of NOT gate NOT5. The output of NAND gate NAND3 is connected to one input of AND gate AND2. The drain of NMOS transistor MN32 is connected to the input of NOT gate NOT7, the gate is connected to the output of NOT gate NOT7, and the source is connected to a low level. The output of NOT gate NOT7 is connected to the other input of AND gate AND2.

[0016] The SRAM sensitive amplifier anti-flip redundancy structure provided by this invention includes two identical sensitive amplifiers and a digital state machine. Each sensitive amplifier includes a main amplification structure and a redundant circuit. The main amplification structure compares and amplifies the differential signals, and the redundant circuit is connected to the main amplification structure. The digital state machine determines the operating state of the sensitive amplifier and outputs control signals to control whether the two redundant circuits are engaged, thereby amplifying the differential signals in either the inverse or the same direction. This invention operates in two modes: the first mode operates in the same direction, where the differential input and differential output are directly proportional; the second mode operates in the inverse direction, where the differential input and differential output are inversely proportional. Switching between the two modes via the digital state machine allows for SA initialization in the initial circuit state, or dynamic SA mode determination via an additional register to optimize the SA inversion, ultimately ensuring the normal functioning of the memory array in the read path. Attached Figure Description

[0017] Figure 1 is a schematic diagram of the redundant SA circuit.

[0018] Figure 2 is a schematic diagram of the first-stage sensitive amplifier.

[0019] Figure 3 is a schematic diagram of the second-stage sensitive amplifier.

[0020] Figure 4 is a schematic diagram of the structure of a digital state machine. Detailed Implementation

[0021] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the anti-flip redundancy structure for an SRAM sensitive amplifier proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0022] This invention provides an anti-flip redundancy structure for SRAM sensitive amplifiers, comprising two sensitive amplifiers and a digital state machine. Each sensitive amplifier includes a main amplification structure and a redundant circuit; the main amplification structure compares and amplifies the differential signals, and the redundant circuit is connected to the main amplification structure; the digital state machine determines the operating state of the sensitive amplifiers and outputs control signals to control whether the two redundant circuits are engaged, thereby amplifying the differential signals in either the reverse or same direction.

[0023] The structure of the sensitive amplifier is shown in Figure 1, including PMOS transistors MP1-MP2 and NMOS transistors MN1-MN9. The gates of PMOS transistors MP1 and MP2 are both connected to a low level (GS), and their sources are both connected to a high level (VS). Their drains are connected to the drains of NMOS transistors MN5 and MN6, respectively. The drains of PMOS transistors MP1 and MP2 are connected to the source and drain of PMOS transistor MP3, or to the drain and source of PMOS transistor MP3, respectively. The gates of NMOS transistors MN5 and MN6 are connected to the positive input terminal IP and the negative input terminal IN, respectively, and their sources are connected to the drains of NMOS transistors MN3 and MN4, respectively. The sources of NMOS transistors MN5 and MN6 are connected to the source and drain of PMOS transistor MP4, or to the drain and source of PMOS transistor MP4, respectively. The gate of PMOS transistor MP3 is connected to the signal... Equal, the gate of PMOS transistor MP4 is connected to the signal AMP_Start; the drain of NMOS transistor MN3 is simultaneously connected to the drain of NMOS transistor MN1 and the gate of NMOS transistor MN4; the drain of NMOS transistor MN4 is simultaneously connected to the drain of NMOS transistor MN2 and the gate of NMOS transistor MN3; the sources of NMOS transistors MN3 and MN4 are simultaneously connected to the drain of NMOS transistor MN8; the gate of NMOS transistor MN1 is connected to its own drain, and its source is connected to the drain of NMOS transistor MN7; the gate of NMOS transistor MN2 is connected to its own drain, and its source is connected to the drain of NMOS transistor MN9; the gates of NMOS transistors MN7 and MN9 are both connected to the signal Re.Ctrl, and the gate of NMOS transistor MN8 is connected to the signal AMP_Start; the sources of NMOS transistors MN7 to MN9 are all connected to a low level GS.

[0024] Please refer to Figure 1. The gates of PMOS transistors MP1 and MP2 are connected to a low level to achieve resistive load characteristics. NMOS transistors MN5 and MN6 form two input differential pairs. The lower part is a cross-coupled structure composed of NMOS transistors MN3 and MN4, which can provide a large small-signal gain through positive feedback and provide faster output in the large-signal region. The NMOS transistors MN1 and MN2 on both sides are redundant circuit structures. They can be turned on by the lower signal Re.Ctrl to achieve the purpose of inverting the output logic. Referring to Figure 1, when the level of the positive input terminal IP is high, the level of the negative output terminal ON is low. When the level of the negative input terminal IN is low, the level of the positive output terminal OP is high. At this time, the input level relationship is IP > IN and the output level ON < OP, which means inversion. Correspondingly, when the level of the positive input terminal IP is high, the level of the negative output terminal ON is high. When the level of the negative input terminal IN is low, the level of the positive output terminal OP is low. Therefore, the input level is IP > IN and ON > OP.

[0025] The following analysis examines the small-signal operation modes of the circuit shown in Figure 1.

[0026] I. Assuming Re.Ctrl is low (i.e., the redundant circuit is in a non-operating state), and assuming each MOSFET in the circuit has a suitable operating point, then from one side, each side is a source-level negative feedback amplifier. From the left side, its small-signal gain is:

[0027]

[0028]

[0029] Among them, V ON For output negative terminal voltage, V IP Input positive terminal voltage, V OP Output positive terminal voltage, V IN For the negative input voltage, R pmos g is the on-resistance of PMOS transistor MP1 (or MP2). mN For the transconductance of NMOS transistor MN5 (or MN6), g m3 Let Id be the partial derivative of the current Id flowing through the MN3 channel with respect to the gate-source level Vgs of MN3, i.e. g m4 Let Id be the partial derivative of the current Id flowing through the MN4 channel with respect to the gate-source level Vgs of MN4, i.e. g m3 =g m4 Subtracting equation (2) from equation (1), we get:

[0030]

[0031] In other words, if the denominator is less than 0, then the input and output are in the same direction, and g... mN >g mB (Assume g) m3 =g m4 =g mB Alternatively, the width-to-length ratio (W / L) of the differential pair tubes and cross-coupled tubes can be adjusted.

[0032] This is called unidirectional, because the differential large signal input and output are unidirectional with the small signal region. Therefore, at a suitable operating point, the large signal also has unidirectional output characteristics.

[0033] II. Assuming the Re.Ctrl level is high (i.e., redundant circuitry is involved), and assuming each MOSFET in the circuit has a suitable operating point, then from a single-side perspective, each side is a source-level negative feedback amplifier. One point to note is the source-level equivalent small-signal impedance r. s.eq Let g be ( m1 =g m2 =g mA ):

[0034]

[0035] g m1 Let Id be the partial derivative of the current Id flowing through the MN1 channel with respect to the gate-source level Vgs of MN1, i.e. g m2 Let Id be the partial derivative of the current Id flowing through the MN2 channel with respect to the gate-source level Vgs of MN2, i.e. g mA =g m1 =g m2 g mB =g m3 =g m4 The corresponding left and right magnification formulas are obtained as follows:

[0036]

[0037]

[0038] Subtracting equation (6) from equation (5) yields

[0039]

[0040] To achieve reverse output, it's necessary to consider that NMOS transistors NM1 and NM3 have the same gate-source voltage Vgs and similar characteristics, therefore, the difference in g must be considered. mB <gmA It can achieve the following: if the denominator is greater than 0, the data output will be inverted. mA and g mB Alternatively, this can be achieved by setting different M values ​​for the NMOS transistors (i.e., the number of MOS transistors connected in parallel). Under suitable operating conditions, large and small signals have the same polarity.

[0041] The two sensitive amplifiers in this invention have the same structure. Figure 2 shows the first-stage sensitive amplifier (SA1) in this invention. This structure is the same as in Figure 1, where levels AP1 and AP2 are output from the 6T memory cell. The differential output of the 6T cell outputs "1" and "0", or "0" and "1", respectively. However, in reality, due to transmission effects and signal interference within the circuit, the output is not a pure "1" and "0", but rather 1.2 and 0.9 (when the system voltage is 1.2V). After passing through the first-stage SA amplifier, it may become 1.2 and 1.0 (SA is positioned close to the output port to reduce signal loss and distortion from the retrieved data to the port). In other words, it is impossible to determine which is high and which is low. Therefore, when the output reaches the second-stage SA amplifier, high and low levels can be amplified (swing amplification), for example, 1.2 and 0.5. After passing through the output stage, logic "1" and "0" can be output. The first stage (and the subsequent second stage) SA amplifier operates in the same direction by default, meaning that the redundant circuit structure does not participate in the operation, and the default level signal Ctrl_1 is low; where Equal_1 is the pre-charge equal potential signal before data reading.

[0042] Figure 3 shows the second-stage sensitive amplifier (SA2) in this invention. Its basic structure is the same as SA1, except that they have different MOS transistor sizes. SA1 requires a larger bandwidth (GBW) and input impedance, while SA2 is expected to have a larger small-signal gain and a larger large-signal swing and slew rate. Therefore, corresponding MOS transistor designs are required based on these requirements, which are well known to those skilled in the art and will not be described in detail here. SA2 receives the differential signal amplified by SA1 and further amplifies it.

[0043] Figure 4 is a schematic diagram of the digital state machine architecture in this invention, including comparators Comp1-Comp2, selectors MUX1-MUX3, AND gates AND1-AND2, NOT gates NOT1-NOT7, NAND gates NAND1-NAND3, NMOS transistors MN31-MN32, and D flip-flops. The two inputs of comparator Comp1 are respectively connected to the output of the first-stage sensitive amplifier. The output of comparator Comp1 and the signal VH are both connected to the input of selector MUX1. The output of selector MUX1 is connected to NAND gate NAND1. One input terminal; the drain of NMOS transistor MN31 is connected to the input terminal of NOT gate NOT1, the gate is connected to the output terminal of NOT gate NOT1, and the source is connected to a low level; the output terminal of NOT gate NOT1 is connected to the other input terminal of NAND gate NAND1; the output terminal of NAND gate NAND1 is simultaneously connected to the input terminal of NOT gate NOT4, the output terminal of NOT gate NOT2, the input terminal of NOT gate NOT3, one input terminal of NAND gate NAND3, and the D terminal of D flip-flop; the output terminal of NOT gate NOT4 is simultaneously connected to the CP terminal and the RST terminal of D flip-flop; the two inputs of the second-stage sensitive amplifier The first and second stages of the sensitive amplifier are connected to their respective outputs. The output of the second stage sensitive amplifier is connected to the input of comparator Comp2. The output of comparator Comp2 and the signal VH are both connected to the input of selector MUX2. The output of selector MUX2 is connected to the first input of NAND gate NAND2. The two inputs of AND gate AND1 are connected to nodes N1 and N3. The output of AND gate AND1 and the signal VH are both connected to the input of selector MUX3. The output of selector MUX3 is connected to the second input of NAND gate NAND2. The third input of gate 2 is connected to node N4; the output of NAND gate NAND2, the other input of NAND gate NAND3, the output of NOT gate NOT5, and the input of NOT gate NOT6 are all connected to node N2, and the output of NOT gate NOT6 is connected to the input of NOT gate NOT5; the output of NAND gate NAND3 is connected to one input of AND gate AND2; the drain of NMOS transistor MN32 is connected to the input of NOT gate NOT7, the gate is connected to the output of NOT gate NOT7, and the source is connected to a low level; the output of NOT gate NOT7 is connected to the other input of AND gate AND2.

[0044] First, consider the number of ports in the circuit. Under standard conditions, the number of sensitive amplifiers is twice the number of ports. Add the module within the dashed box in the lower left corner of Figure 4 to implement a simple register function. That is, when the input is high, the circuit is internally reset. Specifically, when REG inputs a high level, node N4 is low, node N1 is high, and node N2 is also high. Due to the two inverters (NOT2 and NOT3, NOT5 and NOT6), Ctrl_1 and Ctrl_2 output low levels. The redundant circuit does not intervene and the selectors MUX1 and MUX2, controlled by nodes N1 and N2 (node ​​N1 high level), are activated. When the N1 node is low, the lower Comparator_out is output. When the N1 node is low, the upper Comparator_out mode is set to prepare to receive data from the two comparators. Then, when the REG input is low, the internal port control is handed over to the corresponding Comparator_out. At this time, the FLAG output is 0. The FLAG signal is logically associated with the read signal through a gate circuit. This indicates that the circuit can perform a read operation (SA can be corrected). Then, all register 6T units start writing the signal "0", and then read. After reading, no operation is performed, and the read control signal is set high (and only read once or multiple times). Note that there is a flip-flop DFF used to detect stable level when the first stage flips and adjusts redundancy. The principle is that when node N1 changes from the initial high level (node ​​N3 is initially high, so MUX3 selects the lower path; by default, if the first stage does not adjust, SA2 is released for adjustment) to low level, MUX3 still selects the lower path due to the delay of node N3, so SA2 does not adjust at this time. When the transition of node N1 passes through the delayed inverter to reach flip-flop DFF, causing node N3 to transition (become low), MUX3 becomes the upper path output, and SA2 starts to adjust.

[0045] Based on the above reset steps, we will discuss different scenarios.

[0046] ① Case where SA1 does not flip and SA2 does not flip:

[0047] In the first-stage sensitive amplifier, AP1 reads "0" and AP2 reads "1". Therefore, the Z3 signal level is lower than Z4, resulting in a low output signal from comparator Comp1. Node N1 remains high, so Ctrl_1 is low, and SA1 operates in the same-direction mode (consistent with the initial logic settings). At this point, node N1 is high (causing the DFF to reset), and node N3 is also high, so selector MUX3 outputs a high level, releasing the sampling of the second-stage SA2 comparison signal. If Z3 is "0" and Z4 is "1", without flipping, the Z1 output signal level is lower than Z2, so Comp2 outputs a low level. Node N2 then outputs a high level, and selector MUX2 continuously receives input from comparator Comp2. Ctrl_2 is low, the SA2 redundancy section does not engage, and SA2 operates in the same-direction mode. At this time, FLAG is 0 (the FLAG bit can be logically configured based on requirements).

[0048] ② Case where SA1 flips but SA2 does not flip:

[0049] Based on the basic reset, when SA1 flips, if AP1 input is low and AP2 input is high, then Z3 outputs high and Z4 outputs low. In this case, because the positive terminal of comparator Comp1 is connected to Z3 and the negative terminal to Z4, comparator Comp1 outputs high, causing node N1 to output low and Ctrl_1 to output high. At this time, the redundant circuit is working, and the control bit N1 of selector MUX1 outputs low, disabling comparator Comp and outputting the upper VH level, i.e., selector MUX1 outputs high. Therefore, the circuit is latched into the redundant inverting working mode. At this time, the output data is that Z3 output changes to low and Z4 output changes to high (which takes a certain amount of time). When the outputs of Z3 and Z4 conform to the standard logic (i.e., the default logic), because node N1 changes from the initial high level to low, due to the NOT4 gate (which can... By adding an odd number of cascaded inverters, the rising edge will be later than the high level time of node N1 (to ensure that SA1 redundancy adjustment is completed), and finally the output of node N3 will be low. At this time, selector MUX3 will undergo L→H operation. That is to say, when SA1 is compared, SA2 is first controlled not to perform redundancy adjustment operation. After SA1 adjustment is completed, SA2 comparison operation is performed. If SA2 is functioning normally, comparator Comp2 outputs low level and keeps the potential of node N2 high, so Ctrl_2 outputs low level, controlling SA2 redundancy not to work. SA2 works in the same direction region, so the output logic is normal at this time. Finally, FLAG outputs "1", indicating that SA1 or SA2 has flipped. During the read signal holding stage, when the FLAG output is stable (i.e., no high-low level transition occurs), it means that the SA1 and SA2 correction is over.

[0050] ③ SA1 does not flip, SA2 flips:

[0051] Similar to the previous analysis, after the reset, the REG input first goes low, so the output of node N4 goes high, releasing the input of comparator Comp1. If SA1 does not toggle, the output of comparator Comp1 goes low, so node N1 goes high, and Ctrl_1 goes low. The redundant part of SA1 does not work. Since node N1 is high, the flip-flop DFF resets, so node N3 goes high. Since both node N1 and node N3 are high, selector MUX3 enables the lower output, which is high, thus starting the SA2 comparison output. If SA2 toggle, it outputs high, so node N2 goes low, selector MUX2 switches to the upper output, outputting high, thus setting N... Node 2 is locked to low level, and Ctrl_2 output is high level, thus enabling the SA2 redundancy part to work. The circuit output polarity is reversed. That is, under normal circumstances, if AP1 input is low level (AP2 input is high level), then Z3 input is low level (Z4 input is high level), then Z1 output is low level (Z2 output is high level). If SA2 is reversed, then AP1 is low, Z3 is low, then Z1 is high (Z2 is low), which is opposite to the design logic. Therefore, when SA2 redundancy is enabled, a reversal will occur. So at this time, the output result is AP1 low, Z3 low, then Z1 low (Z2 is high), and FLAG output is 1, that is, SA1 or SA2 has been reversed.

[0052] ④ SA1 flip, SA2 flip situation:

[0053] First, a reset occurs. After the reset, comparator Comp1 of SA1 outputs. If SA1 has flipped, node N1 outputs a low level (changing from an initial high level to a low level). After a delay, the rising edge of node N1 is high, causing flip-flop DFF to output N3 = 0, and correspondingly Ctrl_1 becomes high. This activates the redundant circuitry of SA1, inverting SA1. Since node N3 is 0, selector MUX3 outputs a high level (upstream VH input). After delays from NOT gate NOT4 and flip-flop DFF, SA1 achieves a stable output. Then, SA2 performs redundant adjustment. If SA2 has also flipped, node N2 is low, and Ctrl_2 becomes high, activating the redundant circuitry of SA2. SA2 becomes inverted, and the final output, after two inversions, achieves normal logic output, with FLAG outputting 1, indicating that either SA1 or SA2 has flipped. Furthermore, this comparison function can be forcibly disabled via OUT_EN (a common industry practice with various methods).

[0054] After the above compensation, the SA section on the array read path can be corrected, which can improve the abnormal flipping of SA caused by various factors, reduce the probability of read errors on the output path, and improve product yield and reliability.

[0055] The core idea of ​​this invention is to correct abnormal switching of SA through redundant circuitry and a discrimination mechanism, ultimately ensuring that the SA section on the read path functions normally and will not reverse due to factors such as process or temperature. The above is a preferred embodiment of this invention. Various modifications can be made within the scope of this invention, such as defaulting to an inverted state for SA and changing the redundant adjustment to a unidirectional state, or modifying some logic in the two-stage digital discrimination mechanism, etc.

[0056] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A redundancy-resistant structure for an SRAM sensitive amplifier, characterized in that, include: Two identical sensitive amplifiers are used, with the two input terminals of the second-stage sensitive amplifier connected to the output terminals of the first-stage sensitive amplifier. Each sensitive amplifier includes a main amplification structure and a redundant circuit. The main amplification structure compares and amplifies the differential signals, while the redundant circuit is connected to the main amplification structure. A digital state machine is used to determine the operating state of the sensitive amplifier and output control signals to control whether the two redundant circuits are engaged, thus amplifying the differential signals in either the reverse or same direction. The sensitive amplifier includes PMOS transistors MP1~MP2 and NMOS transistors MN1~MN9. PMOS transistors MP1 and M... The gates of P2 are all connected to a low level GS, and the sources are all connected to a high level VS. The drains are connected to the drains of NMOS transistors MN5 and MN6, respectively. The drains of PMOS transistors MP1 and MP2 are connected to the sources and drains of PMOS transistor MP3, respectively. The gates of NMOS transistors MN5 and MN6 are connected to the positive input IP and the negative input IN, respectively, and their sources are connected to the drains of NMOS transistors MN3 and MN4, respectively. The sources of NMOS transistors MN5 and MN6 are connected to the sources and drains of PMOS transistor MP4, respectively. The gate of PMOS transistor MP3 is connected to the signal Equal, and the gate of PMOS transistor MP4 is connected to the signal AMP_Start. The drains of transistors MP1 and MP2 serve as the output terminals of the sensitive amplifier; the drain of NMOS transistor MN3 is simultaneously connected to the drain of NMOS transistor MN1 and the gate of NMOS transistor MN4; the drain of NMOS transistor MN4 is simultaneously connected to the drain of NMOS transistor MN2 and the gate of NMOS transistor MN3; the sources of NMOS transistors MN3 and MN4 are simultaneously connected to the drain of NMOS transistor MN8; the gate of NMOS transistor MN1 is connected to its own drain, and its source is connected to the drain of NMOS transistor MN7; the gate of NMOS transistor MN2 is connected to its own drain, and its source is connected to the drain of NMOS transistor MN9; the gates of NMOS transistors MN7 and MN9 are both connected to the signal... Re.Ctrl connects the gate of NMOS transistor MN8 to the signal AMP_Start; the sources of NMOS transistors MN7-MN9 are all connected to a low level GS; the gates of PMOS transistors MP1 and MP2 are connected to a low level to achieve resistive load characteristics; NMOS transistors MN5 and MN6 form two input differential pairs, with a cross-coupled structure formed by NMOS transistors MN3 and MN4 at the bottom, providing small-signal gain through positive feedback and faster output in the large-signal region; NMOS transistors MN1 and MN2 on both sides are redundant circuit structures, which are turned on by the signal Re.Ctrl to achieve the purpose of inverting the output logic.

2. The SRAM sensitive amplifier anti-flip redundancy structure as described in claim 1, characterized in that, The digital state machine includes comparators Comp1~Comp2, selectors MUX1~MUX3, AND gates AND1~AND2, NOT gates NOT1~NOT7, NAND gates NAND1~NAND3, NMOS transistors MN31~MN32, and D flip-flops. The two inputs of comparator Comp1 are connected to the outputs of the first-stage sensitive amplifier. The output of comparator Comp1 and the signal VH are both connected to the inputs of selector MUX1. The output of selector MUX1 is connected to one input of NAND gate NAND1. The drain of the OS transistor MN31 is connected to the input of NOT gate NOT1, the gate is connected to the output of NOT gate NOT1, and the source is connected to a low level. The output of NOT gate NOT1 is connected to the other input of NAND gate NAND1. The output of NAND gate NAND1 is simultaneously connected to the input of NOT gate NOT4, the output of NOT gate NOT2, the input of NOT gate NOT3, one input of NAND gate NAND3, and the D terminal of the D flip-flop. The output of NOT gate NOT4 is simultaneously connected to the CP and RST terminals of the D flip-flop. The two inputs of the second-stage sensitive amplifier are respectively connected to the... The output of the first-stage sensitive amplifier and the output of the second-stage sensitive amplifier are connected to the input of comparator Comp2. The output of comparator Comp2 and the signal VH are both connected to the input of selector MUX2. The output of selector MUX2 is connected to the first input of NAND gate NAND2. The two inputs of AND gate AND1 are connected to nodes N1 and N3. The output of AND gate AND1 and the signal VH are both connected to the input of selector MUX3. The output of selector MUX3 is connected to the second input of NAND gate NAND2. The three input terminals are connected to node N4; the output terminal of NAND gate NAND2, the other input terminal of NAND gate NAND3, the output terminal of NOT gate NOT5, and the input terminal of NOT gate NOT6 are all connected to node N2, and the output terminal of NOT gate NOT6 is connected to the input terminal of NOT gate NOT5; the output terminal of NAND gate NAND3 is connected to one input terminal of AND gate AND2; the drain of NMOS transistor MN32 is connected to the input terminal of NOT gate NOT7, the gate is connected to the output terminal of NOT gate NOT7, and the source is connected to a low level; the output terminal of NOT gate NOT7 is connected to the other input terminal of AND gate AND2.

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