Dual-edge triggered asynchronous gray code counter

Abstract

The application discloses a double-edge triggered asynchronous Gray code counter, wherein a first stage trigger Rise1 is used as a rising edge triggered D trigger, and the rest of the stage triggers Fall1, Fall2 and Fall3 are used as falling edge triggered D triggers. The application solves the problem that the utilization of clock frequency is not maximized due to the generation of the first stage flag signal in the existing Gray code counter.

Description

Technical Field

[0001] This invention belongs to the field of Gray code counting technology and relates to an asynchronous Gray code counter triggered by two double edges. Background Technology

[0002] In integrated circuit design, counters are frequently used as one of the most basic circuit modules. Compared to binary counters, Gray code counters differ by only one bit between two adjacent values, meaning that only one bit of the output level toggles with each count. Therefore, Gray code counters have a lower error rate, improving the system's noise immunity. This means that Gray code counters can operate at a faster speed with fewer errors. Furthermore, when operating in counting mode, the number of gate toggles for each output of a Gray code counter is far fewer than that of a binary counter. Therefore, using a Gray code counter instead of a binary counter can reduce system power consumption.

[0003] Chinese utility model patent CN108055034A discloses an asynchronous Gray code counter circuit, such as Figure 1 As shown, the circuit includes a flag signal generation circuit and a cascaded flip-flop circuit. The D flip-flops used in this circuit are all the same type; DFF1, DFF2, DFF3, DFF4, and DFF5 are all falling-edge triggered D flip-flops. The first-stage flip-flop circuit uses DFF1. The D terminal of DFF1 is connected to its own inverted output QB, and the clock signal Clock is connected to its input CLK. The signal output from the inverted output QB of DFF1 is the flag signal signal. Simultaneously, the signal signal is input to the CLK terminal of the second-stage flip-flop DFF2. The cascading method for each stage of DFF2, DFF3, DFF4, and DFF5 is the same: the inverted output QB of the current stage's D flip-flop is connected to its D terminal, and the output XB of the current stage's D flip-flop is connected to the CLK input of the next stage's D flip-flop. Each stage of the D flip-flop is connected to the reset signal RST via R... N The reset terminal, and the positive inverted outputs of each stage of the D flip-flops DFF2, DFF3, DFF4, and DFF5 serve as the number of bits Y(0), Y(1), Y(2), and Y(3) of the Gray code counter, respectively. However, Figure 1 An existing asynchronous Gray code counter circuit requires a first-stage D flip-flop to generate a flag signal, which means that the non-inverting output of the first-stage D flip-flop cannot be used as the number of bits in the Gray code counter. Therefore, the first-stage D flip-flop is wasted to some extent. It is also because of the generation of the first-stage flag signal that the utilization of the clock frequency is not maximized. Summary of the Invention

[0004] The purpose of this invention is to provide a double-edge triggered asynchronous Gray code counter, which solves the problem that the clock frequency utilization is not maximized due to the generation of the first-stage flag signal in existing Gray code counters.

[0005] The technical solution adopted in this invention is a dual-edge triggered asynchronous Gray code counter, in which the first-stage flip-flop Rise1 is used as a rising-edge triggered D flip-flop, and the remaining flip-flops Fall1, Fall2 and Fall3 are used as falling-edge triggered D flip-flops.

[0006] The invention is further characterized by:

[0007] The first-level flip-flop, Rise1, is used as a rising-edge triggered D flip-flop, while the remaining flip-flops, Fall1, Fall2, and Fall3, are used as falling-edge triggered D flip-flops.

[0008] Each stage of the D flip-flop is connected to R by the reset signal RST. N The reset terminal and the positive output terminals of each stage of the D flip-flop are respectively used as the number of bits Q(0), Q(1), Q(2), and Q(3) of the Gray code counter.

[0009] For the first-stage D flip-flop Rise1, the non-inverting output terminal Q(0) is triggered at the rising edge of the clock signal Clock, while the XB terminal is triggered at the falling edge of the clock signal Clock. That is, the flip-flop trigger point of the XB terminal is half a clock cycle earlier than the non-inverting output signal Q(0), and the frequency of the XB signal is the same as that of the signal Q(0).

[0010] For the second-stage D flip-flop Fall1, the XB signal output by Rise1 is input to the CLK terminal of the second-stage D flip-flop Fall1. The non-inverting output terminal Q(1) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall1, and the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall1. That is, the flip-flop trigger point of the XB terminal of the flip-flop Fall1 is one clock cycle earlier than the non-inverting output signal Q(1), and the frequency of the XB signal is the same as that of the signal Q(1). This makes the flip-flop trigger point of the non-inverting output terminal Q(1) of the flip-flop Fall1 lag behind the Q(0) by half a clock cycle, and the frequency of the Q(0) signal is twice the frequency of the signal Q(1).

[0011] For the third-stage D flip-flop Fall2, the XB signal output from Fall1 is input to the CLK terminal of the third-stage D flip-flop Fall2. The non-inverting output terminal Q(2) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall2, and the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall2. That is, the flip-flop trigger point of the XB terminal of the flip-flop Fall2 is 2 clock cycles ahead of the non-inverting output signal Q(2), and the frequency of the XB signal is the same as that of the signal Q(2). This makes the flip-flop trigger point of the non-inverting output terminal Q(2) of the flip-flop Fall2 lag behind Q(1) by one clock cycle, and the frequency of the Q(1) signal is twice the frequency of the Q(2) signal.

[0012] For the fourth-stage D flip-flop Fall3, the XB signal output from Fall2 is input to the CLK terminal of the fourth-stage D flip-flop Fall3. Since the fourth-stage D flip-flop Fall3 is triggered on the falling edge, the non-inverting output terminal Q(3) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall3, and the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall3. That is, the flip-flop trigger point of the XB terminal of the flip-flop Fall3 is 4 clock cycles ahead of the non-inverting output signal Q(3), and the frequency of the XB signal is the same as that of the signal Q(3). This causes the flip-flop trigger point of the non-inverting output terminal Q(3) of the flip-flop Fall3 to lag the Q(2) signal by 2 clock cycles, and the frequency of the Q(2) signal is twice the frequency of the signal Q(3).

[0013] The beneficial effects of this invention are as follows:

[0014] 1. with Figure 1 Compared to the existing asynchronous Gray code counter circuit shown, the asynchronous Gray code counter circuit provided by this invention has a dual-edge triggered design, where Rise1 is a rising edge triggered D flip-flop, and Fall1, Fall2, and Fall3 are all falling edge triggered D flip-flops.

[0015] 2. with Figure 1 Compared to existing asynchronous Gray code counter circuits, the dual-edge triggered asynchronous Gray code counter circuit provided by this invention does not require a separate circuit to generate a flag signal. Furthermore, since the positive output Q(0) of the first-stage D flip-flop can be used as the first bit of the Gray code counter, the first-stage flip-flop is not wasted. From an overall circuit construction perspective, because there is no flag signal generation circuit, the use of one D flip-flop is reduced, further reducing power consumption and area.

[0016] 3. with Figure 1Compared to the existing asynchronous Gray code counter circuits shown, the dual-edge triggered asynchronous Gray code counter circuit provided by this invention can maximize the utilization of clock frequency in terms of overall function. That is, when achieving the same number of Gray code counters, this invention only requires half the time of the existing asynchronous Gray code counters to complete Gray code counting. Attached Figure Description

[0017] Figure 1 Here is a circuit diagram of an existing asynchronous Gray code counter;

[0018] Figure 2 This is a circuit diagram of the asynchronous Gray code counter with double-edge triggering according to the present invention;

[0019] Figure 3 This is a basic circuit diagram of a D flip-flop.

[0020] Figure 4 Here is a timing diagram of an existing asynchronous Gray code counter;

[0021] Figure 5 This is a timing diagram of the asynchronous Gray code counter triggered by two double edges according to the present invention. Detailed Implementation

[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0023] against Figure 1 The existing asynchronous Gray code counter circuit shown has the problem that "it requires a first-stage D flip-flop to generate a flag signal, which means the non-inverting output of the first-stage D flip-flop cannot be used as the number of bits in the Gray code counter, thus causing a certain degree of waste in the first-stage D flip-flop. Furthermore, the generation of the first-stage flag signal prevents the clock frequency from being maximized." Therefore, this invention proposes the following... Figure 2 The double-edge triggered asynchronous Gray code counter structure shown is used to solve the above-mentioned problems.

[0024] This invention relates to a dual-edge triggered asynchronous Gray code counter, where Rise1 is a rising-edge triggered D flip-flop, and Fall1, Fall2, and Fall3 are all falling-edge triggered D flip-flops. The first stage uses a rising-edge D flip-flop, with the clock signal Clock connected to its CLK input. The remaining stages all use falling-edge D flip-flops, and each stage is cascaded in the same way: the inverted output QB of the current stage's D flip-flop is connected to its D input, and the output XB of the current stage's D flip-flop is connected to the CLK input of the next stage's D flip-flop. Each stage's D flip-flop is connected to the reset signal RST via R... NThe reset terminal and the positive output terminals of each stage of the D flip-flop are respectively used as the number of bits Q(0), Q(1), Q(2), and Q(3) of the Gray code counter.

[0025] The D flip-flop circuit used, such as Figure 3 As shown, the basic structure of a D flip-flop mainly consists of two series-connected latches with different control conditions, each composed of a tri-state gate. T1 and T4 are tri-state gates controlled by the inverted signal of the input signal Clock, while T2 and T3 are tri-state gates controlled by the input signal Clock. H1 and H2 are NOR gates. The D terminal serves as the input of tri-state gate T1. The outputs of tri-state gates T1 and T2 are connected and used as one input of NOR gate H1. The reset terminal R... N After passing through an inverter, it becomes the other input of NOR gate H1. The output signal of H1 is XB. XB is then used as the input of tri-state gates T2 and T3. The outputs of tri-state gates T3 and T4 are connected and used as one input of NOR gate H2. The reset terminal R... N After passing through an inverter, it becomes the other input of the NOR gate H2. The output signal of H2 becomes the input of the tri-state gate T4. After passing through two inverters, the output signal of H2 becomes the non-inverting output Q. After passing through one inverter, it becomes the inverting output QB. Figure 3 The image shows a rising-edge triggered D flip-flop. If the positions of tri-state gates T1 and T4 are interchanged with those of tri-state gates T2 and T3, it can be transformed into a falling-edge triggered D flip-flop.

[0026] The proposed asynchronous Gray code counter circuit with double-edge triggering in this invention, wherein the second stage and subsequent D flip-flops and their corresponding cascading methods are similar to... Figure 1 The cascading method shown is the same as that in an existing asynchronous Gray code counter circuit. The difference is that, firstly, there is no need to add a flag signal generation circuit; secondly, the first-stage D flip-flop uses a D flip-flop with the opposite triggering method to other D flip-flops.

[0027] Firstly, Figure 2 The dual-edge triggered asynchronous Gray code counter circuit shown does not require a separate circuit to generate the flag signal. Furthermore, since the positive output Q(0) of the first-stage D flip-flop can be used as the first bit of the Gray code counter, the first-stage flip-flop is not wasted. From the perspective of overall circuit construction, because there is no flag signal generation circuit, one D flip-flop is eliminated, further reducing power consumption and area.

[0028] Secondly, Figure 2The dual-edge triggered asynchronous Gray code counter circuit shown above achieves its effect precisely because the first-stage D flip-flop uses a D flip-flop with a triggering method opposite to other D flip-flops. This allows the flip-flop's XB terminal trigger point to advance by half a clock cycle before the positive output signal Q(0), and the frequency of the XB signal is the same as that of the Q(0) signal. Therefore, the output signal from the XB terminal of flip-flop Rise1 is used as the input to the CLK terminal of the next-stage D flip-flop, enabling its output to become Gray code. Functionally, the introduction of dual-edge triggering maximizes the utilization of clock frequency. That is, to achieve the same number of Gray code counter bits, this invention only requires half the time of existing asynchronous Gray code counters to complete Gray code counting.

[0029] It is important to note that the output terminal XB is an output terminal drawn from the circuit of the D flip-flop. The D terminal serves as the input terminal of the tri-state gate T1. The output terminals of tri-state gates T1 and T2 are connected and serve as one input of the NOR gate H1. The reset terminal R... N After passing through an inverter, it becomes another input to the NOR gate H1, and the output signal of H1 is the output terminal XB.

[0030] The working principle of the asynchronous Gray code counter with dual edge triggering of the present invention is as follows: For the first stage D flip-flop Rise1, the positive output terminal Q(0) is triggered at the rising edge of the clock signal Clock, while its XB terminal is triggered at the falling edge of the clock signal Clock. That is, the flip trigger point of the XB terminal is half a clock cycle earlier than the positive output signal Q(0), and the frequency of the XB signal is the same as that of the signal Q(0). For the second-stage D flip-flop Fall1, the XB signal output by Rise1 is input to the CLK terminal of the second-stage D flip-flop Fall1. Since the second-stage D flip-flop Fall1 is triggered by the falling edge, the non-inverting output terminal Q(1) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall1, while its XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall1. That is, the flip-flop trigger point of the XB terminal of the flip-flop Fall1 is one clock cycle earlier than the non-inverting output signal Q(1), and the frequency of the XB signal is the same as that of the signal Q(1). This causes the flip-flop trigger point of the non-inverting output terminal Q(1) of the flip-flop Fall1 to lag behind the Q(0) by half a clock cycle, and the frequency of the Q(0) signal is twice the frequency of the signal Q(1). For the third-stage D flip-flop Fall2, the XB signal output from Fall1 is input to the CLK terminal of the third-stage D flip-flop Fall2. Since the third-stage D flip-flop Fall2 is triggered by the falling edge, the non-inverting output terminal Q(2) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall2, while its XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall2. That is, the flip-flop trigger point of the XB terminal of the flip-flop Fall2 is two clock cycles ahead of the non-inverting output signal Q(2), and the frequency of the XB signal is the same as that of the signal Q(2). This causes the flip-flop trigger point of the non-inverting output terminal Q(2) of the flip-flop Fall2 to lag behind Q(1) by one clock cycle, and the frequency of the Q(1) signal is twice the frequency of the signal Q(2). For the fourth-stage D flip-flop Fall3, the XB signal output from Fall2 is input to the CLK terminal of the fourth-stage D flip-flop Fall3. Since the fourth-stage D flip-flop Fall3 is triggered on the falling edge, the non-inverting output terminal Q(3) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall3, while its XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall3. That is, the flip-flop trigger point of the XB terminal of the flip-flop Fall3 is 4 clock cycles ahead of the non-inverting output signal Q(3), and the frequency of the XB signal is the same as that of the signal Q(3). This causes the flip-flop trigger point of the non-inverting output terminal Q(3) of the flip-flop Fall3 to lag the Q(2) signal by 2 clock cycles, and the frequency of the Q(2) signal is twice the frequency of the Q(3) signal. In summary, Q(0), Q(1), Q(2), and Q(3) form a 4-bit Gray code counter.

[0031] Figure 4 for Figure 1 The figure shown is a timing diagram of an existing asynchronous Gray code counter. Figure 5 This is a timing diagram of the double-edge triggered asynchronous Gray code counter of the present invention. Figure 4 , Figure 5 It can be seen that both can implement Gray code counting, but the difference lies in how they implement a 4-bit Gray code counter. Figure 5 The time consumed was only Figure 4 It achieves half of the goal, maximizing the use of clock frequency.

[0032] The advantages of the dual-edge triggered asynchronous Gray code counter of this invention are: 1. From the perspective of overall circuit construction, since there is no flag signal generation circuit, the use of a D flip-flop is reduced, which can further reduce power consumption and area; 2. From the perspective of overall function, the introduction of dual-edge triggering can maximize the use of clock frequency. That is, in the case of Gray code counters with the same number of bits, this invention can complete Gray code counting in only half the time of existing asynchronous Gray code counters.

Claims

1. A double-edge triggered asynchronous Gray code counter, characterized in that: The first-level flip-flop Rise1 is used as a rising-edge triggered D flip-flop, and the remaining flip-flops Fall1, Fall2, and Fall3 are used as falling-edge triggered D flip-flops. The first stage flip-flop Rise1 uses a rising edge D flip-flop, and the working clock signal Clock is connected to the CLK input of the rising edge D flip-flop. The remaining stages all use falling edge D flip-flops, and the cascading method of each stage is the same. The inverted output QB of the D flip-flop is connected to the D terminal of the current stage D flip-flop, and the output XB of the current stage D flip-flop is connected to the CLK input of the next stage D flip-flop. Each stage of the D flip-flop is connected to R by a reset signal RST. N The reset terminal and the positive output terminals of each stage of the D flip-flop serve as the number of bits Q(0), Q(1), Q(2), and Q(3) of the Gray code counter, respectively. The frequency of the XB signal at the output terminal of each stage of the D flip-flop is the same as that at the output terminal Q, and is one-quarter of a cycle ahead.

2. The double-edge triggered asynchronous Gray code counter according to claim 1, characterized in that: For the first-stage D flip-flop Rise1, the non-inverting output terminal Q(0) is triggered at the rising edge of the clock signal Clock, while the XB terminal is triggered at the falling edge of the clock signal Clock. That is, the flip-flop trigger point of the XB terminal is half a clock cycle earlier than the non-inverting output signal Q(0), and the frequency of the XB signal is the same as that of the signal Q(0).

3. The double-edge triggered asynchronous Gray code counter according to claim 2, characterized in that: For the second-stage D flip-flop Fall1, the XB signal output by Rise1 is input to the CLK terminal of the second-stage D flip-flop Fall1. The non-inverting output terminal Q(1) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall1, and the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall1. That is, the flip-flop trigger point of the XB terminal of the flip-flop Fall1 is one clock cycle earlier than the non-inverting output signal Q(1), and the frequency of the XB signal is the same as that of the signal Q(1). This makes the flip-flop trigger point of the non-inverting output terminal Q(1) of the flip-flop Fall1 lag behind the Q(0) by half a clock cycle, and the frequency of the Q(0) signal is twice the frequency of the signal Q(1).

4. The double-edge triggered asynchronous Gray code counter according to claim 3, characterized in that: For the third-stage D flip-flop Fall2, the XB signal output from Fall1 is input to the CLK terminal of the third-stage D flip-flop Fall2. The non-inverting output terminal Q(2) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall2, and the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall2. That is, the flip-flop trigger point of the XB terminal of the flip-flop Fall2 is 2 clock cycles ahead of the non-inverting output signal Q(2), and the frequency of the XB signal is the same as that of the signal Q(2). This makes the flip-flop trigger point of the non-inverting output terminal Q(2) of the flip-flop Fall2 lag behind Q(1) by one clock cycle, and the frequency of the Q(1) signal is twice the frequency of the Q(2) signal.

5. The double-edge triggered asynchronous Gray code counter according to claim 4, characterized in that: For the fourth-stage D flip-flop Fall3, the XB signal output from Fall2 is input to the CLK terminal of the fourth-stage D flip-flop Fall3. Since the fourth-stage D flip-flop Fall3 is triggered on the falling edge, the non-inverting output terminal Q(3) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall3, and the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall3. That is, the flip-flop trigger point of the XB terminal of the flip-flop Fall3 is 4 clock cycles ahead of the non-inverting output signal Q(3), and the frequency of the XB signal is the same as that of the signal Q(3). This makes the flip-flop trigger point of the non-inverting output terminal Q(3) of the flip-flop Fall3 lag behind the Q(2) signal by 2 clock cycles, and the frequency of the Q(2) signal is twice the frequency of the Q(3) signal.

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