Message encryption method and apparatus

Abstract

The application discloses a message encryption method and device, and relates to the technical field of data encryption. The message encryption method comprises the following steps of: in a previous clock cycle of processing adjacent first and second message words, a first hash module calculates a first e value and a first a value according to the first message word, a hash register value and a hash constant; a second hash module calculates a second e value and a second a value according to the second message word, the hash register value, the first e value, the first a value and the hash constant; and the second a value, the first a value, the second e value and the first e value are sequentially cached into a third hash register, a fourth hash register, a seventh hash register and an eighth hash register of a hash register group. Two hash modules are adopted to process two message words in the same clock cycle, the clock cycle used for calculating the message word digest value in the message encryption process is reduced, and therefore the user experience can be obviously improved.

Description

Technical Field

[0001] This invention relates to the field of data encryption technology, and in particular to a message encryption method and apparatus. Background Technology

[0002] In recent years, with the popularization and widespread application of the Internet, encryption technology has become an important tool for ensuring the privacy of data transmission. To this end, the National Institute of Standards and Technology (NIST) and the National Security Agency (NSA) have successively published a series of Secure Hash Algorithms (SHA).

[0003] Among them, the SHA-256 algorithm is widely used due to its high security. The SHA-256 algorithm generates a 256-bit message digest after encrypting the input message. The first step of the encryption calculation is to pad the input message to form a message with a length that is a multiple of 512 bits. The second step is to decompose this message into n 512-bit message blocks. The third step is to split the first message block into 16 original 32-bit message words and calculate the 256-bit digest value of the first message block according to the hash calculation rules and known hash constants. The fourth step is to split the second message block into 16 original 32-bit message words and calculate another 256-bit digest value according to the hash calculation rules and the digest value calculated in the previous step. This process is repeated for the remaining message blocks in sequence until the last message block is calculated. The resulting 256-bit digest value is the message digest of the input message.

[0004] In calculating the digest value for each message block, the first step is to split the message block. The 16 original message words resulting from this splitting are ordered from least significant bit to most significant bit as follows: W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W 10 W 11 W 12 W 13 W 14 W 15 The second step is to iterate these 16 original message words 48 times according to the following message word construction formula (Formula 1) to generate 48 constructed message words. Adding the original 16 original message words, there are a total of 64 message words.

[0005] Formula 1: W t =σ1(W t-2 )+W t-7 +σ0(W t-15 )+W t-16 Where, σ0(x)=S 7 (x)⊕S 18(x)⊕R 3 (x); σ1(x)=S 17 (x)⊕S 19 (x)⊕R 10 (x); S n It is a circular right shift of n bits, R n It means right shift by n bits, and "⊕" means bitwise XOR.

[0006] The third step is to calculate the digest value of the first message word using the known eight 32-bit initial hash values ​​and the digest value calculation formula (Formula 2) (t = 1, indicating that the first message word is being calculated). This digest value is also represented by eight 32-bit values. The eight initial hash values ​​are: a0, b0, c0, d0, e0, f0, g0, h0, and the generated digest values ​​are: a1, b1, c1, d1, e1, f1, g1, h1.

[0007] Formula 2: T1 = h t-1 +Σ1(e t-1 )+Ch(e t-1 ,f t-1 ,g t-1 )+K t-1 +W t-1 ;

[0008] T2=Σ0(a t-1 )+Maj(a t-1 ,b t-1 ,c t-1 );

[0009] a t =T1+T2;

[0010] b t =a t-1 ;

[0011] c t =b t-1 ;

[0012] d t =c t-1 ;

[0013] e t =d t-1 +T1;

[0014] f t =e t-1 ;

[0015] g t =f t-1 ;

[0016] h t=g t-1 .

[0017] In Formula 2, “∧” means bitwise AND; It is to find the "complement"; Ma(x,y,z)=(x∧y)⊕(x∧z)⊕(y∧z), where "⊕" is the bitwise "exclusive OR".

[0018] Figure 1 This is a schematic diagram of the existing formula for calculating message digest values, combined with Formula 2 and... Figure 1 It can be seen that a hash register set is used when calculating the digest value of each message word, which includes eight hash registers: hash register A, hash register B, hash register C, hash register D, hash register E, hash register F, hash register G, and hash register H. Before calculating the first message word W0, the hash register set stores the above eight initial hash values: a0 in hash register A, b0 in hash register B, c0 in hash register C, d0 in hash register D, e0 in hash register E, f0 in hash register F, g0 in hash register G, and h0 in hash register H.

[0019] Figure 1 The plus sign in the hash table represents adding two numbers together. If the result is greater than 2^32, it must be divided by 2^32 and the remainder must be found. When calculating the first message word W0, t=1. The generated b1, c1, and d1 do not need to be calculated, as they are obtained by shifting a0, b0, and c0 to the right. The generated f1, g1, and h1 also do not need to be calculated, as they are obtained by shifting e0, f0, and g0 to the right. Only e1 and a1 need to be calculated. Moreover, the calculation uses not only the initial hash values ​​a0~h0 and the first message word W0, but also the hash constant K0.

[0020] According to this calculation rule, the subsequent steps involve calculating the (t+1)th message word W. t When calculating the digest value, it is necessary to use not only the hash constant K. t It also requires using the message word W t-1 The calculated summary value a t ~h t Until the last message word W 63 After the calculation is completed, the resulting digest value is added to the digest value calculated for the previous message block to obtain the digest value for this message block.

[0021] Existing hardware circuits implementing the message digest value calculation step in the SHA-256 algorithm typically calculate one message word at a time, using a shift register to shift the previously calculated a, b, c, e, f, g bits backward, generating new b, c, d, f, g, h bits, with new a and e bits obtained through calculation. If calculating one message word takes one clock cycle, then calculating the digest value of 64 message words would require 64 clock cycles. Since there are additional steps between the message block digest value calculations—adding the digest values ​​and storing the results in the hash register group for calculating the next message block digest value—each consumes one clock cycle. Therefore, completing the message digest calculation for n message blocks would take (64+2)*n clock cycles, which is very time-consuming. When users use such hardware circuits to encrypt long input messages (where n is large), they would have to wait a considerable amount of time, impacting the user experience. Summary of the Invention

[0022] This invention provides a message encryption method and apparatus to overcome the technical problems existing in the prior art, reduce the clock cycles consumed in the message digest value calculation process, and improve the user experience.

[0023] The present invention provides a message encryption method, characterized in that, in the clock cycle preceding the processing of adjacent first and second message words, the method includes: a first hash module calculating a first e value and a first a value based on the first message word, a hash register value, and a hash constant; a second hash module calculating a second e value and a second a value based on the second message word, the hash register value, the first e value, the first a value, and the hash constant; and sequentially caching the second a value, the first a value, the second e value, and the first e value to the third, fourth, seventh, and eighth hash registers of the hash register group.

[0024] Further, in the subsequent clock cycle after processing the third and fourth message words that follow the second message word, the process includes: the first hash module calculating the third e value and the third a value based on the third message word, the hash register value, and the hash constant; the second hash module calculating the fourth e value and the fourth a value based on the fourth message word, the hash register value, the third e value, the third a value, and the hash constant; and sequentially caching the fourth a value, the third a value, the fourth e value, and the third e value to the first hash register, the second hash register, the fifth hash register, and the sixth hash register of the hash register group.

[0025] Furthermore, the preceding clock cycle and the following clock cycle are cycled sequentially until all message words in the message block have been processed.

[0026] Further, in the clock cycle preceding the processing of adjacent fourth-to-last and third-to-last message words, the process includes: the first hash module calculating the fourth-to-last e value, the fourth-to-last a value, the first digest e value, and the first digest a value based on the fourth-to-last message word, the hash register value, the hash constant, and the digest register value; the second hash module calculating the third-to-last e value, the third-to-last a value, the second digest e value, and the second digest a value based on the third-to-last message word, the hash register value, the fourth-to-last e value, the fourth-to-last a value, the hash constant, and the digest register value; sequentially caching the third a value, the fourth-to-last a value, the third-to-last e value, and the fourth-to-last e value to the third hash register, fourth hash register, seventh hash register, and eighth hash register of the hash register group; and sequentially caching the second digest a value, the first digest a value, the second digest e value, and the first digest e value to the third digest register, fourth digest register, seventh digest register, and eighth digest register of the digest register group.

[0027] In the clock cycle following the processing of the penultimate message word and the adjacent penultimate and penultimate message words, the process includes: the first hash module calculating the penultimate e value, the penultimate a value, the third digest e value, and the third digest a value based on the penultimate message word, the hash register value, the hash constant, and the digest register value; and the second hash module calculating the fourth digest e value and the fourth digest a value based on the penultimate message word, the hash register value, the penultimate e value, the penultimate a value, the hash constant, and the digest register value.

[0028] The fourth digest a value, the third digest a value, the fourth digest e value, and the third digest e value are sequentially cached to the first digest register, the second digest register, the fifth digest register, and the sixth digest register of the digest register group;

[0029] When the encryption mode is single hash or double hash, and in the first round of hash calculation, during the last clock cycle of processing each message block except the last message block, the fourth digest a value, the third digest a value, the fourth digest e value, and the third digest e value are sequentially cached to the first hash register, the second hash register, the fifth hash register, and the sixth hash register of the hash register group; the digest register values ​​in the third digest register, the fourth digest register, the seventh digest register, and the eighth digest register of the digest register group are sequentially cached to the third hash register, the fourth hash register, the seventh hash register, and the eighth hash register of the hash register group; when the encryption mode is double hash, and the clock cycle after processing the second-to-last message word and the last message word is the last clock cycle of the first round of hash calculation in the double hash, the initial hash value is stored in the hash register group.

[0030] Furthermore, when the message word register group is not full, the message encryption method further includes: when the encryption mode is single hash, or when the encryption mode is double hash and during the first round of hash calculation in the double hash, the message word buffer register group outputs a supplementary message word to the message word register group.

[0031] Optionally, when the message word buffer register group is not full, the message encryption method further includes: the message word buffer register group receiving a candidate message word input from the digest register group.

[0032] Optionally, when the message word register group is full, the message encryption method further includes: the first hash module calculating the Nth constructed message word based on the original message word; the second hash module calculating the (N+1)th constructed message word based on the original message word; and sequentially caching the Nth constructed message word and the (N+1)th constructed message word to the Mth message word register and the (M+1)th message register of the message word register group, where M = N % the number of message word registers. When the encryption mode is single hash, or when the encryption mode is double hash and the first round of hash calculation in the double hash is performed, the original message word comes from the message word register group; when the encryption mode is double hash and the second round of hash calculation in the double hash is performed, the original message word comes from the digest register group and the constant message word.

[0033] The present invention provides a message encryption device, comprising: a hash register group, a message word register group, a first hash module, and a second hash module; the hash register group is used to cache hash register values; the message word register group is used to cache message words;

[0034] The first hash module includes a first 4-2 compressor, a first 5-2 compressor, a second 4-2 compressor, a first 3-2 compressor, and a first carry-lookahead adder connected in sequence, and a second 5-2 compressor, a third 4-2 compressor, a fourth 3-2 compressor, and a fourth carry-lookahead adder connected in sequence. The output of the first 5-2 compressor is connected to the input of the second 5-2 compressor. The hash register value is input to the first 5-2 compressor, the second 4-2 compressor, and the second 5-2 compressor. The message word is input to either the first 4-2 compressor or the first 5-2 compressor.

[0035] The second hash module includes a fourth 4-2 compressor, a third 5-2 compressor, a fifth 4-2 compressor, a sixth 3-2 compressor, and a sixth carry-lookahead adder connected in sequence. The fourth 5-2 compressor, the sixth 4-2 compressor, the ninth 3-2 compressor, and the ninth carry-lookahead adder are also connected in sequence. The output of the third 5-2 compressor is connected to the input of the fourth 5-2 compressor. The hash register value is input to the third 5-2 compressor, the fifth 4-2 compressor, and the fourth 5-2 compressor. The output of the first carry-lookahead adder is connected to the third 5-2 compressor, the output of the fourth carry-lookahead adder is connected to the fourth 5-2 compressor, and the message word is input to either the fourth 4-2 compressor or the third 5-2 compressor.

[0036] The outputs of the first carry-lookahead adder, the fourth carry-lookahead adder, the sixth carry-lookahead adder, and the ninth carry-lookahead adder are connected to the hash register group.

[0037] Furthermore, the message encryption device also includes a control module for controlling the input and output of the first hash module and the second hash module until all message words in the message block have been processed.

[0038] Furthermore, the message encryption device also includes a digest register group, which is used to cache digest register values;

[0039] The first hash module includes a second 3-2 compressor and a second carry-lookahead adder connected in sequence, and a fifth 3-2 compressor and a fifth carry-lookahead adder connected in sequence; the output of the first 3-2 compressor is connected to the input of the second 3-2 compressor, and the output of the fourth 3-2 compressor is connected to the input of the fifth 3-2 compressor;

[0040] The second hash module includes a seventh 3-2 compressor and a seventh carry-lookahead adder connected in sequence, and a 10th 3-2 compressor and a 10th carry-lookahead adder connected in sequence; the output of the sixth 3-2 compressor is connected to the input of the seventh 3-2 compressor, and the output of the ninth 3-2 compressor is connected to the input of the 10th 3-2 compressor;

[0041] The digest register value is input to the second 3-2 compressor, the fifth 3-2 compressor, the seventh 3-2 compressor, and the tenth 3-2 compressor; the outputs of the second carry-lookahead adder, the fifth carry-lookahead adder, the seventh carry-lookahead adder, and the tenth carry-lookahead adder are connected to the digest register group; when the encryption mode is single hash and it is the last clock cycle of message block processing, the control module is used to connect the outputs of the second carry-lookahead adder, the fifth carry-lookahead adder, the seventh carry-lookahead adder, and the tenth carry-lookahead adder to the hash register group, and input the digest register value into the hash register group; when the encryption mode is double hash and it is the first round of hash calculation in the double hash, the control module is used to input the initial hash value into the hash register group.

[0042] Furthermore, the message encryption device also includes a padding module, and the message word buffer register group includes a first buffer register queue and a second buffer register queue; the output of the padding module is connected to the message word buffer register group, and the output of the message word buffer register group is connected to the message word register group; when the encryption mode is single hash, or when the encryption mode is double hash and the first round of hash calculation is performed in the double hash, the control module is used to cause the message word buffer register group to output supplementary message words to the message word register group.

[0043] Furthermore, the first hash module further includes a third 3-2 compressor and a third carry-lookahead adder connected in sequence, with the output of the first 4-2 compressor connected to the third 3-2 compressor; the second hash module further includes an eighth 3-2 compressor and an eighth carry-lookahead adder connected in sequence, with the output of the fourth 4-2 compressor connected to the eighth 3-2 compressor; the outputs of the third carry-lookahead adder and the eighth carry-lookahead adder are connected to the message word register group.

[0044] The message encryption method and apparatus provided by this invention employs two hash modules that operate simultaneously within the same clock cycle. The two hash modules calculate the digest value of two adjacent message words respectively, thus realizing the processing of two message words in one clock cycle. Compared with the existing case where only one message word is processed in one clock cycle, this reduces the clock cycle used for message word digest value calculation during message encryption, thereby significantly improving the user experience. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A schematic diagram illustrating the formula for calculating message digest values ​​using existing technology;

[0047] Figure 2 A flowchart of a message encryption method provided in an embodiment of the present invention;

[0048] Figure 3 A flowchart of another message encryption method provided in an embodiment of the present invention;

[0049] Figure 4 A flowchart of a digest register group update method provided in an embodiment of the present invention;

[0050] Figure 5 A block diagram of a message encryption device provided in an embodiment of the present invention;

[0051] Figure 6 for Figure 5 A block diagram of the first hash module in the message encryption device shown;

[0052] Figure 7 for Figure 5 A block diagram of the second hash module in the message encryption device shown;

[0053] Figure 8 A block diagram of another message encryption device provided in an embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0055] To make the technical solution of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0056] Figure 2A flowchart of a message encryption method provided in an embodiment of the present invention is shown below. Figure 2 As shown, the method performs the following steps within a timeframe called the preceding clock cycle to process adjacent first and second message words. These two adjacent message words can be either the first 16 message words constituting a message block, or construct words generated from the first 16 message words.

[0057] Step 201: The first hash module calculates the first e value and the first a value based on the first message word, the hash register value, and the hash constant.

[0058] Specifically, the message encryption device includes a first hash module and a second hash module. The two hash modules have identical structures and can operate simultaneously. The first hash module calculates the digest value of the first message word, and the second hash module calculates the digest value of the second message word. According to existing digest value calculation formulas, of the eight digest values ​​(a to h) generated from a message word, only a and e need to be calculated; the remaining digest values ​​are obtained through shifting, i.e., the initial a value is... t-1 b t-1 c t-1 As calculated b t c t d t e before calculation t-1 f t-1 g t-1 As calculated f t g t h t Therefore, the first hash module only needs to calculate two digest values, a and e, to obtain the first e value and the first a value.

[0059] According to the formula for calculating e:

[0060] e t =d t-1 +T1, T1=h t-1 +Σ1(e t-1 )+Ch(e t-1 ,f t-1 ,g t-1 )+K t-1 +W t-1 Taking t=1 as an example, we can

[0061] The calculation process requires the values ​​d0, e0, f0, g0, and h0 from before the calculation. These values ​​are stored in the five hash registers D, E, F, G, and H in the hash register group as hash register values, as shown in Table 1. K0 and W0 are also used. K0 is a hash constant, with a total of 64 values, each corresponding to one of the 64 different message words. W0 is the first message word to be calculated.

[0062] Table 1

[0063] A B C D E F G H <![CDATA[a0]]> <![CDATA[b0]]> <![CDATA[c0]]> <![CDATA[d0]]> <![CDATA[e0]]> <![CDATA[f0]]> <![CDATA[g0]]> <![CDATA[h0]]>

[0064] According to the formula for calculating a: a t =T1+T2,T2=Σ0(a t-1 )+Maj(a t-1 ,b t-1 ,c t-1 When t=1, it can be seen that the calculation process requires the values ​​a0, b0, c0, d0, e0, f0, g0, and h0 from before the calculation. These values ​​are stored in the eight registers of the hash register group A to H as hash register values, as shown in Table 1. K0 and W0 are also used, with W0 being the first message word to be calculated.

[0065] Step 202: The second hash module calculates the second e value and the second a value based on the second message word, the hash register value, the first e value, the first a value, and the hash constant.

[0066] The second hash module is used to calculate the digest value of the second message word. According to the calculation formula of e, when t=2, the calculation process requires the values ​​d1, e1, f1, g1, and h1 before the calculation, which are the digest values ​​of the first message word after the calculation. Here, d1 uses c0 in the C register, e1 uses the first e value, f1 uses e0 in the E register, g1 uses f0 in the F register, and h1 uses g0 in the G register. K1 and W1 are also used; K1 is a hash constant, and W1 is the second message word.

[0067] According to the formula for calculating 'a', when t=2, the calculation process requires the values ​​a1, b1, c1, d1, e1, f1, g1, and h1 from before the calculation, which are the digest values ​​of the first message word after the calculation. Here, a1 uses the first 'a' value, b1 uses a0 from register A, and c1 uses b0 from register B. The second 'a' value and the second 'e' value are then obtained through calculation.

[0068] Step 203: Cache the second a value, the first a value, the second e value, and the first e value sequentially to the third hash register, the fourth hash register, the seventh hash register, and the eighth hash register of the hash register group.

[0069] Here, the names of the eight registers A through H are assigned sequentially as First Hash Register, Second Hash Register, Third Hash Register, Fourth Hash Register, Fifth Hash Register, Sixth Hash Register, Seventh Hash Register, and Eighth Hash Register, forming a hash register group, as shown in Table 2, which illustrates the corresponding relationship.

[0070] Table 2

[0071]

[0072] Based on the analysis of steps 201 and 202 above, the hash register values ​​of the eight registers A through H were used when calculating the first message digest value to obtain the first a value and the first e value. When calculating the second message digest value, the a value and the e value used the first a value and the first e value, respectively. The remaining hash register values ​​used came from registers A, B, C, E, F, and G. It can be seen that registers D and H were not used, that is, the fourth hash register and the eighth hash register were not used.

[0073] Based on the hash register values ​​in registers A through H used in the above digest value calculation process, it can be inferred that when processing the next message word following the second message word, in addition to using the calculated first a value, second a value, first e value, and second e value, the remaining hash register values ​​used come from registers A, B, E, and F, respectively. It can be seen that, apart from the previously unused registers D and H, registers C and G are also unused, that is, the third hash register and the seventh hash register are unused.

[0074] Therefore, the second 'a' value, the first 'a' value, the second 'e' value, and the first 'e' value can be cached sequentially in the third, fourth, seventh, and eighth hash registers of the hash register group, as shown in Table 3. This arrangement not only makes full use of storage space and avoids waste, but also avoids the use of shift registers in existing technologies, preventing the need to shift and update the values ​​of all hash registers in the hash register group after each message digest value is calculated. This saves one shift clock cycle and also saves the power consumed during the shift process.

[0075] Table 3

[0076]

[0077] In the message encryption method provided by this invention, since two hash modules work simultaneously in the same clock cycle, the two hash modules calculate the digest value of two adjacent message words respectively, realizing the processing of two message words in one clock cycle. Compared with the existing case of processing only one message word in one clock cycle, the clock cycle used for message word digest value calculation during message encryption is reduced, thereby significantly improving the user experience.

[0078] Figure 3 A flowchart of another message encryption method provided in an embodiment of the present invention. Figure 3The method shown includes not only the message encryption method within the previous clock cycle described in the above embodiments ( Figure 3 (As shown in steps 301-303), it also includes the message encryption method to be executed in the subsequent clock cycle. The subsequent clock cycle is performed after the completion of the preceding clock cycle. In this subsequent clock cycle, the processing of adjacent third and fourth message words continues to calculate their digest values, wherein the third message word follows the second message word, and the fourth message word follows the third message word. The steps executed in the subsequent clock cycle are as follows.

[0079] Step 304: The first hash module calculates the third e value and the third a value based on the third message word, the hash register value, and the hash constant.

[0080] The first hash module is used to calculate the digest value of the third message word. According to the calculation formula of e, when t=3, the calculation process requires the values ​​d2, e2, f2, g2, and h2 before the calculation, which are the digest values ​​of the calculated second message word, already stored in the hash register group. Referring to Table 3, d2 uses b0 in register B, e2 uses the second e value in register G, f2 uses the first e value in register H, g2 uses e0 in register E, and h2 uses f0 in register F. K2 and W2 are also used, where K2 is a hash constant and W2 is the third message word.

[0081] According to the formula for calculating 'a', when t=3, the calculation process requires the values ​​a2, b2, c2, d2, e2, f2, g2, and h2 from before the calculation. These are the digest values ​​of the second message word after calculation, which are already stored in the hash register group. Referring to Table 3, a2 uses the second 'a' value from register C, b2 uses the first 'a' value from register D, and c2 uses a0 from register A. The third 'a' value and the third 'e' value are then obtained through calculation.

[0082] Step 305: The second hash module calculates the fourth e value and the fourth a value based on the fourth message word, the hash register value, the third e value, the third a value, and the hash constant.

[0083] The second hash module is used to calculate the digest value of the fourth message word. According to the formula for calculating e, when t=4, the calculation process requires the use of d3, e3, f3, g3, and h3 before the calculation, which are the digest values ​​of the third message word after the calculation. Here, d3 uses a0 in register A, e3 uses the third e value, f3 uses the second e value in register G, g3 uses the first e value in register H, and h3 uses e0 in register E. K3 and W3 are also used; K3 is a hash constant, and W3 is the fourth message word.

[0084] According to the formula for calculating 'a', the calculation process requires the values ​​a3, b3, c3, d3, e3, f3, g3, and h3 from before the calculation, which are the digest values ​​of the third message word after the calculation. Here, a3 uses the third 'a' value, b3 uses the second 'a' value from the C register, and c3 uses the first 'a' value from the D register. The fourth 'a' value and the fourth 'e' value are then obtained through calculation.

[0085] Step 306: Cache the fourth a value, the third a value, the fourth e value, and the third e value sequentially to the first hash register, the second hash register, the fifth hash register, and the sixth hash register of the hash register group.

[0086] Based on the analysis in steps 304 and 305 above, the hash register values ​​from registers A through H were used in the calculation of the third message digest value to obtain the third a value and the third e value. In the calculation of the fourth message digest value, the a and e values ​​used the third a value and the third e value, respectively. The remaining hash register values ​​used came from registers A, C, D, E, G, and H. It can be seen that registers B and F were not used, that is, the second hash register and the sixth hash register were not used.

[0087] Based on the hash register values ​​in registers A through H used in the above digest value calculation process, it can be inferred that when processing the next message word following the fourth message word, in addition to using the calculated third a value, fourth a value, third e value, and fourth e value, the remaining hash register values ​​used come from registers C, D, G, and H respectively. Apart from the previously unused D and H registers, registers A and E are also unused, that is, the first hash register and the fifth hash register are unused.

[0088] Therefore, the fourth 'a' value, the third 'a' value, the fourth 'e' value, and the third 'e' value can be cached sequentially in the first hash register, the second hash register, the fifth hash register, and the sixth hash register of the hash register group, as shown in Table 4. This arrangement not only makes full use of storage space and avoids waste, but also avoids the use of shift registers in existing technologies, preventing the need to shift and update the values ​​of all hash registers in the hash register group after each message digest value is calculated. This saves one shift clock cycle and also saves the power consumed during the shift process.

[0089] Table 4

[0090]

[0091] Step 307: Determine if there are any unprocessed message words in the message block. If the result is yes, return to step 301.

[0092] Specifically, the message to be encrypted, after padding and decomposition, forms several 512-bit message blocks. Each message block is further divided into 16 32-bit original message words. Based on these 16 original message words, 64 message words can be generated. In other words, calculating the digest value of a message block involves calculating the digest value of each of the 64 message words. As mentioned above, executing steps 301 to 306 performs digest calculations for four message words, generating eight hash register values ​​and updating all hash registers in the hash register group. While these 64 message words are not processed, steps 301 to 306 are repeatedly executed until all 64 message words in the message block have been processed.

[0093] In the message encryption method provided in the above embodiments, since two hash modules work simultaneously in the same clock cycle, the two hash modules calculate the digest value of two adjacent message words respectively, realizing the processing of two message words in one clock cycle. Compared with the existing case of processing only one message word in one clock cycle, the clock cycle used for message word digest value calculation during message encryption is reduced, thereby significantly improving the user experience.

[0094] When calculating the digest values ​​of the last four message words in the message block sequentially using steps 301 to 306 above, that is, when processing the adjacent fourth-to-last message word, third-to-last message word, second-to-last message word, and last message word, in addition to calculating the new 'a' and 'e', ​​the message block digest value will also be calculated and updated based on the digest register values ​​of the eight digest registers in the digest register group.

[0095] After the last message word in a message block is calculated, the digest value of that message block needs to be obtained. According to the message encryption method described in steps 301-306 above, the digest values ​​in Table 5 should be generated after processing the adjacent fourth-to-last, third-to-last, second-to-last, and last message words. Specifically, the fourth-to-last 'a' and 'e' values ​​are generated during the processing of the fourth-to-last message word, the third-to-last 'a' and 'e' values ​​are generated during the processing of the third-to-last message word, and the processing of the fourth-to-last and third-to-last message words is completed within the previous clock cycle. The second-to-last 'a' and 'e' values ​​are generated during the processing of the second-to-last message word, the first-to-last 'a' and 'e' values ​​are generated during the processing of the last message word, and the processing of the second-to-last and last message words is completed within the subsequent clock cycle.

[0096] Table 5

[0097]

[0098]

[0099] According to the SHA-256 algorithm, the digest value calculated from the last message word in this message block is added to the digest value of the previous message block to form the digest value of this message block. The digest value of the previous message block is stored in the first to eighth digest registers of the digest register group, totaling eight digest registers. As shown in Table 6, each digest register stores digest register values ​​h0 to h7.

[0100] Table 6

[0101]

[0102] The first digest register h0 is added to the sixty-fourth a value (the last a value) of the first hash register in Table 5 to form a new digest register value h0', which is stored in the first digest register. The second digest register h1 is added to the sixty-third a value (the second-to-last a value) of the second hash register in Table 5 to form a new digest register value h1', and so on, forming the digest register values ​​h0' to h7' in Table 7. Each new digest register value can be obtained by adding it to the original digest register value at the same time as the corresponding hash register value is generated.

[0103] Table 7

[0104]

[0105] Figure 4 A flowchart of the summary register update method provided in the embodiments of the present invention is shown below. Figure 4 As shown, steps 401 to 404 are executed in the clock cycle before processing the adjacent fourth-to-last message word and the third-to-last message word, and steps 405 to 408 are executed in the clock cycle after processing the third-to-last message word and the adjacent second-to-last message word and the first-to-last message word.

[0106] Step 401: The first hash module calculates the fourth-to-last e value, the fourth-to-last a value, the first digest e value, and the first digest a value based on the fourth-to-last message word, the hash register value, the hash constant, and the digest register value.

[0107] The first hash module is used to calculate the digest value of the fourth-to-last message word (the 61st message word). According to the formula for calculating e, when t=61, the calculation process requires the d value before the calculation. 60 e 60 f 60 g 60 h 60 That is, the digest value of the fifth-to-last message word (the 60th message word) has been calculated and stored in the hash register set, as shown in Table 8, where d 60The value used is the fifty-seventh a in the D register, e 60 The value used is the sixtieth value in the E register, f 60 The value used is the fifty-ninth e in the F register, g 60 The value used is the fifty-eighth e in the G register, h 60 The value of the fifty-seventh e in register H is used. K is also used. 60 and W 60 K 60 W is a hash constant. 60 It is the fourth to last message word (the 61st message word).

[0108] Table 8

[0109]

[0110] According to the formula for calculating 'a', when t = 61, the calculation process requires the 'a' from before the initial calculation. 60 b 60 c 60 d 60 e 60 f 60 g 60 h 60 That is, the digest value of the fifth-to-last message word after calculation has been stored in the hash register group, as shown in Table 8, where a 60 The value used is the sixtieth value a in register A, b 60 The value used is the fifty-ninth a in register B, c 60 The value used is the fifty-eighth value of the C register. After calculation, the fourth-to-last value of a and the fourth-to-last value of e are obtained.

[0111] Therefore, similar to step 201, in the two message words processed in the previous clock cycle, the hash register values ​​a to h used in the process of calculating the digest value of the previous message word are obtained from the corresponding A to H registers, that is, a is obtained from register A, b is obtained from register B, and so on.

[0112] Based on the obtained fourth-to-last a value and fourth-to-last e value, referring to Tables 5, 6 and 7, it can be seen that the fourth-to-last a value is added to the original h3 in the fourth digest register to form the first digest a value (h3'), and the fourth-to-last e value is added to the original h7 in the eighth digest register to form the first digest e value (h7').

[0113] 402. The second hash module calculates the third-to-last e value, the third-to-last a value, the second digest e value, and the second digest a value based on the third-to-last message word, the hash register value, the fourth-to-last e value, the fourth-to-last a value, the hash constant, and the digest register value.

[0114] The second hash module is used to calculate the digest value of the third-to-last message word (the 62nd message word). According to the formula for calculating e, when t=62, the calculation process requires the d value before the calculation. 61 e 61 f 61 g 61 h 61 This refers to the digest value of the fourth-to-last message word (the 61st message word) after calculation, as shown in Table 8, where d... 61 The value used is the fifty-eighth value in the C register, e 61 The fourth-to-last value, e, is used, f 61 The value used is the sixtieth value in the E register, g 61 The value used is the fifty-ninth e in the F register, h 61 The value of the fifty-eighth term in the G register is used. K is also used. 61 and W 61 K 61 W is a hash constant. 61 It is the third to last message word (the 62nd message word).

[0115] According to the formula for calculating 'a', when t = 62, the calculation process requires the 'a' from before the initial calculation. 61 b 61 c 61 d 61 e 61 f 61 g 61 h 61 This refers to the digest value of the fourth-to-last message word (the 61st digest word) after calculation. Refer to Table 8, where 'a'... 61 The fourth-to-last value 'a' is used, and 'b' is used. 61 The value used is the sixtieth a in register A, c 61 The value of 'a' in register B is used. The values ​​of 'a' (third to last) and 'e' (third to last) are then calculated.

[0116] Therefore, similar to step 202, among the two message words processed in the previous clock cycle, the hash register values ​​a to h used in the calculation of the digest value of the second message word, except for a and e which are obtained from the calculation result of the digest value of the previous message word, are obtained from the register preceding the corresponding hash register, i.e. b is obtained from register A, c is obtained from register B, and so on.

[0117] Based on the obtained third-to-last a value and third-to-last e value, referring to Tables 5, 6 and 7, it can be seen that the third-to-last a value is added to the original h2 in the third digest register to form the second digest a value (h2'), and the third-to-last e value is added to the original h6 in the seventh digest register to form the second digest e value (h6').

[0118] 403. Cache the third 'a' value, the fourth 'a' value from the end, the third 'e' value from the end, and the fourth 'e' value from the end to the third, fourth, seventh, and eighth hash registers of the hash register group in sequence.

[0119] According to the description of step 203 above and referring to Table 5, the third hash register, fourth hash register, seventh hash register, and eighth hash register, which are not used in subsequent calculations, are used to cache the calculated a and e for subsequent calculations. This avoids the use of shift registers and saves clock cycles.

[0120] 404. Cache the second digest a value, the first digest a value, the second digest e value, and the first digest e value sequentially to the third digest register, the fourth digest register, the seventh digest register, and the eighth digest register of the digest register group.

[0121] As described above, the second digest a value (h2') is stored in the third digest register, the second digest e value (h6') is stored in the seventh digest register, the first digest a value (h3') is stored in the fourth digest register, and the first digest e value (h7') is stored in the eighth digest register.

[0122] 405. The first hash module calculates the penultimate e value, the penultimate a value, the third digest e value, and the third digest a value based on the penultimate message word, the hash register value, the hash constant, and the digest register value.

[0123] The first hash module is used to calculate the digest value of the second-to-last message word (the 63rd message word). According to the formula for calculating e, when t=63, the calculation process requires the d value before the calculation. 62 e 62 f 62 g 62 h 62 That is, the digest value of the third-to-last message word (the 62nd message word) has been calculated and stored in the hash register set, as shown in Table 9, where d 62 The value used is the fifty-ninth a in register B, e 62 The value used is the third-to-last e value in the G register, f 62 The value used is the fourth-to-last e value in the H register, g 62 The value used is the fifty-ninth e in the F register, h 62The value of the sixtieth element in the E register is used. K is also used. 62 and W 62 K 62 W is a hash constant. 62 It is the second to last message word (the 63rd message word).

[0124] Table 9

[0125]

[0126] According to the formula for calculating 'a', when t = 63, the calculation process requires the 'a' from before the initial calculation. 62 b 62 c 62 d 62 e 62 f 62 g 62 h 62 This refers to the digest value of the third-to-last message word (the 62nd message word) after calculation, as shown in Table 9, where 'a'... 62 The value used is the third-to-last value 'a' in the C register, b. 62 The value used is the fourth-to-last value 'a' in the D register, c 62 The value used is the sixtieth 'a' in register A. The second-to-last 'a' and second-to-last 'e' values ​​are then calculated.

[0127] Therefore, similar to step 304, in the two message words processed in the later clock cycle, the hash register values ​​a to h used in the process of calculating the digest value of the first message word are as follows: a is obtained from the third hash register, b is obtained from the fourth hash register, c is obtained from the first hash register, d is obtained from the second hash register, e is obtained from the seventh hash register, f is obtained from the eighth hash register, g is obtained from the fifth hash register, and h is obtained from the sixth hash register.

[0128] Based on the second-to-last 'a' value and the second-to-last 'e' value obtained, referring to Tables 5, 6, and 7, it can be seen that the second-to-last 'a' value is added to the original 'h1' value in the second digest register to form the third digest 'a' value (h1'), and the second-to-last 'e' value is added to the original 'h5' value in the sixth digest register to form the third digest 'e' value (h5').

[0129] 406. The second hash module calculates the fourth digest e value and the fourth digest a value based on the last message word, the hash register value, the second-to-last e value, the second-to-last a value, the hash constant, and the digest register value.

[0130] The second hash module is used to calculate the digest value of the last message word (the 64th message word). According to the formula for calculating e, when t=64, the calculation process requires the d value before the calculation.63 e 63 f 63 g 63 h 63 This refers to the digest value of the second-to-last message word (the 63rd message word) after calculation, as shown in Table 9, where d... 63 The value used is the sixtieth a in register A, e 63 The second-to-last e value is used, f 63 The value used is the third-to-last e value in the G register, g 63 The value used is the fourth-to-last e value in the H register, h 61 The value of the sixtieth element in the E register is used. K is also used. 63 and W 63 K 63 W is a hash constant. 63 It is the last message word (the 64th message word).

[0131] According to the formula for calculating 'a', when t = 64, the calculation process requires the 'a' from before the initial calculation. 63 b 63 c 63 d 63 e 63 f 63 g 63 h 63 This refers to the digest value of the second-to-last message word (the 63rd message word) after calculation, as shown in Table 9, where 'a'... 63 The second-to-last value of 'a' is used, and 'b' is used. 61 The value used is the third-to-last 'a' value in the C register, c 63 The fourth-to-last 'a' value in the D register is used. The last 'a' value and the last 'e' value are obtained through calculation.

[0132] Therefore, similar to step 305, in the two message words processed in the later clock cycle, among the hash register values ​​a to h used in the calculation of the digest value of the later message word, except for a and e which are calculated using the previous message word, b is obtained from the third hash register, c is obtained from the fourth hash register, d is obtained from the first hash register, f is obtained from the seventh hash register, g is obtained from the eighth hash register, and h is obtained from the fifth hash register.

[0133] Based on the obtained last 'a' value and last 'e' value, and referring to Tables 5, 6 and 7, it can be seen that the last 'a' value is added to the original h0 value in the first digest register to form the fourth digest 'a' value (h0'), and the last 'e' value is added to the original h4 value in the fifth digest register to form the fourth digest 'e' value (h4').

[0134] 407. Cache the fourth digest a value, the third digest a value, the fourth digest e value, and the third digest e value sequentially to the first digest register, the second digest register, the fifth digest register, and the sixth digest register of the digest register group.

[0135] As described above, the fourth digest a value (h0') is stored in the first digest register, the fourth digest e value (h4') is stored in the fifth digest register, the third digest a value (h1') is stored in the second digest register, and the third digest e value (h5') is stored in the sixth digest register.

[0136] The step of storing the last 'a' value and the last 'e' value in the hash register is omitted here because the values ​​in the hash register are mainly used for calculating the digest values ​​of each message word. The last 'a' value and the last 'e' value are the digest values ​​of the last message word in the message block, which are not used in subsequent calculations, so they do not need to be stored in the hash register. The last 'a' value and the last 'e' value calculated here are only used to generate the fourth digest 'a' value and the fourth digest 'e' value.

[0137] 408. When the encryption mode is single hash, the fourth digest a value, the third digest a value, the fourth digest e value, and the third digest e value are cached sequentially to the first hash register, the second hash register, the fifth hash register, and the sixth hash register of the hash register group; at the same time, the digest register values ​​in the third digest register, the fourth digest register, the seventh digest register, and the eighth digest register of the digest register group are cached sequentially to the third hash register, the fourth hash register, the seventh hash register, and the eighth hash register of the hash register group; when the encryption mode is double hash, and the clock cycle after processing the penultimate message word and the penultimate message word is the last clock cycle of the first round of hash calculation in double hash, the initial hash value is stored in the hash register group.

[0138] Specifically, the digest register update method provided in this embodiment is applicable to the SHA-2 series algorithms. In single hashing, after calculating the digest values ​​for the last two message words in the last clock cycle (later clock cycle) of a message block, the third digest a value, third digest e value, fourth digest a value, and fourth digest e value are obtained. These four digest values, besides being stored in the corresponding digest registers in step 407, also need to be stored in the corresponding hash registers for use in the digest value calculation of the next message block. Additionally, after calculating the digest values ​​for the fourth-to-last and third-to-last message words in the second-to-last clock cycle (previous clock cycle), the first digest a value, first digest e value, second digest a value, and second digest e value are obtained. These four digest values ​​were stored in the corresponding digest registers in step 404. At this point, these values ​​also need to be retrieved from the digest registers and stored in the corresponding hash registers, ensuring that the hash register values ​​stored in the hash register group are the same as the updated digest register values, for use in the digest value calculation of the next message block.

[0139] When using this method to cache the updated digest register value into the hash register group, no additional clock cycles are required. In the subsequent clock cycle, while calculating four new digest values, the four new digest values ​​that were calculated and stored in the digest register group in the previous clock cycle are retrieved, and the eight values ​​are updated together to update the eight hash register values ​​in the hash register group.

[0140] In double hashing, after the digest value of the last message word in the message block is calculated in the first round of hash calculation, the digest register group stores the digest values ​​of this message block, which total eight. These eight digest values ​​are padded and then eight constant message words are added to form 16 original message words. These 16 original message words are then used as the new input message block for the second round of hash calculation, i.e., the calculation of the message block digest value. Before the calculation, the initial hash value needs to be stored in the hash register group.

[0141] The next clock cycle begins the second round of hash calculation for double hashing, with the two message words to be processed being retrieved sequentially from the digest register set. After four clock cycles, once all eight digest values ​​in the digest register set have been calculated, the control module provides the remaining eight specified constant message words, which are eight fixed constants.

[0142] The flow of digest register values ​​in the digest register group can be controlled by the encryption mode control signal. In the first round of hash calculation in single hash mode and double hash mode, during the last clock cycle of processing each message block except the last message block, the fourth digest a value, the third digest a value, the fourth digest e value, and the third digest e value are cached in the first hash register, the second hash register, the fifth hash register, and the sixth hash register of the hash register group. At the same time, the digest register values ​​in the third digest register, the fourth digest register, the seventh digest register, and the eighth digest register of the digest register group are cached in the third hash register, the fourth hash register, the seventh hash register, and the eighth hash register of the hash register group in sequence. If it is double hash, and the clock cycle after processing the second-to-last message word and the last message word is the last clock cycle of the first round of hash calculation in double hash, the initial hash value is stored in the hash register group.

[0143] In double hash mode, the digest value register group is not initialized before the second hash calculation begins; only the hash register group is initialized. The digest value calculation in the second hash calculation process directly uses the initial value of the digest value register, rather than the current value of the digest value register.

[0144] The digest register group update method provided in the above embodiments includes a message encryption method for digest register value calculation. This method, like the message encryption method described in steps 301 to 307, uses two hash modules to work simultaneously in the same clock cycle. The two hash modules calculate the digest value of two adjacent message words respectively, realizing the processing of two message words in one clock cycle. Compared with the existing case where only one message word is processed in one clock cycle, this reduces the clock cycle used for message word digest value calculation during message encryption, thereby significantly improving the user experience.

[0145] While the hash module calculates the message digest value, the message encryption method provided in this embodiment of the invention may also include a step of constructing 16 original message words in a message block. The 16 original message words are stored in a message word register group consisting of 16 message word registers. At this point, the message word register group is full. When all 64 words constructed in this message block have been processed, the message word register group is not full until the 16 message word registers have stored all 16 original message words of the new message block, at which point it becomes full.

[0146] After the two hash modules have processed the first 16 raw message words stored in the message word register group, the subsequent construction steps of the two message words and the calculation of the digest values ​​of the two constructed message words are performed simultaneously.

[0147] The specific steps for constructing a message word include: the first hash module calculates the Nth constructed message word based on the original message word; the second hash module calculates the (N+1)th constructed message word based on the original message word; and the Nth and (N+1)th constructed message words are sequentially cached to the Mth and (M+1)th message word registers in the message word register group, where M = N% of the number of message word registers.

[0148] Specifically, the calculation of the message word is performed based on the known message word construction formula.

[0149] W t =σ1(W t-2 )+W t-7 +σ0(W t-15 )+W t-16 Where, σ0(x)=S 7 (x)⊕S 18 (x)⊕R 3 (x);

[0150] σ1(x)=S 17 (x)⊕S 19 (x)⊕R 10 (x); S n It is a circular right shift of n bits, R n It means right shift by n bits, and "⊕" means bitwise XOR.

[0151] For example, W0~W 15 These are the first to sixteenth message words, all original message words, stored in the first to sixteenth message word registers respectively, as shown in Table 10. The first hash module calculates the seventeenth message word W according to the formula. 16 t=16, requiring the use of the original message words W0, W1, W9 and W 14 Simultaneously, the second hash module calculates the eighteenth message word W according to the formula. 17 t=17, requiring the use of the original message words W1, W2, and W... 10 and W 15 .

[0152] Table 10

[0153]

[0154] Based on the formula, it can be deduced that when calculating the next nineteenth and twentieth message words, t is 18 and 19 respectively. The message words required for the nineteenth message word are W2, W3, and W... 11 and W 16 The twentieth message requires the message words W3, W4, and W. 12 and W 17Therefore, the calculation of the nineteenth and twentieth message words will no longer use the first message word W0 and the second message word W1, but will use the seventeenth message word W. 16 And the eighteenth message word W 17 Therefore, the previously calculated seventeenth message word W can be... 16 And the eighteenth message word W 17 The messages are stored in the first message word register and the second message word register, as shown in Table 11, to improve the utilization of storage space.

[0155] Table 11

[0156]

[0157] There is a correspondence between the storage location M of the constructed message word and the number N of the constructed message word, that is, M = N % number of message registers, where "%" represents the remainder. The number of message registers is the number of message registers in the message register group, for example, 16. When constructing the seventeenth message word W... 16 When N is 17, taking the remainder of 17 divided by 16 gives 1, so M equals 1. This means the seventeenth message word W... 16 It is stored in the first message word register.

[0158] Furthermore, the source of the original message words differs depending on the encryption mode. When the encryption mode is single hash, or when it's double hash and during the first round of hash calculation in double hash, the original message words come from the message word register set. This is because in single hash, the original message words of the current message block are stored in the message word register set. Once the register set is full (16 original message words), subsequent message word construction and digest value calculations are performed. Similarly, in the first round of hash calculation in double hash, the original message words of the current message block are also stored in the message word register set. Once the register set is full (16 original message words), subsequent message word construction and digest value calculations are performed.

[0159] When the encryption mode is double hashing and during the second round of hash calculation in double hashing, the original message words come from the digest register set and constant digest words. This is because after the first round of hash calculation in double hashing, the digest value of the current message block is stored in the digest register set, which contains eight words. These, along with the eight constant digest words, form 16 original message words, which are used as the new input message block for constructing the message words and calculating the digest value. Therefore, during the second round of hash calculation, the original message words come from the digest register set and constant message words.

[0160] The above-described message word construction method is a component of the message encryption method provided in this embodiment of the invention. It employs two hash modules working simultaneously, which can calculate the construction of message words separately within the same clock cycle. This enables the construction of two new message words in one clock cycle, which reduces the number of clock cycles compared to the existing method of constructing only one message word in one clock cycle. In addition, the message word construction step can be performed synchronously with the calculation of the message word digest value without occupying additional clock cycles, resulting in high processing efficiency and significantly improving the user experience.

[0161] As mentioned above, when a message block is processed, the message word register group becomes in a state where it is not full. At this time, the original message word of the next message block is needed. The specific methods include: when the encryption mode is single hash, or when the encryption mode is double hash and the first round of hash calculation is in double hash, the message word buffer register group outputs a supplementary message word to the message word register group.

[0162] In implementing this method, since two hash modules can process two message words within one clock cycle, the method can be designed to output two adjacent supplementary message words to the message word register group within one clock cycle. For example, the first input is W0 and W1, the second input is W2 and W3, and so on, until the 16 message word registers are full. The number of supplementary message words output each time depends on the bit width of the connection path between the message word buffer register group and the message word register group, as well as the number of bits in the supplementary message word. Specifically, for the SHA-256 algorithm, the number of bits in the supplementary message word is 32 bits. When the bit width of the connection path between the message word buffer register group and the message word register group is 64 bits, two message words can be output each time. For the SHA-512 algorithm, the number of bits in the supplementary message word is 64 bits, so only one supplementary message word can be output each time.

[0163] The source of the supplementary message word is the message word buffer register group. In this embodiment of the invention, the message word buffer register group has two buffer register queues. The first buffer register queue contains two buffer registers, each buffer register being 32 bits. For the SHA-256 algorithm, it is used to cache two adjacent supplementary message words. For the SHA-512 algorithm, it is used to cache one supplementary message word.

[0164] As mentioned above, when the encryption mode is single hash, or when the encryption mode is double hash and the hash calculation is performed in the first round of double hash, the hash module needs to obtain the message word from the message word register. In both cases, when the message word register group becomes in a state that is not full, that is, when the digest of an input message block is calculated, the message word buffer register group outputs one or two message words to the message word register group.

[0165] The second buffer register queue also contains two buffer registers, each 32 bits, used to buffer candidate message words following the supplementary message word. Similarly, for the SHA-256 algorithm, it buffers two adjacent candidate message words, and for the SHA-512 algorithm, it buffers one candidate message word. When the supplementary message word of the first buffer register queue is output in a certain clock cycle, the message word buffer register group becomes in a non-full state, and the candidate message word in the second buffer register queue becomes the supplementary message word. When the next clock cycle arrives, if it is determined that it needs to be output to the message word register group, the supplementary message word is output. At the same time, the first buffer register queue continues to buffer the following candidate message words from the padding module. In this way, the two buffer register queues are used alternately to output supplementary message words to the message word register group and alternately to input candidate message words from the padding module until the message word register group is full.

[0166] The above-mentioned message word supplementation method is a component of the message encryption method provided in the embodiments of the present invention. Since two buffer register queues are used in the message word buffer register group, one queue outputs the supplementary message word and the other queue receives the candidate message word in the same clock cycle. In the next cycle, one queue receives the candidate message word and the other queue outputs the supplementary message word. The two queues alternately output message words, so that there can be a message word output in every clock cycle. The processing is compact and efficient, which can significantly improve the user experience.

[0167] As described above, whenever the message word buffer register group is not full, it will receive the candidate message word from the padding module so that it can output the supplementary message word to the message word register group whenever needed. This realizes the pipelined method of supplementing message words, which is compact, does not waste clock cycles, and is highly efficient.

[0168] Figure 5 This is a block diagram of a message encryption device provided in an embodiment of the present invention. Figure 6 for Figure 5 The block diagram shown is of the first hash module in the message encryption device. Figure 7 for Figure 5 The block diagram of the second hash module in the message encryption device shown is as follows: Figures 5-7 As shown, the message encryption device executes the message encryption method described in the above embodiments. The specific method can be found in the description of steps 301 to 307, and will not be repeated here.

[0169] like Figures 5-7 As shown, the device includes: a hash register group 1, a message word register group 2, a first hash module 3, and a second hash module 4; the hash register group 1 is used to cache hash register values; the message word register group 2 is used to cache message words.

[0170] The first hash module 3 includes a first 4-2 compressor 301, a first 5-2 compressor 302, a second 4-2 compressor 303, a first 3-2 compressor 304, and a first carry-look ahead adder 305 connected in sequence, and a second 5-2 compressor 306, a third 4-2 compressor 307, a fourth 3-2 compressor 308, and a fourth carry-look ahead adder 309 connected in sequence. The output of the first 5-2 compressor 302 is connected to the input of the second 5-2 compressor 306. The hash register values ​​of the hash register group 1 are input to the first 5-2 compressor 302, the second 4-2 compressor 303, and the second 5-2 compressor 306. Message words are input to either the first 4-2 compressor 301 or the first 5-2 compressor 302. The carry-look ahead adder is abbreviated as CLA.

[0171] The second hash module 4 includes a fourth 4-2 compressor 401, a third 5-2 compressor 402, a fifth 4-2 compressor 403, a sixth 3-2 compressor 404, and a sixth carry-lookahead adder 405 connected in sequence, and a fourth 5-2 compressor 406, a sixth 4-2 compressor 407, a ninth 3-2 compressor 408, and a ninth carry-lookahead adder 409 connected in sequence. The output of the third 5-2 compressor 402 is connected to the input of the fourth 5-2 compressor 406. The hash register value of the hash register group 1 is input to the third 5-2 compressor 402, the fifth 4-2 compressor 403, and the fourth 5-2 compressor 406. The output of the first carry-lookahead adder 305 is connected to the third 5-2 compressor 402, and the output of the fourth carry-lookahead adder 309 is connected to the fourth 5-2 compressor 406. The message word is input to the fourth 4-2 compressor 401 or the third 5-2 compressor 402.

[0172] The outputs of the first carry-lookahead adder 305, the fourth carry-lookahead adder 309, the sixth carry-lookahead adder 405, and the ninth carry-lookahead adder 409 are connected to hash register group 1.

[0173] Figure 6 and Figure 7 The first hash module further includes a first ssigm0 unit and a first ssigm1 unit, and the second hash module further includes a second ssigm0 unit and a second ssigm1 unit, wherein the first ssigm0 unit and the second ssigm1 unit perform the operation on the input x: σ0(x) = S 7 (x)⊕S 18 (x)⊕R 3 (x), the first and second ssigm1 units perform the operation on the input x: σ1(x) = S 17 (x)⊕S 19(x)⊕R 10 (x), S n It is a circular right shift of n bits, R n It means right shift by n bits, and "⊕" means bitwise XOR.

[0174] According to the message word construction formula: W t =σ1(W t-2 )+W t-7 +σ0(W t-15 )+W t-16 The first ssigm0 unit and the second ssigm0 unit input is W. t-15 The inputs of the first and second ssigm1 units are W. t-2 t indicates that the message being processed is the (t+1)th message.

[0175] Figure 6 and Figure 7 The first hash module further includes a first lsigm0 unit and a first lsigm1 unit, and the second hash module further includes a second lsigm0 unit and a second lsigm1 unit. The partial digest value is calculated using the formula: T1 = h t-1 +Σ1(e t-1 )+Ch(e t-1 ,f t-1 ,g t-1 )+K t-1 +W t-1 T2=Σ0(a t-1 )+Maj(a t-1 ,b t-1 ,c t-1 ), where the first lsigm0 unit and the second lsigm0 unit perform the operation: Σ0(a t-1 ), a t-1 The value 'a' is one of the digest values ​​a~h from the previous message word. The first and second lsigm1 units perform the operation: Σ1(e t-1 ), e t-1 e is the digest value of the message preceding the current message word, from a to h.

[0176] Figure 6 and Figure 7 The first hash module further includes a first ch unit and a first Maj unit, and the second hash module further includes a second ch unit and a second Maj unit. According to the partial digest value calculation formula mentioned above, the first ch unit and the second ch unit perform the following operation: Ch(e t-1 ,f t-1 ,g t-1 ), e t-1 f t-1 and gt-1 These are e, f, and g, respectively, from the digest values ​​a to h of the message preceding the current message. The first and second Maj units perform the operation: Maj(a t-1 ,b t-1 ,c t-1 ), a t-1 ,b t-1 ,c t-1 These are a, b, and c, respectively, from the digest values ​​a to h of the message preceding the current message.

[0177] Each compressor adds multiple input values ​​and outputs a single value, with the number of output values ​​being less than the number of input values. Each carry-lookahead adder adds the fewer values ​​output by the compressors and outputs a single register value. By combining compressors and carry-lookahead adders, the number of adders required can be reduced. Since adders have a relatively large latency while compressors have a relatively small latency, reducing the number of adders can significantly shorten the critical path length in the addition calculation process, thereby reducing device latency and improving device processing speed.

[0178] As described above, the hash register group 1 caches eight hash register values, a to h. After calculating the digest value of two message words, a portion of the hash register values ​​are updated. The specific update method is the message encryption method described in the above embodiment.

[0179] In the first hash module, the first 4-2 compressor 301, the first 5-2 compressor 302, the second 4-2 compressor 303, the first 3-2 compressor 304, and the first carry-lookahead adder 305 are connected sequentially. The first carry-lookahead adder 305 outputs the first e value e1 of the current message word, which is T1+d in the above digest value calculation formula. The e, f, g, and h values ​​in the hash register are input to the first 5-2 compressor 302, and the hash constant k corresponding to the current message word is also input. t The 'd' value in the hash register is input to the second 4-2 compressor 303. If the message word is the first 16 raw message words, it is directly input from message word register group 2 to the first 5-2 compressor 302. Figure 6 A branch Wt is added to the output of the first 4-2 compressor to represent the input of the first 16 raw message words. If the message word is a constructed message word, the output result of the first 4-2 compressor 301 is used to input the first 5-2 compressor 302. The input of the message words can be controlled by the control module.

[0180] The second 5-2 compressor 306, the third 4-2 compressor 307, the fourth 3-2 compressor 308, and the fourth carry-lookahead adder 309 are connected in sequence, and the output of the first 5-2 compressor 302 is connected to the input of the second 5-2 compressor 306. The fourth carry-lookahead adder 309 outputs the first 'a' value a1 of the current message word, which is T1+T2 in the above digest value calculation formula. The values ​​a, b, and c in the hash register are input to the second 5-2 compressor 306.

[0181] W of the message word register group t-2 W t-7 W t-15 W t-16 Input the first 4-2 compressor to calculate the constructed message word.

[0182] After the first hash module 3 processes a message word, the second hash module 4 processes the next message word, and its structure is exactly the same as that of the first hash module 3. The fourth 4-2 compressor 401, the third 5-2 compressor 402, the fifth 4-2 compressor 403, the sixth 3-2 compressor 404, and the sixth carry-lookahead adder 405 are connected sequentially. The sixth carry-lookahead adder 405 outputs the second e value e2 of the current message word, which is T1+d in the above digest value calculation formula. The f, g, and h values ​​in the hash register are input to the third 5-2 compressor 402. The output of the first carry-lookahead adder 305 is connected to the third 5-2 compressor 402 to input the first e value e1. The hash constant k corresponding to the current message word is also input. t The 'd' value in the hash register is input to the fifth 4-2 compressor 403. If the message word is the first 16 raw message words, it is directly input from message word register group 2 to the third 5-2 compressor 402. Figure 7 Add a branch W to the output of the first 4-2 compressor. t+1 This indicates the input of the first 16 raw message words. If the message word is a constructed message word, the output of the fourth compressor 4-2 401 is used as the input to the third compressor 5-2 402. The input of the message words can be controlled by the control module.

[0183] The fourth 5-2 compressor 406, the sixth 4-2 compressor 407, the ninth 3-2 compressor 408, and the ninth carry-lookahead adder 409 are connected in sequence. The output of the third 5-2 compressor 402 is connected to the input of the fourth 5-2 compressor 406. The ninth carry-lookahead adder 409 outputs the second a value a2 of the current message word, which is T1+T2 in the above digest value calculation formula. The b and c values ​​in the hash register are input to the fourth 5-2 compressor 406. The output of the fourth carry-lookahead adder 309 is connected to the fourth 5-2 compressor 406 to input the first a value a1.

[0184] Finally, the first e value e1 of the first carry-lookahead adder 305, the first a value a1 of the fourth carry-lookahead adder 309, the second e value e2 of the sixth carry-lookahead adder 405, and the second a value a2 of the ninth carry-lookahead adder 409 are stored in hash register group 1 through the connection with hash register group 1.

[0185] The hash register group specifically includes eight registers, from the first hash register to the eighth hash register. The storage method for the four digest values ​​calculated by the first and second hash modules for two message words in the first clock cycle (previous clock cycle) is as follows: the output of the first carry-lookahead adder is connected to the eighth hash register, the output of the fourth carry-lookahead adder is connected to the fourth hash register, the output of the sixth carry-lookahead adder is connected to the seventh hash register, and the output of the ninth carry-lookahead adder is connected to the third hash register. This forms the hash register values ​​shown in Table 3. The output connection method of each carry-lookahead adder is controlled by the control module.

[0186] In the second clock cycle (after the first clock cycle), following the first clock cycle (the previous clock cycle), the first hash module 3 and the second hash module 4 calculate the digest values ​​of the two consecutive message words based on the partially updated hash register values ​​in Table 3, obtaining four digest values: the third a value, the third e value, the fourth a value, and the fourth e value. Their storage method is as follows: the output of the first carry-lookahead adder is connected to the sixth hash register; the output of the fourth carry-lookahead adder is connected to the second hash register; the output of the sixth carry-lookahead adder is connected to the fifth hash register; and the output of the ninth carry-lookahead adder is connected to the first hash register. This forms the hash register values ​​in Table 4. The output connection method of each carry-lookahead adder is controlled by the control module.

[0187] In the message encryption module provided in this embodiment of the invention, since two hash modules work simultaneously in the same clock cycle, the two hash modules calculate the digest value of two adjacent message words respectively, realizing the processing of two message words in one clock cycle. Compared with the existing case of processing only one message word in one clock cycle, the clock cycle used for message word digest value calculation during message encryption is reduced, thereby significantly improving the user experience.

[0188] In the message encryption device provided in the above embodiments, such as Figure 5As shown, it may also include a control module 5, as described above, used to control the input and output of the first hash module 3 and the second hash module 4 until all message words in the message block have been processed. That is, by controlling which register value is input to the hash register group and the message word register group, and controlling the output to which position in the digest register group and the hash register group, the first hash module 3 and the second hash module 4 sequentially perform message word digest calculation in the previous clock cycle, and then sequentially perform message word digest calculation in the next clock cycle. Then it is determined whether all message words in the message block have been processed. If not, the next previous clock cycle is entered, then the next clock cycle is entered, and so on, until all message words in the message block have been processed.

[0189] In the aforementioned message encryption devices, such as Figures 5-7 As shown, it may also include a digest register group 6, which is used to cache digest register values. The digest register value is generated by adding the digest register value of the current message block to the digest register value obtained from the previous message block after the digest value of the current message block is calculated. According to the digest register update method described in steps 401 to 408 of the above message encryption method, it can be seen that in the last two clock cycles (including the previous clock cycle and the next clock cycle) of the current message block processing, the fourth-to-last and third-to-last message words of the current message block are processed in the previous clock cycle, and the second-to-last and last message words of the current message block are processed in the next clock cycle.

[0190] The first hash module 3 includes a second 3-2 compressor 310 and a second carry-lookahead adder 311 connected in sequence. The output of the first 3-2 compressor 304 is connected to the input of the second 3-2 compressor 310.

[0191] During the previous clock cycle, the first 4-2 compressor 301, the first 5-2 compressor 302, the second 4-2 compressor 303, and the first 3-2 compressor 304 calculate the fourth-to-last e value of the fourth-to-last message word. One output of the first 3-2 compressor 304 is fed into the first carry-lookahead adder 305 to form the fourth-to-last e value of the required number of bits. The other output is fed into the second 3-2 compressor 310 and the input digest register value (…). Figure 6 After being added together (represented by hx0), the result is fed into the second carry-lookahead adder 311 to form the first digest value e (h7') of the required number of bits. Figure 6 In the diagram, hx0' represents the output of the second carry-lookahead adder 311, which is connected to the digest register group. The digest register group includes eight registers, from the first digest register to the eighth digest register. Specifically, the digest register value input to the second 3-2 compressor 310 comes from the eighth digest register, and the output of the second carry-lookahead adder 311 is connected to the eighth digest register to update the digest value of the eighth digest register.

[0192] The first hash module 3 also includes a fifth 3-2 compressor 312 and a fifth carry-lookahead adder 313 connected in sequence, and the output of the fourth 3-2 compressor 308 is connected to the input of the fifth 3-2 compressor 312.

[0193] During the previous clock cycle, the first 4-2 compressor 301, the first 5-2 compressor 302, the second 5-2 compressor 306, the third 4-2 compressor 307, and the fourth 3-2 compressor 308 calculate the fourth-to-last 'a' value of the fourth-to-last message word. One output of the fourth 3-2 compressor 308 is fed into the fourth carry-looka-adder 309 to form the fourth-to-last 'a' value of the required number of bits. The other output is fed into the fifth 3-2 compressor 312 and the input digest register value (…). Figure 6 After being added together (represented by hx1), the result is fed into the fifth carry-looka adder 313 to form the first digest value a (h3') of the required number of bits. Figure 6 In this context, hx1' indicates that the output of the fifth carry-lookahead adder 313 is connected to the digest register group. Specifically, the digest register value input to the fifth 3-2 compressor 312 comes from the fourth digest register, and the output of the fifth carry-lookahead adder 313 is connected to the fourth digest register to update the digest value of the fourth digest register.

[0194] The second hash module 4 includes a seventh 3-2 compressor 410 and a seventh carry-lookahead adder 411 connected in sequence, and the output of the sixth 3-2 compressor 404 is connected to the input of the seventh 3-2 compressor 410.

[0195] During the previous clock cycle, the third-to-last e-value of the third-to-last message word is calculated by the fourth 4-2 compressor 401, the third 5-2 compressor 402, the fifth 4-2 compressor 403, and the sixth 3-2 compressor 404. One output of the sixth 3-2 compressor 404 is fed into the sixth carry-lookahead adder 405 to form the third-to-last e-value of the required number of bits. The other output is fed into the seventh 3-2 compressor 410 and the input digest register value (…). Figure 7 After being added together (represented by hx2), the result is fed into the seventh carry-lookahead adder 411 to form the second digest value e (h6') of the required number of bits. Figure 7 In this context, hx2' represents the output of the seventh carry-lookahead adder 411, which is connected to the digest register group. Specifically, the digest register value input to the seventh 3-2 compressor 410 comes from the seventh digest register, and the output of the seventh carry-lookahead adder 411 is connected to the seventh digest register to update the digest value of the seventh digest register.

[0196] The second hash module 4 also includes a tenth 3-2 compressor 412 and a tenth carry-lookahead adder 413 connected in sequence, and the output of the ninth 3-2 compressor 408 is connected to the input of the tenth 3-2 compressor 412.

[0197] During the previous clock cycle, the third-to-last 'a' value of the third-to-last message word is calculated by the fourth 4-2 compressor 401, the third 5-2 compressor 402, the fourth 5-2 compressor 406, the sixth 4-2 compressor 407, and the ninth 3-2 compressor 408. One output of the ninth 3-2 compressor 408 is fed into the ninth carry-looka-adder 409 to form the third-to-last 'a' value of the required number of bits. The other output is fed into the ninth 3-2 compressor 412 and the input digest register value (…). Figure 7 After being added together (represented by hx3), the result is fed into the tenth carry-looka adder 413 to form the second digest value a (h2') of the required number of bits. Figure 7 In this context, hx3' indicates that the output of the tenth carry-lookahead adder 413 is connected to the digest register group. Specifically, the digest register value input to the tenth 3-2 compressor 412 comes from the third digest register, and the output of the tenth carry-lookahead adder 413 is connected to the third digest register to update the digest value of the third digest register.

[0198] During the subsequent clock cycle, the first hash module calculates the penultimate e-value of the penultimate message word using the first 4-2 compressor 301, the first 5-2 compressor 302, the second 4-2 compressor 303, and the first 3-2 compressor 304. The output of the first 3-2 compressor 304 is fed into the first carry-lookahead adder 305 to form the penultimate e-value of the required number of bits. The other output is fed into the second 3-2 compressor 310, added to the input digest register value, and then fed into the second carry-lookahead adder 311 to form the third digest e-value (h5') of the required number of bits. The output of the second carry-lookahead adder 311 is connected to the digest register group. Specifically, the digest register value input to the second 3-2 compressor 310 comes from the sixth digest register, and the output of the second carry-lookahead adder 311 is connected to the sixth digest register to update the digest value of the sixth digest register.

[0199] During the subsequent clock cycle, the first hash module 3 calculates the penultimate 'a' value of the penultimate message word using the first 4-2 compressor 301, the first 5-2 compressor 302, the second 5-2 compressor 306, the third 4-2 compressor 307, and the fourth 3-2 compressor 308. One output of the fourth 3-2 compressor 308 is fed into the fourth carry-looka adder 309 to form the penultimate 'a' value of the required number of bits. The other output is fed into the fifth 3-2 compressor 312, added to the input digest register value, and then fed into the fifth carry-looka adder 313 to form the third digest 'a' value (h1') of the required number of bits. The output of the fifth carry-looka adder 313 is connected to the digest register group. Specifically, the digest register value input to the fifth 3-2 compressor 312 comes from the second digest register, and the output of the fifth carry-looka adder 313 is connected to the second digest register to update the digest value of the second digest register.

[0200] During the subsequent clock cycle, the penultimate e-value of the last message word is calculated by the fourth 4-2 compressor 401, the third 5-2 compressor 402, the fifth 4-2 compressor 403, and the sixth 3-2 compressor 404. One output of the sixth 3-2 compressor 404 is fed into the sixth carry-lookahead adder 405 to form the penultimate e-value of the required number of bits. The other output is fed into the seventh 3-2 compressor 410, added to the input digest register value, and then fed into the seventh carry-lookahead adder 411 to form the fourth digest e-value (h4') of the required number of bits. The output of the seventh carry-lookahead adder 411 is connected to the digest register group. Specifically, the digest register value input to the seventh 3-2 compressor 410 comes from the fifth digest register, and the output of the seventh carry-lookahead adder 411 is connected to the fifth digest register to update the digest value of the fifth digest register.

[0201] During the subsequent clock cycle, the penultimate 'a' value of the last message word is calculated by the fourth 4-2 compressor 401, the third 5-2 compressor 402, the fourth 5-2 compressor 406, the sixth 4-2 compressor 407, and the ninth 3-2 compressor 408. One output of the ninth 3-2 compressor 408 is fed into the ninth carry-looka-adder 409 to form the penultimate 'a' value of the required number of bits. The other output is fed into the ninth 3-2 compressor 412, added to the input digest register value, and then fed into the tenth carry-looka-adder 413 to form the fourth digest 'a' value (h0') of the required number of bits. The output of the tenth carry-looka-adder 413 is connected to the digest register group. Specifically, the digest register value input to the tenth 3-2 compressor 412 comes from the first digest register, and the output of the tenth carry-looka-adder 413 is connected to this first digest register to update the digest value of the first digest register. The updated digest register group is shown in Table 7.

[0202] When the encryption mode is single hash, the control module can be used to connect the outputs of the second carry-lookahead adder, the fifth carry-lookahead adder, the seventh carry-lookahead adder, and the tenth carry-lookahead adder to the hash register group, and input the digest register value into the hash register group; when the encryption mode is double hash and during the first round of hash calculation in double hash, the control module can be used to input the initial hash value into the hash register group.

[0203] As described above, the digest register update method provided in this embodiment is applicable not only to the single-hash SHA-256 algorithm but also to the double-hash SHA-256 algorithm. In the single-hash case, after calculating the digest values ​​of the last two message words in the last clock cycle (the next clock cycle) of message block computation, the third digest a value, the third digest e value, the fourth digest a value, and the fourth digest e value are obtained. These four digest values, in addition to being stored in the corresponding digest registers in step 407, also need to be stored in the corresponding hash registers for use in the digest value calculation of the next message block. Specifically, the third digest e value is output from the second carry-lookahead adder 311, the third digest a value is output from the fifth carry-lookahead adder 313, the fourth digest e value is output from the seventh carry-lookahead adder 411, and the fourth digest a value is output from the tenth carry-lookahead adder 413.

[0204] In addition, after calculating the digest values ​​of the fourth and third-to-last message words in the second-to-last clock cycle (previous clock cycle), the first digest a value, the first digest e value, the second digest a value, and the second digest e value are obtained. These four digest values ​​are stored in the corresponding digest registers in step 404. At this time, it is also necessary to retrieve the values ​​from these digest registers and store them in the corresponding hash registers for the digest value calculation of the next message block.

[0205] In the first round of hash calculation in double hashing, after the digest value of the last message word of the message block is calculated, the digest register group stores the digest value of this message block. This digest value is used as the new input message block, and then the second round of hash calculation, that is, the calculation of the message block digest value, is performed. Before the second round of hash calculation, the initial hash value needs to be stored in the hash register group.

[0206] The direction of the digest register value in the digest register group can be controlled by the encryption mode control signal. If it is a single hash, the outputs of the second carry-lookahead adder, the fifth carry-lookahead adder, the seventh carry-lookahead adder, and the tenth carry-lookahead adder are connected to the hash register group, and the digest register value is input into the hash register group. If it is a double hash and in the first round of hash calculation, the digest register value of the digest register group is used as the first eight original message words together with the eight padded constant message words to prepare for the second round of hash calculation, and the initial hash value is stored in the hash register group.

[0207] Figure 8 A block diagram of another message encryption device provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the message encryption device described in the above embodiment may further include a padding module 7 and a message word buffer register group 8. The message word buffer register group 8 includes a first buffer register queue 81 and a second buffer register queue 82. The output of the padding module 7 is connected to the message word buffer register group 8 through the control module 5, and the output of the message word buffer register group 8 is connected to the message word register group 2 through the control module 5. When the encryption mode is single hash, or when the encryption mode is double hash and the first round of hash calculation is performed in double hash, the control module is used to cause the message word buffer register group 2 to output supplementary message words to the message word register group.

[0208] As described above, when a message block is processed, the message word register group becomes incomplete. At this time, it is necessary to send the original message word of the next message block to the message word register group. The specific methods include: the message word buffer register group outputs supplementary message words to the message word register group; when the encryption mode is single hash, or when the encryption mode is double hash and in the first round of hash calculation in double hash, the message word for digest calculation comes from the message word register group. The message word register group is not full, which means that 16 original messages have not been received yet, and supplementary message words need to be input from the message word buffer register group; when the encryption mode is double hash and in the second round of hash calculation in double hash, the message word for digest calculation comes from the digest register and the constant message word provided by the control module, so it is not necessary to input supplementary message words from the message word buffer register group.

[0209] The message word buffer register set has two buffer register queues. The first buffer register queue contains two buffer registers to buffer one or two supplementary message words. The second buffer register queue also contains two buffer registers, which are used to buffer candidate message words that follow the supplementary message word. These can be one or two. When the supplementary message word in the first buffer register queue is output in a certain clock cycle, the candidate message word in the second buffer register queue becomes the supplementary message word. When the next clock cycle arrives, it is output to the message word register set as needed. While the supplementary message word is being output, the first buffer register queue continues to buffer the following candidate message word. The two buffer register queues are used alternately to output supplementary message words to the message word register set as needed until the message word register set is full.

[0210] The candidate message word comes from the padding module. When the message word buffer register is not full, it receives the candidate message word from the padding module. The padding module is used to pad and split the original input message, and output each message word in sequence.

[0211] In the aforementioned message encryption device, since two buffer register queues are used in the message word buffer register group, one queue outputs supplementary message words and the other queue receives candidate message words in the same clock cycle. In the next cycle, the order is reversed: one queue receives candidate message words and the other queue outputs supplementary message words. The two queues alternately output message words, so that message words are output in every clock cycle. The processing is compact and efficient, which can significantly improve the user experience.

[0212] In the message encryption device provided in the above embodiments, such as Figure 5 As shown, the first hash module 3 may further include a third 3-2 compressor 314 and a third carry-lookahead adder 315 connected in sequence, with the output of the first 4-2 compressor 301 connected to the third 3-2 compressor 314. The first 4-2 compressor 301, the third 3-2 compressor 314, and the third carry-lookahead adder 315 form a path for calculating a constructed message word based on the message word in the message word register group. Figure 6 The middle is represented as W t .

[0213] The second hash module 4 may further include an eighth 3-2 compressor 414 and an eighth carry-lookahead adder 415 connected in sequence, with the output of the fourth 4-2 compressor 401 connected to the eighth 3-2 compressor 414. The fourth 4-2 compressor 401, the eighth 3-2 compressor 414, and the eighth carry-lookahead adder 415 form a path for simultaneously calculating a constructed message word based on the message word in the message word register group, together with the first hash module 3. Figure 7 The middle is represented as W t+1 .

[0214] The outputs of the third carry-lookahead adder 315 and the eighth carry-lookahead adder 415 are connected to a message word register group. As described above, the message word register group includes 16 registers, from the first message word register to the sixteenth message word register. The control module controls which message word register the outputs of the third carry-lookahead adder 315 and the eighth carry-lookahead adder 415 are connected to. Specifically, when the third carry-lookahead adder 315 outputs the Nth construct message word, the eighth carry-lookahead adder 415 outputs the (N+1)th construct message word. The output of the third carry-lookahead adder 315 is connected to the Mth message word register in the message word register group, and the output of the eighth carry-lookahead adder 415 is connected to the (M+1)th message word register in the message word register group, where M = N % the number of message registers.

[0215] Specifically, there is a correspondence between the storage location M of the constructed message word and the number N of the constructed message word, that is, M = N % number of message registers, where "%" represents the remainder. The number of message word registers is the number of message word registers in the message word register group, for example, 16. When constructing the seventeenth message word W... 16 When N is 17, taking the remainder of 17 divided by 16 gives 1, so M equals 1. This means the seventeenth message word W... 16 It is stored in the first message word register.

[0216] As mentioned above, the message word construction process uses two hash modules working simultaneously, which can calculate the message word construction separately within the same clock cycle. This enables the construction of two new message words in one clock cycle, which reduces the number of clock cycles compared to the existing method of constructing only one message word per clock cycle. In addition, the message word construction step can be performed synchronously with the calculation of the message word digest value without occupying additional clock cycles, resulting in high processing efficiency and significantly improving the user experience.

[0217] In the message encryption method and device provided in the embodiments of the present invention, by appropriately setting the storage bits of each register, the method and device can be adapted to implement the SHA-512 encryption algorithm.

[0218] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A message encryption device, characterized in that, include: The system includes a hash register group, a message word register group, a first hash module, and a second hash module; the hash register group is used to cache hash register values; the message word register group is used to cache message words. During the clock cycle before processing adjacent first and second message words, the first hash module calculates the first e value and the first a value based on the first message word, the hash register value, and the hash constant. The second hash module calculates the second e value and the second a value based on the second message word, the hash register value, the first e value, the first a value, and the hash constant; and sequentially caches the second a value, the first a value, the second e value, and the first e value to the third hash register, the fourth hash register, the seventh hash register, and the eighth hash register of the hash register group. During the clock cycle following the processing of the second message word and the adjacent third and fourth message words, the first hash module calculates the third e value and the third a value based on the third message word, the hash register value, and the hash constant; the second hash module calculates the fourth e value and the fourth a value based on the fourth message word, the hash register value, the third e value, the third a value, and the hash constant; and sequentially caches the fourth a value, the third a value, the fourth e value, and the third e value to the first hash register, the second hash register, the fifth hash register, and the sixth hash register of the hash register group.

2. The apparatus according to claim 1, characterized in that, The first hash module includes a first 4-2 compressor, a first 5-2 compressor, a second 4-2 compressor, a first 3-2 compressor, and a first carry-lookahead adder connected in sequence, and a second 5-2 compressor, a third 4-2 compressor, a fourth 3-2 compressor, and a fourth carry-lookahead adder connected in sequence. The output of the first 5-2 compressor is connected to the input of the second 5-2 compressor. The hash register value is input to the first 5-2 compressor, the second 4-2 compressor, and the second 5-2 compressor. The message word is input to the first 4-2 compressor or the first 5-2 compressor; The second hash module includes a fourth 4-2 compressor, a third 5-2 compressor, a fifth 4-2 compressor, a sixth 3-2 compressor, and a sixth carry-lookahead adder connected in sequence. The fourth 5-2 compressor, the sixth 4-2 compressor, the ninth 3-2 compressor, and the ninth carry-lookahead adder are also connected in sequence. The output of the third 5-2 compressor is connected to the input of the fourth 5-2 compressor. The hash register value is input to the third 5-2 compressor, the fifth 4-2 compressor, and the fourth 5-2 compressor. The output of the first carry-lookahead adder is connected to the third 5-2 compressor, the output of the fourth carry-lookahead adder is connected to the fourth 5-2 compressor, and the message word is input to either the fourth 4-2 compressor or the third 5-2 compressor. The outputs of the first carry-lookahead adder, the fourth carry-lookahead adder, the sixth carry-lookahead adder, and the ninth carry-lookahead adder are connected to the hash register group.

3. The apparatus according to claim 2, characterized in that, It also includes a control module for controlling the input and output of the first hash module and the second hash module until all message words in the message block have been processed.

4. The apparatus according to claim 3, characterized in that, It also includes a digest register set, which is used to cache digest register values; The first hash module includes a second 3-2 compressor and a second carry-lookahead adder connected in sequence, and a fifth 3-2 compressor and a fifth carry-lookahead adder connected in sequence; the output of the first 3-2 compressor is connected to the input of the second 3-2 compressor, and the output of the fourth 3-2 compressor is connected to the input of the fifth 3-2 compressor; The second hash module includes a seventh 3-2 compressor and a seventh carry-lookahead adder connected in sequence, and a 10th 3-2 compressor and a 10th carry-lookahead adder connected in sequence; the output of the sixth 3-2 compressor is connected to the input of the seventh 3-2 compressor, and the output of the ninth 3-2 compressor is connected to the input of the 10th 3-2 compressor; The summary register value is input to the second 3-2 compressor, the fifth 3-2 compressor, the seventh 3-2 compressor, and the tenth 3-2 compressor; The outputs of the second carry-lookahead adder, the fifth carry-lookahead adder, the seventh carry-lookahead adder, and the tenth carry-lookahead adder are connected to the digest register group; When the encryption mode is single hash and it is the last clock cycle of message block processing, the control module is used to connect the outputs of the second carry-lookahead adder, the fifth carry-lookahead adder, the seventh carry-lookahead adder and the tenth carry-lookahead adder to the hash register group, and input the digest register value into the hash register group; When the encryption mode is double hash and during the first round of hash calculation in the double hash, the control module is used to input the initial hash value into the hash register group.

5. The apparatus according to claim 4, characterized in that, It also includes a padding module, and the message word buffer register group includes a first buffer register queue and a second buffer register queue; the output of the padding module is connected to the message word buffer register group, and the output of the message word buffer register group is connected to the message word register group; when the encryption mode is single hash, or when the encryption mode is double hash and the first round of hash calculation is performed in the double hash, the control module is used to cause the message word buffer register group to output supplementary message words to the message word register group.

6. The apparatus according to any one of claims 2 to 5, characterized in that, The first hash module further includes a third 3-2 compressor and a third carry-lookahead adder connected in sequence, and the output of the first 4-2 compressor is connected to the third 3-2 compressor; the second hash module further includes an eighth 3-2 compressor and an eighth carry-lookahead adder connected in sequence, and the output of the fourth 4-2 compressor is connected to the eighth 3-2 compressor; The outputs of the third carry-lookahead adder and the eighth carry-lookahead adder are connected to the message word register group.

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