Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present application relate to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate, a trench is formed in the substrate; a conductive layer is located in the trench, the conductive layer comprises a first conductive layer and a second conductive layer, the second conductive layer is located on the first conductive layer, and a projection area of a bottom of the second conductive layer in the trench is greater than a projection area of a top of the first conductive layer in the trench; a dielectric layer is located between the conductive layer and an inner wall of the trench, and a top of the dielectric layer is lower than a top of the first conductive layer; an isolation layer is located on the conductive layer; and a gap is enclosed by the isolation layer, the conductive layer, the dielectric layer and a side wall of the trench. A work function of the first conductive layer is greater than a work function of the second conductive layer. The opening speed of the transistor is improved, the gate-induced drain leakage current of the semiconductor structure is reduced, the reliability of the semiconductor structure is improved, and the power consumption of the semiconductor structure is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Metal oxide semiconductor (MOS) transistors are important components in integrated circuit manufacturing. MOS transistors are typically formed on a substrate. A MOS transistor includes a gate structure, and source and drain regions are formed in the substrate on both sides of the gate structure by implantation. The current flowing between the source and drain regions is controlled by controlling the voltage applied to the gate structure.

[0003] MOS transistors can be used to form memory, such as access transistors used in dynamic random access memory (DRAM), where the source region is connected to the bit line and the drain region is connected to the storage capacitor, which is typically used to store charge representing stored information. By controlling the MOS transistor to turn on and off, data information stored in the storage capacitor can be read through the bit line or written to the storage capacitor.

[0004] Currently, DRAM devices typically use buried word lines (BWs) for their access transistors. However, fabricating BWs can easily lead to gate-induced drain leakage (GIDL). GIDL occurs when a voltage is applied to the drain region, causing the PN junction to reverse-bias. Excess electron-hole pairs generated by electrothermal energy are driven by the electric field before they can recombine, resulting in leakage. GIDL becomes increasingly significant as DRAM device size decreases and the gate oxide layer thins. Excessive GIDL reduces the reliability of DRAM devices and increases power consumption, negatively impacting data storage and read / write operations. Summary of the Invention

[0005] This application provides a semiconductor structure and its fabrication method, which can optimize the gate-drain leakage current of semiconductor devices, thereby reducing the gate-drain voltage, suppressing the gate-drain leakage current, increasing the reliability of semiconductor devices, and reducing the power consumption of semiconductor devices.

[0006] This application provides a semiconductor structure, including:

[0007] The substrate, in which grooves are formed;

[0008] A conductive layer is located in the trench. The conductive layer includes a first conductive layer and a second conductive layer. The second conductive layer is located on the first conductive layer, and the projected area of ​​the bottom of the second conductive layer in the trench is greater than the projected area of ​​the top of the first conductive layer in the trench.

[0009] A dielectric layer is located between the conductive layer and the inner wall of the trench, and the top of the dielectric layer is lower than the top of the first conductive layer.

[0010] An isolation layer is located on top of the conductive layer;

[0011] The gap is formed by the isolation layer, the conductive layer, the dielectric layer, and the sidewalls of the trench;

[0012] The work function of the first conductive layer is greater than that of the second conductive layer.

[0013] In one embodiment, the top of the first conductive layer has a shape including at least one of Ω, triangle, trapezoid and π.

[0014] In one embodiment, a shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure isolates a plurality of spaced active regions in the substrate, the active regions are formed with the trench, and active electrode / drain electrode regions are formed on opposite sides of the trench, respectively.

[0015] The bottom of the void is not lower than the top of the source / drain region.

[0016] In one embodiment, the gap includes a first gap and a second gap, the first gap being located between the second conductive layer and the sidewall of the trench, and the second gap being located between the first conductive layer and the sidewall of the trench.

[0017] In one embodiment, in a direction perpendicular to the substrate surface, the projected area of ​​the first void in the trench is smaller than the projected area of ​​the second void in the trench.

[0018] In one embodiment, the top of the isolation layer is flush with the top of the trench.

[0019] In one embodiment, the top of the conductive layer is lower than the top of the trench.

[0020] In one embodiment, the projected area of ​​the top of the second conductive layer in the trench is equal to the projected area of ​​the bottom of the second conductive layer in the trench.

[0021] In one embodiment, the semiconductor structure further includes:

[0022] A diffusion barrier layer is located between the conductive layer and the dielectric layer, and the upper surface of the diffusion barrier layer is flush with the upper surface of the dielectric layer.

[0023] A method for fabricating a semiconductor structure, comprising:

[0024] Provide a substrate in which grooves are formed;

[0025] A dielectric layer and a conductive layer are sequentially formed in a trench; the dielectric layer is located between the conductive layer and the inner wall of the trench; the conductive layer includes a first conductive layer and a second conductive layer located on the first conductive layer, the top of the dielectric layer is lower than the top of the first conductive layer, the bottom of the second conductive layer has a projected area in the trench that is greater than the top of the first conductive layer has a projected area in the trench that is greater than the top of the first conductive layer, and the work function of the first conductive layer is greater than the work function of the second conductive layer.

[0026] An isolation layer is formed on the conductive layer, and the isolation layer, the conductive layer, and the sidewalls of the trench form a void.

[0027] In one embodiment, a shallow trench isolation structure is formed in the substrate, which isolates a plurality of spaced active regions in the substrate. A trench is formed in the active region, and active electrode / drain electrode regions are formed on opposite sides of the trench, respectively.

[0028] In one embodiment, the bottom of the void is not lower than the top of the source / drain region.

[0029] In one embodiment, the top of the isolation layer is flush with the top of the trench.

[0030] In one embodiment, the voids include a first void and a second void, and a dielectric layer and a conductive layer are sequentially formed in the trench, including:

[0031] A dielectric layer and a first conductive layer are sequentially formed in the trench;

[0032] A second conductive layer is formed on the upper surface of the first conductive layer, and a first gap is formed between the second conductive layer and the sidewall of the trench, and a second gap is formed between the first conductive layer and the sidewall of the trench.

[0033] In one embodiment, a dielectric layer and a first conductive layer are sequentially formed in the trench, including:

[0034] A dielectric material layer is formed on the inner wall of the trench;

[0035] A first conductive material layer is formed in the trench, the first conductive material layer covers the dielectric material layer, and fills the trench;

[0036] The dielectric material layer and the first conductive material layer are etched to form the dielectric layer and the first conductive layer.

[0037] In one embodiment, before forming a first conductive material layer in the trench, the following steps are included:

[0038] A diffusion barrier material layer is formed in the trench, and the diffusion barrier material layer is located between the first conductive material layer and the dielectric material layer;

[0039] Etching of the dielectric material layer and the first conductive material layer also includes:

[0040] The diffusion barrier material layer is etched to obtain the diffusion barrier layer, and the upper surface of the diffusion barrier layer is flush with the upper surface of the dielectric layer.

[0041] In one embodiment, the top of the first conductive layer has a shape including at least one of Ω, triangle, trapezoid and π.

[0042] In one embodiment, a second conductive layer is formed on the upper surface of the first conductive layer, including:

[0043] A first sacrificial layer is formed on the sidewall of the trench, the first sacrificial layer is located above the medium layer, and there is a gap between the first sacrificial layers on opposite sidewalls of the trench;

[0044] A second conductive layer is formed in the gap, the second conductive layer fills the gap, and the second conductive layer is in contact with the first conductive layer;

[0045] Remove the first sacrificial layer to form the first void.

[0046] In one embodiment, before forming the first sacrificial layer on the sidewall of the trench, the method further includes:

[0047] A second sacrificial layer is formed on the upper surface of the dielectric layer, the second sacrificial layer surrounds the first conductive layer, and the top of the second sacrificial layer exposes the first conductive layer;

[0048] The bottom of the first sacrificial layer is flush with the top of the second sacrificial layer.

[0049] In one embodiment, before forming an isolation layer on the conductive layer, the method further includes:

[0050] Remove the second sacrificial layer to form a second void.

[0051] The aforementioned semiconductor structure includes: a substrate in which trenches are formed; a conductive layer located within the trenches, the conductive layer comprising a first conductive layer and a second conductive layer, the second conductive layer being located on the first conductive layer, and the projected area of ​​the bottom of the second conductive layer within the trench being larger than the projected area of ​​the top of the first conductive layer within the trench; a dielectric layer located between the conductive layer and the inner wall of the trench, and the top of the dielectric layer being lower than the top of the first conductive layer; an isolation layer located on the conductive layer; and a gap formed by the isolation layer, the conductive layer, the dielectric layer, and the sidewalls of the trench; wherein the work function of the first conductive layer is greater than the work function of the second conductive layer. In this application, the conductive layer serving as the gate structure includes a first conductive layer and a second conductive layer, and the work function of the first conductive layer is greater than the work function of the second conductive layer. This configuration improves the transistor's turn-on speed, reduces the gate-drain leakage current of the semiconductor structure, and simultaneously improves the reliability of the semiconductor structure and reduces its power consumption. Furthermore, in this application, the gate dielectric layer of the transistor is composed of a gap and a dielectric layer, reducing the gate-drain voltage and suppressing the gate-drain leakage current, thereby further improving the reliability of the semiconductor structure and reducing its power consumption.

[0052] The method for fabricating the aforementioned semiconductor structure includes providing a substrate in which trenches are formed; sequentially forming a dielectric layer and a conductive layer in the trenches; the dielectric layer being located between the conductive layer and the inner wall of the trench; the conductive layer comprising a first conductive layer and a second conductive layer on the first conductive layer, wherein the top of the dielectric layer is lower than the top of the first conductive layer, the projected area of ​​the bottom of the second conductive layer within the trench is greater than the projected area of ​​the top of the first conductive layer within the trench, and the work function of the first conductive layer is greater than the work function of the second conductive layer; and an isolation layer being formed on the conductive layer, the isolation layer, the conductive layer, the dielectric layer, and the sidewalls of the trench forming a void. In this application, the conductive layer serving as the gate structure comprises a first conductive layer and a second conductive layer, and the work function of the first conductive layer is greater than the work function of the second conductive layer. This configuration improves the transistor's turn-on speed, reduces the gate-drain leakage current of the semiconductor structure, and simultaneously improves the reliability of the semiconductor structure and reduces its power consumption. Furthermore, in this application, the gate dielectric layer of the storage transistor is composed of a void and a dielectric layer, reducing the gate-drain voltage and suppressing the gate-drain leakage current, thereby further improving the reliability of the semiconductor structure and reducing its power consumption. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure in one embodiment;

[0055] Figure 2 This is a flowchart illustrating step S104 in one embodiment;

[0056] Figure 3 This is a flowchart illustrating step S202 in one embodiment;

[0057] Figure 4 This is a schematic cross-sectional view of the semiconductor structure after the formation of the first conductive material layer in one embodiment;

[0058] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the first conductive layer in the first embodiment;

[0059] Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the first conductive layer in the second embodiment;

[0060] Figure 7 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the first conductive layer in the third embodiment;

[0061] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the first conductive layer in the fourth embodiment;

[0062] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after the formation of the second conductive layer in one embodiment;

[0063] Figure 10 for Figure 9 A cross-sectional schematic diagram of the semiconductor structure after the first gap is formed in one corresponding embodiment;

[0064] Figure 11 for Figure 10 A cross-sectional schematic diagram of the semiconductor structure after the second gap is formed in one corresponding embodiment;

[0065] Figure 12 This is a flowchart illustrating step S204 in one embodiment;

[0066] Figure 13 for Figure 11 A cross-sectional schematic diagram of the semiconductor structure after the isolation layer is formed in one corresponding embodiment.

[0067] Explanation of reference numerals in the attached figures:

[0068] 102, Substrate; 104, Trench; 106, Dielectric material layer; 108, First conductive material layer; 110, Diffusion barrier material layer; 112, First sacrificial layer; 114, Gap; 116, Second sacrificial layer; 202, Dielectric layer; 204, First conductive layer; 206, Diffusion barrier layer; 208, Second conductive layer; 210, First void; 212, Second void; 214, Void; 216, Isolation layer. Detailed Implementation

[0069] To facilitate understanding of the embodiments of this application, a more comprehensive description of the embodiments of this application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the embodiments of this application. However, the embodiments of this application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the embodiments of this application more thorough and complete.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein in the description of embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0071] In the description of the embodiments of this application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0072] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first conductive layer may be referred to as a second conductive layer, and similarly, a second conductive layer may be referred to as a first conductive layer. Both the first conductive layer and the second conductive layer are conductive layers, but they are not the same conductive layer.

[0073] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0074] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure in one embodiment, as shown below. Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor structure, including:

[0075] S102 provides a substrate in which grooves are formed.

[0076] Specifically, a trenched substrate is provided, which can be made of undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in this embodiment, the substrate is made of single-crystal silicon.

[0077] S104, a dielectric layer and a conductive layer are sequentially formed in the trench.

[0078] A dielectric layer and a conductive layer are sequentially formed in a trench, wherein the dielectric layer is located between the conductive layer and the inner wall of the trench; the conductive layer includes a first conductive layer and a second conductive layer located on the first conductive layer, the top of the dielectric layer is lower than the top of the first conductive layer, the projected area of ​​the bottom of the second conductive layer in the trench is larger than the projected area of ​​the top of the first conductive layer in the trench, and the work function of the first conductive layer is larger than the work function of the second conductive layer. Specifically, the dielectric layer covers the part of the sidewalls near the bottom of the trench and the bottom of the trench, and the conductive layer is filled between the dielectric layers on the sidewalls, the upper surface of the conductive layer is higher than the upper surface of the dielectric layer; from the bottom of the trench to the opening of the trench, the conductive layer includes a first conductive layer near the bottom of the trench and a second conductive layer near the top of the trench, wherein the first conductive layer and the second conductive layer are electrically connected, the orthographic projection area of ​​the bottom of the second conductive layer in the trench is larger than the orthographic projection area of ​​the top of the first conductive layer in the trench, that is, in the direction parallel to the upper surface of the substrate, the cross-sectional area of ​​the bottom of the second conductive layer is larger than the cross-sectional area of ​​the top of the first conductive layer. For those skilled in the art, when a semiconductor structure includes a memory device, the conductive layer serves as the gate of the memory transistor, and simultaneously, the conductive layer can serve as the word line structure of the memory device. It is understood that the sidewalls of the second conductive layer are isolated from the sidewalls of the trench.

[0079] S106, an isolation layer is formed on the conductive layer.

[0080] An isolation layer is formed on the conductive layer, and the isolation layer, the conductive layer, the dielectric layer, and the sidewalls of the trench form a void. Specifically, an isolation layer is formed on the conductive layer, and the isolation layer contacts the sidewalls of the trench. The unfilled portion within the space enclosed by the isolation layer, the conductive layer, the dielectric layer, and the sidewalls of the trench forms a void. This void, together with the dielectric layer, serves as the gate dielectric layer of the storage transistor, reducing the gate-drain voltage and effectively suppressing the gate-drain leakage current. This improves the reliability of the semiconductor structure and reduces its power consumption. When the semiconductor structure is a memory device, this enhances the data storage and read / write performance of the memory device.

[0081] The method for fabricating the aforementioned semiconductor structure includes providing a substrate in which trenches are formed; sequentially forming a dielectric layer and a conductive layer in the trenches; the dielectric layer being located between the conductive layer and the inner wall of the trench; the conductive layer comprising a first conductive layer and a second conductive layer on the first conductive layer, wherein the top of the dielectric layer is lower than the top of the first conductive layer, the projected area of ​​the bottom of the second conductive layer within the trench is greater than the projected area of ​​the top of the first conductive layer within the trench, and the work function of the first conductive layer is greater than the work function of the second conductive layer; and an isolation layer being formed on the conductive layer, the isolation layer, the conductive layer, the dielectric layer, and the sidewalls of the trench forming a void. In this application, the conductive layer serving as the gate structure comprises a first conductive layer and a second conductive layer, and the work function of the first conductive layer is greater than the work function of the second conductive layer. This configuration improves the turn-on speed of the storage transistor, reduces the gate-drain leakage current of the semiconductor structure, improves the reliability of the semiconductor structure, and reduces the power consumption of the semiconductor structure. When the semiconductor structure is a memory device, the data storage and read / write performance of the semiconductor structure is improved. Meanwhile, the gate dielectric layer of the storage transistor in this application is composed of gaps and dielectric layers, which reduces the gate-drain voltage and suppresses the gate-drain leakage current, thereby further improving the reliability of the semiconductor structure and reducing the power consumption of the semiconductor structure. At the same time, the data storage and read / write performance of the semiconductor structure is further improved.

[0082] In one embodiment, a shallow trench isolation structure is formed in the substrate, isolating several spaced-apart active regions within the substrate. Trenchings are formed within these active regions, with active / drain regions formed on opposite sides of each trench. In this embodiment, the source / drain regions are formed simultaneously after doping the active regions. Based on their connection relationships in the transistor structure, they can be further distinguished as source and drain regions; those subsequently connected to the bit line structure are source regions, and those connected to the storage capacitor are drain regions. The active regions are periodically arranged on the substrate at certain intervals, and the trenches formed within the active regions laterally penetrate several active regions and the shallow trench isolation structure between adjacent active regions. Word line structures are formed within the trenches, connecting several active regions. It should be noted that the present invention does not limit the formation order of the trenches, source / drain regions, and shallow trench isolation structure. For example, trenches can be formed on the substrate first, and a sacrificial layer can be introduced to cover the trenches, followed by ion implantation to form the source / drain regions on the substrate. In addition, the mask material layer in the trench formation process can be a silicon dioxide layer, and may also include an amorphous carbon layer formed on the upper layer, in order to improve the etching selectivity during dry etching and remove the residual amorphous carbon layer after dry etching.

[0083] In one embodiment, the bottom of the gap is not lower than the top of the source / drain region. That is, the bottom of the gap is higher than or equal to the top of the source / drain region, and the gap does not extend into the substrate below the source / drain region. The substrate and the conductive layer are isolated by the dielectric layer, which, exemplarily, can be a silicon dioxide dielectric layer. In other embodiments of the invention, the gap may further extend into the substrate below the source / drain region, i.e., a portion of the area between the substrate and the conductive layer is isolated by the gap. The above distinctions determine the composition of the isolation dielectric in the gate-drain overlap region and part of the channel region of the transistor structure obtained by the present invention. The choice of isolation dielectric will have a significant impact on the gate-drain leakage current and switching characteristics of the transistor. In this embodiment, the isolation dielectric in the channel region will be entirely composed of a silicon dioxide gate dielectric layer, which ensures that the resulting device has good switching characteristics.

[0084] Figure 2 This is a flowchart illustrating step S104 in one embodiment, as follows: Figure 2 As shown, in one embodiment, the gap includes a first gap and a second gap, and step S104 includes:

[0085] S202, a dielectric layer and a first conductive layer are sequentially formed in the trench.

[0086] Specifically, a dielectric layer and a first conductive layer are sequentially formed in the trench. For example, the dielectric layer is made of at least one of silicon dioxide, silicon nitride, or silicon carbonitride. The first conductive layer is made of at least one of tungsten, polycrystalline silicon, or titanium nitride.

[0087] Figure 3 This is a flowchart illustrating step S202 in one embodiment. Figure 4 This is a schematic cross-sectional view of the semiconductor structure after the formation of the first conductive material layer in one embodiment. Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the first conductive layer in the first embodiment. Figure 6 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the first conductive layer in the second embodiment. Figure 7 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the first conductive layer in the third embodiment. Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the first conductive layer in the fourth embodiment. For example... Figure 3 , Figure 4 , Figure 5 As shown, in one embodiment, step S202 includes:

[0088] S302, a dielectric material layer is formed on the inner wall of the trench.

[0089] Specifically, firstly, a substrate 102 with trenches 104 is provided. In actual processes, the depth and feature size of the trenches 104 can be set as needed. For example, the depth of the trenches 104 can be 50nm-300nm, such as 50nm, 70nm, 90nm, 100nm, 150nm, 200nm, 250nm, and 300nm; the feature size of the trenches 104 can be 20nm-100nm, such as 0nm, 30nm, 50nm, 70nm, 90nm, and 100nm. Secondly, a dielectric material layer 106 is formed on the inner wall of the trenches 104, and the dielectric material layers 106 on opposite sidewalls of the trenches 104 are isolated from each other. In some embodiments, the dielectric material layer 106 extends along the sidewalls of the trenches 104 and covers the substrate 102. For example, the dielectric material layer 106 can be formed using an oxidation annealing process (ISSG), a thermal oxidation process, or a chemical vapor deposition process.

[0090] S304, a first conductive material layer is formed in the trench.

[0091] Specifically, a first conductive material layer 108 is formed in the trench 104 using film-forming processes well known to those skilled in the art, such as chemical vapor deposition, atomic layer deposition, and physical vapor deposition. The first conductive material layer 108 covers the dielectric material layer 106 and fills the trench 104. It is understood that in some embodiments, the upper surface of the first conductive material layer 108 is higher than the upper surface of the substrate 102.

[0092] S306, etching to form a dielectric layer and a first conductive layer.

[0093] The dielectric material layer 106 and the first conductive material layer 108 are etched to remove excess dielectric material layer 106 and excess first conductive material layer 108. The remaining dielectric material layer 106 is the dielectric layer 202, and the remaining first conductive material layer 108 is the first conductive layer 204. For example, a dry etching process or a wet etching process can be selected for etching.

[0094] like Figure 4 , Figure 5 As shown, in one embodiment, before step S304, a diffusion barrier material layer 110 is formed in the trench 104, the diffusion barrier material layer 110 being located between the first conductive material layer 108 and the dielectric material layer 106. Step S306 further includes etching the diffusion barrier material layer 110 to obtain a diffusion barrier layer 206, the upper surface of the diffusion barrier layer 206 being flush with the upper surface of the dielectric layer 202.

[0095] Specifically, after forming a dielectric material layer 106 on the inner wall of the trench 104, firstly, a diffusion barrier material layer 110 is formed on the dielectric material layer 106. The diffusion barrier material layer 110 does not fill the space between the dielectric material layers 106 formed on the sidewall of the trench 104. In some embodiments, the diffusion barrier material layer 110 is located on the upper surface of the dielectric material layer 106, that is, the diffusion barrier material layer 110 is in contact with the dielectric material layer 106. For example, the material of the diffusion barrier material layer 110 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride. In this case, the diffusion barrier material layer 110 can also serve as an adhesion layer between the first conductive material layer 108 and the dielectric material layer 106, thereby improving the bonding performance between the first conductive material layer 108 and the dielectric material layer 106 and preventing delamination and cracking. Secondly, a first conductive material layer 108 that fills the trench 104 is formed on the diffusion barrier material layer 110. Then, the excess dielectric material layer 106, excess diffusion barrier material layer 110, and excess first conductive material layer 108 are removed by dry etching and / or wet etching processes. The remaining dielectric material layer 106 is the dielectric layer 202, the remaining diffusion barrier material layer 110 is the diffusion barrier layer 206, and the remaining first conductive material layer 108 is the first conductive layer 204. In some embodiments, before etching the dielectric layer 202, diffusion barrier layer 206, and first conductive layer 204, the etching selectivity ratio of the dry etching of diffusion barrier material layer 110 and first conductive material layer 108 is adjusted to obtain a diffusion barrier layer 206 with an upper surface flush with the upper surface of dielectric layer 202, while obtaining a first conductive layer 204 with a different top shape.

[0096] In one embodiment, the top of the first conductive layer has a shape including Ω (as shown in the figure), a triangle (as shown in the figure), etc. Figure 6(as shown), trapezoidal (as shown) Figure 7 (as shown) and π (as shown) Figure 8 At least one of the following (shown), with the top of the first conductive layer having a shape of Ω as an example, is described below.

[0097] S204, a second conductive layer is formed on the upper surface of the first conductive layer.

[0098] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after the formation of the second conductive layer in one embodiment. Figure 10 for Figure 9 A cross-sectional schematic diagram of the semiconductor structure after the first gap is formed in one corresponding embodiment; Figure 11 for Figure 10 A cross-sectional view of the semiconductor structure after the second gap is formed in one corresponding embodiment. Figure 12 This is a flowchart illustrating step S204 in one embodiment. Figure 13 for Figure 11 A cross-sectional schematic diagram of the semiconductor structure after the isolation layer is formed in one corresponding embodiment. For example... Figure 9 As shown, a second conductive layer 208 is formed on the upper surface of the first conductive layer 204. A first gap 210 is formed between the second conductive layer 208 and the sidewall of the trench 104, and a second gap 212 is formed between the first conductive layer 204 and the sidewall of the trench 104.

[0099] In one embodiment, in a direction perpendicular to the substrate surface, the projected area of ​​the first gap 210 in the groove 102 is smaller than the projected area of ​​the second gap 212 in the groove 102, that is, the projected area of ​​the orthographic projection of the first gap 210 in the groove 102 is smaller than the projected area of ​​the orthographic projection of the second gap 212 in the groove 102.

[0100] like Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 As shown, in one embodiment, step S204 includes:

[0101] S402, a first sacrificial layer is formed on the sidewall of the trench.

[0102] A first sacrificial layer 112 is formed on the sidewall of trench 104, and the first sacrificial layer 112 is located above the dielectric layer 202. A gap 114 exists between the first sacrificial layers 112 on opposite sidewalls of trench 104. Exemplarily, the material of the first sacrificial layer 112 includes nitrides and oxides, such as silicon dioxide or silicon nitride. In one embodiment, the material of the first sacrificial layer 112 includes silicon dioxide, and the material of the first sacrificial layer 112 can be formed using thermal oxidation, chemical vapor deposition, or atomic layer deposition processes. The gap 114 between the first sacrificial layers 112 on opposite sidewalls of trench 104 can be obtained by photolithography or etching processes. In some embodiments, the distance between the side of the first sacrificial layer 112 away from trench 104 and the sidewall of trench 104 is 0.5 nm to 2 nm, for example, 0.5 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.0 nm, 1.5 nm, 1.7 nm, 2.0 nm, etc.

[0103] In one embodiment, before step S402, a second sacrificial layer 116 is formed on the upper surface of the dielectric layer 202, the second sacrificial layer 116 surrounds the first conductive layer 204, and the top of the second sacrificial layer 116 exposes the first conductive layer 204; wherein the bottom of the first sacrificial layer 112 is flush with the top of the second sacrificial layer 116.

[0104] In one embodiment, the material of the second sacrificial layer 116 includes nitrides and oxides, such as silicon dioxide and silicon nitride. In some embodiments, the second sacrificial layer 116 and the first sacrificial layer 112 are made of the same material. In this case, the first sacrificial layer 112 and the second sacrificial layer 116 can be removed by two separate etching processes, thereby achieving complete removal of the first sacrificial layer 112 and the second sacrificial layer 116. Alternatively, the first sacrificial layer 112 and the second sacrificial layer 116 can be removed by a single etching process, thereby simplifying the semiconductor structure manufacturing process. In other embodiments, the second sacrificial layer 116 and the first sacrificial layer 112 are made of different materials. In this case, the first sacrificial layer 112 and the second sacrificial layer 116 can be removed by two separate etching processes. In this case, different etching steps can be used to remove the first sacrificial layer 112 and the second sacrificial layer 116, thereby achieving complete removal of the first sacrificial layer 112 and the second sacrificial layer 116.

[0105] S404, a second conductive layer is formed between the first sacrificial layers.

[0106] A second conductive layer 208 is formed in the gap 114, the second conductive layer 208 fills the gap 114, and the second conductive layer 208 is in contact with the first conductive layer 204.

[0107] In some embodiments, the second conductive layer 208 is formed using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. For example, the material of the second conductive layer 208 includes doped polysilicon. In some embodiments, the doped polysilicon is formed by deposition-doping.

[0108] S406, Remove the first sacrificial layer to form the first void.

[0109] The first sacrificial layer 112 on the sidewall of the trench 104 is removed by a dry etching process or a wet etching process to obtain the first void 210.

[0110] In one embodiment, step S106 further includes removing the second sacrificial layer 116 to form the second void 212. Specifically, as shown... Figure 10 , Figure 11 As shown, after the first sacrificial layer 112 is removed by a wet etching process or a dry etching process, a first void 210 is formed, exposing a portion of the surface of the second sacrificial layer 116. The second sacrificial layer 116, located on the dielectric layer 202 and the diffusion barrier layer 206, is then removed by a dry etching process or a wet etching process to form a second void 212 located between the first conductive layer 204 and the sidewall of the trench 104. For example, when the material of the first sacrificial layer 112 is silicon dioxide and the material of the second sacrificial layer 116 is silicon nitride, the first sacrificial layer 112 is first completely removed by a dry etching process or a wet etching process, and then the second sacrificial layer 116 is removed by a wet etching process using an etching solution including hot phosphoric acid. Then, an isolation layer 216 is formed on the second conductive layer 208. It is understood that when the isolation layer 216 is located on the second conductive layer 208, the lower surface of the isolation layer 216 can be flush with the upper surface of the second conductive layer 208.

[0111] In one embodiment, the top of the isolation layer 216 is flush with the top of the trench 104. Exemplarily, the material of the isolation layer 216 includes nitrides and oxides, such as silicon dioxide or silicon nitride. The isolation layer 216 is formed using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. It is understood that, in order to obtain a smooth-surfaced isolation layer 216, a chemical mechanical polishing process is used after deposition to obtain a smooth-surfaced isolation layer 216. When a dielectric material layer 106 remains on the substrate 102, the dielectric material layer 106 on the substrate 102 is removed while the dielectric material layer 106 is being removed during the chemical mechanical polishing process to obtain a smooth-surfaced isolation layer 216.

[0112] In one embodiment, the top of the conductive layer is lower than the top of the trench 102.

[0113] In one embodiment, the projected area of ​​the top of the second conductive layer 208 in the trench 102 is equal to the projected area of ​​the bottom of the second conductive layer 208 in the trench 102.

[0114] It should be understood that, although Figure 1 , Figure 2 , Figure 3 , Figure 12 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 2 , Figure 3 , Figure 12 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0115] like Figure 4 , Figure 13 As shown, this application also provides a semiconductor structure, including: a substrate 102, a conductive layer, a dielectric layer 202, an isolation layer 216, and a void 214. A trench 104 is formed in the substrate 102; the conductive layer is located within the trench 104, and the conductive layer includes a first conductive layer 204 and a second conductive layer 208, the second conductive layer 208 being located on the first conductive layer 204, and the projected area of ​​the bottom of the second conductive layer 208 within the trench 104 being greater than the projected area of ​​the top of the first conductive layer 204 within the trench 104; the dielectric layer 202 is located between the conductive layer and the inner wall of the trench 104, and the top of the dielectric layer 202 is lower than the top of the first conductive layer 204; the isolation layer 216 is located on the conductive layer; the void 214 is formed by the isolation layer 216, the conductive layer, the dielectric layer, and the sidewall of the trench 104; wherein the work function of the first conductive layer 204 is greater than the work function of the second conductive layer 208.

[0116] Specifically, the substrate 102 can be made of undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in this embodiment, the substrate 102 is made of single-crystal silicon. A dielectric layer 202 covers a portion of the sidewalls near the bottom of the trench 104 and the bottom of the trench 104, and a conductive layer is filled between the dielectric layers 202 on the sidewalls, with the upper surface of the conductive layer higher than the upper surface of the dielectric layers 202. From the bottom of the trench 104 toward the opening of the trench 104, the conductive layer includes a first conductive layer 204 near the bottom of the trench 104 and a second conductive layer 208 near the top of the trench 104. The first conductive layer 204 and the second conductive layer 208 are electrically connected. The area of ​​the bottom of the second conductive layer 208 projected orthographically within the trench 104 is larger than the area of ​​the top of the first conductive layer 204 projected orthographically within the trench 104; that is, in a direction parallel to the upper surface of the substrate 102, the cross-sectional area of ​​the bottom of the second conductive layer 208 is larger than the cross-sectional area of ​​the top of the first conductive layer 204. For those skilled in the art, when the semiconductor structure includes a memory device, the conductive layer serves as the gate of a memory transistor, and simultaneously, the conductive layer can serve as the word line structure of the memory device. Understandably, the sidewalls of the second conductive layer 208 are isolated from the sidewalls of the trench. The isolation layer 216 is located on the conductive layer and is in contact with the sidewalls of the trench 104. At this time, the unfilled portion of the space enclosed by the isolation layer 216, the conductive layer, the dielectric layer 202, and the sidewalls of the trench 102 forms a void 214. This void 214, together with the dielectric layer 202, serves as the gate dielectric layer of the storage transistor, reducing the gate-drain voltage and effectively suppressing the gate-drain leakage current, thereby improving the reliability of the semiconductor structure and reducing its power consumption. When the semiconductor structure is a memory device, this improves the data storage and read / write performance of the memory device.

[0117] The aforementioned semiconductor structure includes: a substrate in which trenches are formed; a conductive layer located within the trenches, the conductive layer comprising a first conductive layer and a second conductive layer, the second conductive layer being located on top of the first conductive layer, and the projected area of ​​the bottom of the second conductive layer within the trench being larger than the projected area of ​​the top of the first conductive layer within the trench; a dielectric layer located between the conductive layer and the inner wall of the trench, and the top of the dielectric layer being lower than the top of the first conductive layer; an isolation layer located on the conductive layer; and a gap formed by the isolation layer, the conductive layer, the dielectric layer, and the sidewalls of the trench; wherein the work function of the first conductive layer is greater than the work function of the second conductive layer. In this application, the conductive layer serving as the gate structure includes a first conductive layer and a second conductive layer, and the work function of the first conductive layer is greater than the work function of the second conductive layer. This configuration improves the turn-on speed of the storage transistor, reduces the gate-drain leakage current of the semiconductor structure, improves the reliability of the semiconductor structure, and reduces the power consumption of the semiconductor structure, thereby enhancing the data storage and read / write performance of the semiconductor structure. Meanwhile, the gate dielectric layer of the storage transistor in this application is composed of gaps and dielectric layers, which reduces the gate-drain voltage and suppresses the gate-drain leakage current, thereby further improving the reliability of the semiconductor structure and reducing the power consumption of the semiconductor structure. At the same time, the data storage and read / write performance of the semiconductor structure is further improved.

[0118] In one embodiment, a shallow trench isolation structure is formed in the substrate 102, which isolates a plurality of spaced active regions in the substrate 102. The trench 104 is formed in the active regions, and active electrode / drain electrode regions are formed on opposite sides of the trench 104, respectively.

[0119] In one embodiment, the bottom of the gap 214 is not lower than the top of the source / drain region. That is, the bottom of the gap 214 is higher than or equal to the top of the source / drain region, and the gap 214 does not extend into the substrate below the source / drain region. The substrate 102 and the conductive layer are isolated by a dielectric layer 202, which, exemplarily, can be a silicon dioxide dielectric layer. In other embodiments of the invention, the gap 214 may further extend into the substrate 102 below the source / drain region, i.e., a portion of the area between the substrate 102 and the conductive layer is isolated by the gap 214. The above distinctions determine the composition of the isolation dielectric in the gate-drain overlap region and part of the channel region of the transistor structure obtained by the present invention. The choice of isolation dielectric will have a significant impact on the gate-drain leakage current and switching characteristics of the transistor. In this embodiment, the isolation dielectric in the channel region will be entirely composed of a silicon dioxide gate dielectric layer, which ensures that the obtained device has good switching characteristics.

[0120] In one embodiment, the top of the first conductive layer has a shape including Ω (as shown in the figure), a triangle (as shown in the figure), etc. Figure 6 (as shown), trapezoidal (as shown) Figure 7 (as shown) and π (as shown) Figure 8 At least one of the following (shown), with the top of the first conductive layer having a shape of Ω as an example, is described below.

[0121] In one embodiment, the void 214 includes a first void 210 and a second void 212, the first void 210 being located between the second conductive layer 208 and the sidewall of the trench 102, and the second void 212 being located between the first conductive layer 204 and the sidewall of the trench 102. Exemplarily, the dielectric layer 202 is made of silicon dioxide. The first conductive layer 204 is made of tungsten.

[0122] In actual processes, the depth and feature size of the trench 104 can be set as needed. For example, the depth of the trench 104 can be 50nm-300nm, such as 50nm, 70nm, 90nm, 100nm, 150nm, 200nm, 250nm, and 300nm; the feature size of the trench 104 can be 20nm-100nm, such as 0nm, 30nm, 50nm, 70nm, 90nm, and 100nm.

[0123] In one embodiment, the semiconductor structure further includes a diffusion barrier layer 206, which is located between the conductive layer and the dielectric layer 202, and the upper surface of the diffusion barrier layer 206 is flush with the upper surface of the dielectric layer 202. In some embodiments, the diffusion barrier layer 206 conforms to the dielectric layer 202, that is, the diffusion barrier layer 206 is in contact with the dielectric layer 202. For example, the material of the diffusion barrier layer 206 includes at least one of titanium metal and titanium nitride. In this case, the diffusion barrier layer 206 can also serve as an adhesion layer between the first conductive layer 204 and the dielectric layer 202, thereby improving the bonding performance between the first conductive layer 204 and the dielectric layer 202 and preventing delamination and cracking.

[0124] In one embodiment, in a direction perpendicular to the substrate surface, the projected area of ​​the first gap 210 in the groove 102 is smaller than the projected area of ​​the second gap 212 in the groove 102, that is, the projected area of ​​the orthographic projection of the first gap 210 in the groove 102 is smaller than the projected area of ​​the orthographic projection of the second gap 212 in the groove 102.

[0125] In one embodiment, the material of the second conductive layer 208 comprises doped polycrystalline silicon.

[0126] In one embodiment, the isolation layer 216 is located on the upper surface of the second conductive layer 208, and the lower surface of the isolation layer 216 is flush with the upper surface of the second conductive layer 208.

[0127] In one embodiment, the top of the isolation layer 216 is flush with the top of the trench 102. Exemplarily, the material of the isolation layer 216 includes nitrides and oxides, such as silicon dioxide and silicon nitride.

[0128] In one embodiment, the top of the conductive layer is lower than the top of the trench 102. Exemplarily, the conductive layer includes a first conductive layer 204 and a second conductive layer 208, the top of the second conductive layer 208 being lower than the top of the trench 102.

[0129] In one embodiment, the projected area of ​​the top of the second conductive layer 208 in the trench 102 is equal to the projected area of ​​the bottom of the second conductive layer 208 in the trench 102.

[0130] In one embodiment, the semiconductor structure includes dynamic random access memory.

[0131] This application also provides an electronic device comprising the semiconductor structure described in any of the preceding claims.

[0132] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above-described embodiments are merely illustrative of several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided in which trenches are formed; A dielectric layer and a conductive layer are sequentially formed in the trench; The dielectric layer is located between the conductive layer and the inner wall of the trench; the conductive layer includes a first conductive layer and a second conductive layer located on the first conductive layer, the top of the dielectric layer is lower than the top of the first conductive layer, the bottom of the second conductive layer has a projected area in the trench that is greater than the top of the first conductive layer in the trench, and the work function of the first conductive layer is greater than the work function of the second conductive layer. An isolation layer is formed on the conductive layer, and the isolation layer, the conductive layer, and the sidewalls of the trench form a void; The voids include a first void and a second void, and the formation of a dielectric layer and a conductive layer sequentially in the trench includes: The dielectric layer and the first conductive layer are sequentially formed in the trench; A second sacrificial layer is formed on the upper surface of the dielectric layer, the second sacrificial layer surrounds the first conductive layer, and the top of the second sacrificial layer exposes the first conductive layer; A first sacrificial layer is formed on the sidewall of the trench, the first sacrificial layer is located above the medium layer, the bottom of the first sacrificial layer is flush with the top of the second sacrificial layer, and there is a gap between the first sacrificial layers on opposite sidewalls of the trench; A second conductive layer is formed in the gap, the second conductive layer fills the gap, and the second conductive layer is in contact with the first conductive layer; The first sacrificial layer is removed to form the first void, and the second conductive layer has the first void between it and the sidewall of the trench; The second sacrificial layer is removed to form the second void, and the second void is present between the first conductive layer and the sidewall of the trench.

2. The preparation method according to claim 1, characterized in that, A shallow trench isolation structure is formed in the substrate, which isolates a plurality of spaced active regions within the substrate. The trenches are formed in the active regions, and active / drain regions are formed on opposite sides of the trenches, respectively.

3. The preparation method according to claim 2, characterized in that, The bottom of the gap is not lower than the top of the source / drain region.

4. The preparation method according to claim 1, characterized in that, The top of the isolation layer is flush with the top of the trench.

5. The preparation method according to claim 1, characterized in that, The step of sequentially forming the dielectric layer and the first conductive layer in the trench includes: A dielectric material layer is formed on the inner wall of the trench; A first conductive material layer is formed in the trench, the first conductive material layer covers the dielectric material layer, and fills the trench; The dielectric material layer and the first conductive material layer are etched to form the dielectric layer and the first conductive layer.

6. The preparation method according to claim 5, characterized in that, Before forming the first conductive material layer in the trench, the process includes: A diffusion barrier material layer is formed in the trench, and the diffusion barrier material layer is located between the first conductive material layer and the dielectric material layer; The etching of the dielectric material layer and the first conductive material layer further includes: The diffusion barrier material layer is etched to obtain a diffusion barrier layer, the upper surface of which is flush with the upper surface of the dielectric layer.

7. The preparation method according to claim 5, characterized in that, The top of the first conductive layer has a shape including at least one of Ω, triangle, trapezoid and π.

8. A semiconductor structure, characterized in that, The semiconductor structure is manufactured using the preparation method according to any one of claims 1-7, and comprises: A substrate in which grooves are formed; A conductive layer is located in the trench. The conductive layer includes a first conductive layer and a second conductive layer. The second conductive layer is located on the first conductive layer, and the projected area of ​​the bottom of the second conductive layer in the trench is greater than the projected area of ​​the top of the first conductive layer in the trench. A dielectric layer is located between the conductive layer and the inner wall of the trench, and the top of the dielectric layer is lower than the top of the first conductive layer; An isolation layer is located on the conductive layer; The gap is formed by the isolation layer, the conductive layer, the dielectric layer, and the sidewalls of the trench; The work function of the first conductive layer is greater than that of the second conductive layer.

9. The semiconductor structure according to claim 8, characterized in that, The top of the first conductive layer has a shape including at least one of Ω, triangle, trapezoid and π.

10. The semiconductor structure according to claim 8, characterized in that, A shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates a plurality of spaced active regions in the substrate. The trench is formed in the active regions, and active electrode / drain electrode regions are formed on opposite sides of the trench, respectively. Wherein, the bottom of the gap is not lower than the top of the source / drain region.

11. The semiconductor structure according to claim 8, characterized in that, The gap includes a first gap and a second gap, wherein the first gap is located between the second conductive layer and the sidewall of the trench, and the second gap is located between the first conductive layer and the sidewall of the trench.

12. The semiconductor structure according to claim 11, characterized in that, In a direction perpendicular to the surface of the substrate, the projected area of ​​the first void in the trench is smaller than the projected area of ​​the second void in the trench.

13. The semiconductor structure according to claim 8, characterized in that, The top of the isolation layer is flush with the top of the trench.

14. The semiconductor structure according to claim 8, characterized in that, The top of the conductive layer is lower than the top of the trench.

15. The semiconductor structure according to claim 8, characterized in that, The projected area of ​​the top of the second conductive layer in the trench is equal to the projected area of ​​the bottom of the second conductive layer in the trench.

16. The semiconductor structure according to claim 8, characterized in that, Also includes: A diffusion barrier layer is located between the conductive layer and the dielectric layer, and the upper surface of the diffusion barrier layer is flush with the upper surface of the dielectric layer.

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