Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a semiconductor substrate; a plurality of stack structures and a plurality of isolation structures on the semiconductor substrate, the stack structures are distributed at intervals, the isolation structures are located between adjacent stack structures, the stack structure comprises, from bottom to top: a nucleation layer and a first epitaxial layer; and a heterojunction structure on the plurality of stack structures, the heterojunction structure is distributed on the whole surface, and an air gap is formed between the heterojunction structure and the isolation structure. The stack structures are separated by the isolation structures, on the one hand, the stack structures can be thick, the distance between the interface of the heterojunction structure and the conductive layer of the substrate is increased, which is beneficial to reducing the leakage of the semiconductor substrate, and the parasitic capacitance can also be reduced, thereby reducing the radio frequency loss; on the other hand, after the stack structure is thickened, the separated stack structures can weaken the stress accumulation, so that cracking does not occur.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As a typical representative of third-generation semiconductor materials, group III nitrides, with their wide bandgap semiconductors, have excellent properties such as large bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructures. They are very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.

[0003] For example, AlGaN / GaN heterojunctions have strong spontaneous polarization and piezoelectric polarization, resulting in a high concentration of two-dimensional electron gas (2DEG) at the AlGaN / GaN interface. They are widely used in semiconductor structures such as high electron mobility transistors (HEMTs).

[0004] At the interface between a semiconductor substrate, such as a silicon substrate and a GaN epitaxial layer, the resistance is very low due to diffusion, resulting in a conductive layer. This conductive layer causes leakage current in the device, and for radio frequency devices, it also causes radio frequency loss, degrading device performance. Therefore, it is necessary to provide a new semiconductor structure and its fabrication method to solve the aforementioned technical problems. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor structure and its fabrication method to improve the leakage current problem of semiconductor substrates.

[0006] To achieve the above objectives, a first aspect of the present invention provides a semiconductor structure comprising:

[0007] Semiconductor substrate;

[0008] A plurality of stacked structures and a plurality of isolation structures are located on the semiconductor substrate, the stacked structures being spaced apart, and the isolation structures being located between adjacent stacked structures; the stacked structures, from bottom to top, include: a nucleation layer and a first epitaxial layer; and

[0009] The heterojunction structure is located on the plurality of stacked structures, the heterojunction structure is distributed across the entire surface, and an air gap is formed between the heterojunction structure and the isolation structure.

[0010] Optionally, the stacked structure further includes a buffer layer located between the nucleation layer and the first epitaxial layer.

[0011] Optionally, the heterojunction structure includes, from bottom to top, a channel layer and a barrier layer, wherein the first epitaxial layer is made of the same material as the channel layer;

[0012] Alternatively, the heterojunction structure may include, from bottom to top, a back barrier layer and a channel layer, wherein the first epitaxial layer is made of the same material as the back barrier layer.

[0013] Optionally, the semiconductor substrate is made of sapphire, silicon carbide, silicon, or diamond, and the isolation structure is made of at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, magnesium oxide, titanium oxide, and gallium oxide.

[0014] Optionally, the material of the nucleation layer is AlN or AlGaN, and the materials of the first epitaxial layer and the heterojunction structure are at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN.

[0015] Optionally, the heterojunction structure includes: a source region and a drain region, and a gate region located between the source region and the drain region; the source region has a source, the drain region has a drain, and the gate region has a P-type semiconductor layer and a gate in sequence.

[0016] Another aspect of the present invention provides a method for fabricating a semiconductor structure, comprising:

[0017] A semiconductor substrate is provided, on which a plurality of stacked structures and a plurality of isolation structures are formed, the stacked structures being spaced apart, and the isolation structures being located between adjacent stacked structures; the stacked structure includes, from bottom to top, a nucleation layer and a first epitaxial layer.

[0018] Heterojunction structures are epitaxially grown on the plurality of stacked structures, and the heterojunction structures on adjacent stacked structures are healed to form a full-surface distribution, with an air gap formed between the heterojunction structures and the isolation structure.

[0019] Optionally, forming a plurality of stacked structures and a plurality of isolation structures on the semiconductor substrate includes:

[0020] An isolation structure is formed on the semiconductor substrate at intervals. Using the isolation structure as a mask, a core layer and a first epitaxial layer are sequentially grown on the semiconductor substrate to form the plurality of stacked structures.

[0021] Optionally, forming a plurality of stacked structures and a plurality of isolation structures on the semiconductor substrate includes:

[0022] A core layer and a first epitaxial layer are sequentially grown on the semiconductor substrate;

[0023] The nucleation layer and the first epitaxial layer in a certain area are removed to expose the semiconductor substrate, and the remaining nucleation layer and the first epitaxial layer are spaced apart to form the plurality of stacked structures;

[0024] An isolation structure is formed on the exposed semiconductor substrate.

[0025] Optionally, a buffer layer is grown on the nucleation layer before the first epitaxial layer is grown.

[0026] Optionally, the semiconductor substrate is made of sapphire, silicon carbide, silicon, or diamond, and the isolation structure is made of at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, magnesium oxide, titanium oxide, and gallium oxide. The method for forming the isolation structure includes:

[0027] The insulating material layer is formed using physical vapor deposition or chemical vapor deposition.

[0028] The insulating material layer is graphically represented to form an isolation structure;

[0029] Or include:

[0030] Multiple grooves are formed within the semiconductor substrate, and an insulating material layer is filled within the grooves to form the isolation structure.

[0031] Optionally, the semiconductor substrate is made of silicon, the isolation structure is made of silicon dioxide, and the isolation structure is formed by local thermal oxidation.

[0032] Optionally, the heterojunction structure includes, from bottom to top, a channel layer and a barrier layer, wherein the first epitaxial layer is made of the same material as the channel layer;

[0033] Alternatively, the heterojunction structure may include, from bottom to top, a back barrier layer and a channel layer, wherein the first epitaxial layer is made of the same material as the back barrier layer.

[0034] Optionally, the heterojunction structure includes: a source region and a drain region, and a gate region located between the source region and the drain region; the fabrication method further includes:

[0035] A source is formed on the source region, a drain is formed on the drain region, and a P-type semiconductor layer and a gate are sequentially formed on the gate region.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] 1) Using isolation structures to separate the stacked structures has several advantages. First, the stacked structure can be made thicker, increasing the distance between the heterojunction interface and the substrate conductive layer, reducing parasitic capacitance, thereby reducing RF loss and leakage current caused by the substrate conductive layer. Second, with a thicker stacked structure, the thermal expansion coefficients of the stacked structure and the semiconductor substrate differ. The thicker the stacked structure, the more likely the stress accumulation will cause cracking of the entire stacked structure. The isolated stacked structure reduces stress accumulation and therefore does not crack. In addition, the isolation structure and air gap (AR) can also reduce leakage current from the heterojunction interface to the semiconductor substrate.

[0038] 2) In the optional scheme, forming multiple stacked structures and multiple isolation structures on the semiconductor substrate includes: a) forming spaced-apart isolation structures on the semiconductor substrate, using the isolation structures as masks to sequentially grow a nucleation layer and a first epitaxial layer on the semiconductor substrate to form multiple stacked structures; or b) sequentially growing a nucleation layer and a first epitaxial layer on the semiconductor substrate; removing a portion of the nucleation layer and the first epitaxial layer to expose the semiconductor substrate, leaving the remaining nucleation layer and the first epitaxial layer spaced apart to form multiple stacked structures; and forming isolation structures on the exposed semiconductor substrate. Compared to scheme b), the advantage of scheme a) is that the substrate conductive layer formed between the stacked structures and the semiconductor substrate is also isolated, which helps to further reduce substrate leakage current. Attached Figure Description

[0039] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention;

[0040] Figure 2 and Figure 3 yes Figure 1 A schematic diagram of the intermediate structure corresponding to the process in the document;

[0041] Figure 4 This is a schematic cross-sectional view of the semiconductor structure according to the first embodiment of the present invention;

[0042] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure according to the second embodiment of the present invention;

[0043] Figure 6 and Figure 7 Is making Figure 5 A schematic diagram of the intermediate structure corresponding to the semiconductor structure process in the diagram;

[0044] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure according to the third embodiment of the present invention;

[0045] Figure 9This is a cross-sectional schematic diagram of the semiconductor structure according to the fourth embodiment of the present invention;

[0046] Figure 10 This is a cross-sectional schematic diagram of the semiconductor structure according to the fifth embodiment of the present invention;

[0047] Figure 11 This is a cross-sectional schematic diagram of the semiconductor structure according to the sixth embodiment of the present invention.

[0048] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below:

[0049] Detailed Implementation

[0050] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0051] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention. Figure 2 and Figure 3 yes Figure 1 The diagram shows the intermediate structure corresponding to the process flow. Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure according to the first embodiment of the present invention.

[0052] First, refer to Figure 1 Step S1 in Figure 2 and Figure 3 As shown, a semiconductor substrate 10 is provided, on which a plurality of stacked structures 11 and a plurality of isolation structures 12 are formed respectively. The stacked structures 11 are spaced apart, and the isolation structures 12 are located between adjacent stacked structures 11. The stacked structure 11 includes, from bottom to top: a nucleation layer 111, a buffer layer 112 and a first epitaxial layer 113.

[0053] In this embodiment, forming a plurality of stacked structures 11 and a plurality of isolation structures 12 on the semiconductor substrate 10 may specifically include the following steps:

[0054] Step S11: Refer to Figure 2 As shown, a core layer 111, a buffer layer 112, and a first epitaxial layer 113 are sequentially grown on a semiconductor substrate 10.

[0055] Step S12: Refer to Figure 3 As shown, a portion of the nucleation layer 111, buffer layer 112, and first epitaxial layer 113 are removed to expose the semiconductor substrate 10, while the remaining nucleation layer 111, buffer layer 112, and first epitaxial layer 113 are spaced apart to form multiple stacked structures 11.

[0056] Step S13: Continue to refer to Figure 3 As shown, an isolation structure 12 is formed on the exposed semiconductor substrate 10.

[0057] In step S11, the semiconductor substrate 10 can be made of materials such as sapphire, silicon carbide, silicon, or diamond.

[0058] The nucleation layer 111 is made of a group III nitride-based material, such as AlN or AlGaN. The buffer layer 112 is also made of a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. The nucleation layer 111 can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the first epitaxial layer 113, and the semiconductor substrate 10. The buffer layer 112 can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0059] The material of the first epitaxial layer 113 can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN.

[0060] The formation process of nucleation layer 111, and / or buffer layer 112, and / or first epitaxial layer 113 may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0061] A substrate conductive layer 20 will diffuse to form at the interface between the semiconductor substrate 10 and the group III nitride-based material. For example, silicon atoms in the silicon substrate 10 will diffuse into the group III nitride-based material, and group III atoms in the group III nitride-based material will diffuse into the silicon substrate 10, resulting in the formation of a substrate conductive layer 20 at the interface between the silicon substrate 10 and the group III nitride-based material.

[0062] In step S12, the removal of the nucleation layer 111, buffer layer 112 and first epitaxial layer 113 in a certain area can be done by dry etching or wet etching.

[0063] Dry etching can be inductively coupled plasma etching (ICP). Etching gases can include Cl2 and BCl3.

[0064] The etching solution used in wet etching can be H3PO4 solution or KOH solution, which is corrosive to the N-plane. The GaN crystal has a wurtzite structure, in which the Ga and N atomic layers are stacked in an ABABAB hexagonal layer, and each Ga(N) atom is bonded to the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure. Taking the Ga-N bond parallel to the C-axis (

[0001] crystal direction) as a reference, if the Ga atom in each Ga-N bond is further away from the lower surface, the upper surface is the Ga plane; if the N atom in each Ga-N bond is further away from the lower surface, the upper surface is the N plane. In this embodiment, the upper surfaces of the nucleation layer 111, the buffer layer 112, and the first epitaxial layer 113 can be controlled to be N planes.

[0065] In step S13, the semiconductor substrate 10 can be made of silicon, and the isolation structure 12 can be made of silicon dioxide. The isolation structure 12 is formed using localized thermal oxidation (LOCOS). In other embodiments, the isolation structure 12 can also be made of at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, magnesium oxide, titanium oxide, and gallium oxide, and can be formed using dry etching or wet etching.

[0066] Next, refer to Figure 1 Step S2 and Figure 4 As shown, heterojunction structures 13 are epitaxially grown on multiple stacked structures 11, and the heterojunction structures 13 on adjacent stacked structures 11 are fused together to form a full-surface distribution, and an air gap 14 is formed between the heterojunction structures 13 and the isolation structure 12.

[0067] In this embodiment, the heterojunction structure 13 may include a channel layer 131 and a barrier layer 132 from bottom to top. A two-dimensional electron gas or a two-dimensional hole gas may be formed at the interface between the channel layer 131 and the barrier layer 132. In one optional embodiment, the channel layer 131 is an intrinsic GaN layer, and the barrier layer 132 is an N-type AlGaN layer. In other optional embodiments, the materials of the channel layer 131 and the barrier layer 132 may also be at least one selected from GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. In addition, besides Figure 4 The channel layer 131 and barrier layer 132 shown each have one layer; the channel layer 131 and barrier layer 132 may also have multiple layers, which are alternately distributed; or one channel layer 131 and two or more barrier layers 132 to form a multi-barrier structure.

[0068] The formation process of the heterojunction structure 13 can refer to the formation process of the nucleation layer 111, and / or the buffer layer 112, and / or the first epitaxial layer 113.

[0069] In this embodiment, the channel layer 131 is obtained by epitaxial growth of the first epitaxial layer 113. Therefore, in order to reduce the dislocation density and defect density of the channel layer 131, the channel layer 131 is preferably made of the same material as the first epitaxial layer 113.

[0070] In some embodiments, during the epitaxial growth process, the channel layer 131 may also be made of a different material than the first epitaxial layer 113, depending on the requirements.

[0071] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure according to the first embodiment of the present invention.

[0072] Reference Figure 4 As shown, the semiconductor structure 1 in this embodiment includes:

[0073] Semiconductor substrate 10;

[0074] Multiple stacked structures 11 and multiple isolation structures 12 are located on a semiconductor substrate 10, with the stacked structures 11 spaced apart and the isolation structures 12 located between adjacent stacked structures 11; each stacked structure 11 includes, from bottom to top: a nucleation layer 111, a buffer layer 112, and a first epitaxial layer 113; and

[0075] The heterojunction structure 13 is located on multiple stacked structures 11. The heterojunction structure 13 is distributed across the entire surface, and an air gap 14 is formed between the heterojunction structure 13 and the isolation structure 12.

[0076] The semiconductor substrate 10 can be made of sapphire, silicon carbide, silicon or diamond.

[0077] The nucleation layer 111 is made of a group III nitride-based material, such as AlN or AlGaN. The buffer layer 112 is also made of a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. The nucleation layer 111 can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the first epitaxial layer 113, and the semiconductor substrate 10. The buffer layer 112 can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0078] The material of the first epitaxial layer 113 can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN.

[0079] The material of the isolation structure 12 may also be at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, magnesium oxide, titanium oxide, and gallium oxide.

[0080] In this embodiment, the heterojunction structure 13 may include a channel layer 131 and a barrier layer 132 from bottom to top. A two-dimensional electron gas or a two-dimensional hole gas may be formed at the interface between the channel layer 131 and the barrier layer 132. In one optional embodiment, the channel layer 131 is an intrinsic GaN layer, and the barrier layer 132 is an N-type AlGaN layer. In other optional embodiments, the materials of the channel layer 131 and the barrier layer 132 may also be at least one selected from GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. In addition, besides Figure 4 The channel layer 131 and barrier layer 132 shown each have one layer; the channel layer 131 and barrier layer 132 may also have multiple layers, which are alternately distributed; or one channel layer 131 and two or more barrier layers 132 to form a multi-barrier structure.

[0081] A conductive substrate layer 20 is formed by interdiffusion at the interface between the semiconductor substrate 10 and the group III nitride-based material. When the channel of the semiconductor structure 1 is turned on, the low resistance of the conductive substrate layer 20 causes leakage from the group III nitride-based material to the semiconductor substrate 10. In the semiconductor structure 1 of this embodiment, the stacked structure 11 is separated by an isolation structure 12. On the one hand, the stacked structure 11 can be made thicker, increasing the distance between the interface of the heterojunction structure 13 and the conductive substrate layer 20, which helps to reduce leakage from the interface of the heterojunction structure 13 to the semiconductor substrate 10, thereby reducing radio frequency loss. On the other hand, when the stacked structure 11 is made thicker, the thermal expansion coefficients of the entire stacked structure and the semiconductor substrate 10 are different. The thicker the stacked structure 11, the more likely the stress accumulation will cause cracking of the entire stacked structure 11. The isolated stacked structure 11 reduces stress accumulation and therefore does not crack.

[0082] In addition, the isolation structure 12 and the air gap 14 (AR) can also reduce leakage current from the interface of the heterojunction structure 13 to the semiconductor substrate 10.

[0083] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure according to the second embodiment of the present invention. Figure 6 and Figure 7 Is making Figure 5 The schematic diagram of the intermediate structure corresponding to the semiconductor structure process.

[0084] Reference Figure 5 As shown, the semiconductor structure 2 of Embodiment 2 is largely the same as the semiconductor structure 1 of Embodiment 1, except that the substrate conductive layer 20 is located only between the stacked structure 11 and the semiconductor substrate 10.

[0085] Accordingly, the method for fabricating the semiconductor structure in Embodiment 2 is largely the same as that in Embodiment 1, except that: in step S1, forming multiple stacked structures 11 and multiple isolation structures 12 on the semiconductor substrate 10 may specifically include:

[0086] Step S11': Refer to Figure 6 As shown, spaced isolation structures 12 are formed on the semiconductor substrate 10;

[0087] Step S12': Refer to Figure 7 As shown, using the isolation structure 12 as a mask, a core layer 111, a buffer layer 112 and a first epitaxial layer 113 are sequentially grown on the semiconductor substrate 10 to form multiple stacked structures 11.

[0088] In step S11', the material of the isolation structure 12 can be at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, magnesium oxide, titanium oxide, and gallium oxide. A method for forming the isolation structure 12 may include:

[0089] The insulating material layer is formed using physical vapor deposition or chemical vapor deposition.

[0090] A patterned insulating material layer forms an isolation structure 12.

[0091] The patterned insulating material layer is achieved using dry etching or wet etching.

[0092] Another method for forming the isolation structure 12 may include:

[0093] Multiple grooves are formed in the semiconductor substrate 10, and insulating material layers are filled in the grooves to form an isolation structure 12.

[0094] Forming a trench within the semiconductor substrate 10 can be achieved through dry etching or wet etching. Filling the trench with an insulating material layer can be achieved by depositing an insulating material layer over the entire surface, followed by removing the insulating material layer outside the trench using chemical mechanical polishing.

[0095] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure according to the third embodiment of the present invention.

[0096] Reference Figure 8 As shown, the semiconductor structure 3 and its fabrication method in Embodiment 3 are largely the same as the semiconductor structures 1 and 2 and their fabrication methods in Embodiments 1 and 2, with the only difference being that the buffer layer 112 is omitted in the stacked structure 11.

[0097] Figure 9 This is a cross-sectional schematic diagram of the semiconductor structure according to the fourth embodiment of the present invention.

[0098] Reference Figure 9 As shown, the semiconductor structure 4 of Embodiment 4 and its fabrication method are largely the same as the semiconductor structures 1, 2, and 3 of Embodiments 1, 2, and 3 and their fabrication methods, except that the heterojunction structure 13 includes, from bottom to top, a back barrier layer 133 and a channel layer 131.

[0099] Two-dimensional electron gas or two-dimensional hole gas can be formed at the interface between the back barrier layer 133 and the channel layer 131.

[0100] The back barrier layer 133 is preferably made of the same material as the first epitaxial layer 113.

[0101] Figure 10 This is a cross-sectional schematic diagram of the semiconductor structure according to the fifth embodiment of the present invention.

[0102] Reference Figure 10 As shown, the semiconductor structure 5 of Embodiment 5 is largely the same as the semiconductor structures 1, 2, 3, and 4 of Embodiments 1, 2, 3, and 4, except that: the heterojunction structure 13 includes: a source region 13a and a drain region 13b, and a gate region 13c located between the source region 13a and the drain region 13b; the source region 13a has a source 15a, the drain region 13b has a drain 15b, and the gate region 13c has a P-type semiconductor layer 16 and a gate 15c in sequence.

[0103] In this embodiment, the P-type semiconductor layer 16 can deplete the two-dimensional electron gas in the heterojunction structure 13 and turn off the conductivity of the channel; that is, the P-type semiconductor layer 16 is used to form a normally off state, which is to form an enhancement semiconductor structure 5.

[0104] The material of the P-type semiconductor layer 16 can be a group III nitride-based material, and the corresponding formation method can refer to the formation process of the channel layer 131 or the barrier layer 132. The P-type dopant ions can be at least one of Mg ions, Zn ions, Ca ions, Sr ions or Ba ions.

[0105] Figure 10 In this structure, the source 15a and drain 15b are connected to the barrier layer 132, and ohmic contacts are formed between the source 15a and the barrier layer 132, and between the drain 15b and the barrier layer 132. The source 15a, drain 15b, and gate 15c can be made of metals, such as existing conductive materials like Ti / Al / Ni / Au and Ni / Au.

[0106] In some embodiments, ohmic contacts can be formed between the source 15a and the barrier layer 132, and between the drain 15b and the barrier layer 132 using N-type ion heavily doped layers. The N-type ion heavily doped layers enable the source 15a and the source region 13a of the heterojunction structure 13, and the drain 15b and the drain region 13b of the heterojunction structure 13, to directly form ohmic contact layers without high-temperature annealing, and avoid the performance degradation and reduced electron migration rate of the heterojunction structure 13 caused by the high temperatures during the annealing process.

[0107] In some embodiments, at least one of the source region 13a and drain region 13b of the heterojunction structure 13 may have an N-type ion heavily doped layer. The source region 13a and source 15a of the heterojunction structure 13 without an N-type ion heavily doped layer, or the drain region 13b and drain 15b of the heterojunction structure 13 without an N-type ion heavily doped layer, may form an ohmic contact layer by high-temperature annealing.

[0108] In the N-type ion heavily doped layer, the N-type ion can be at least one of Si ions, Ge ions, Sn ions, Se ions, and Te ions. For different N-type ions, the doping concentration can be greater than 1E19 / cm3. The N-type ion heavily doped layer can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN.

[0109] Accordingly, the fabrication method further includes: step S3, forming a source 15a on the source region 13a, forming a drain 15b on the drain region 13b, and sequentially forming a P-type semiconductor layer 16 and a gate 15c on the gate region 13c.

[0110] The area covered by the P-type semiconductor layer 16 can be slightly larger than the gate region 13c. Specifically, in step S3, the P-type semiconductor layer 16 can be formed first, and then the source 15a, drain 15b and gate 15c can be formed in the same process.

[0111] The P-type doped ions in the P-type semiconductor layer 16 can be doped in situ, i.e., doped while growing.

[0112] Figure 11 This is a cross-sectional schematic diagram of the semiconductor structure according to the sixth embodiment of the present invention.

[0113] Reference Figure 11 As shown, the semiconductor structure 6 in Embodiment 6 is largely the same as the semiconductor structure 5 in Embodiment 5, with the only difference being: (Refer to...) Figure 11 As shown, the source 15a and the drain 15b are in contact with the channel layer 132, and an ohmic contact is formed between them.

[0114] Accordingly, in the fabrication method, step S3 also removes the barrier layer 132 of the source region 13a and the drain region 13b.

[0115] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate (10); A plurality of stacked structures (11) and a plurality of isolation structures (12) are located on the semiconductor substrate (10), the stacked structures (11) are spaced apart, and the isolation structures (12) are located between adjacent stacked structures (11); the stacked structure (11) includes, from bottom to top, a nucleation layer (111) and a first epitaxial layer (113), and the thickness of the isolation structure (12) is less than the thickness of the stacked structure (11); as well as A heterojunction structure (13) is located on the plurality of stacked structures (11), the heterojunction structure (13) is distributed across the entire surface, and an air gap (14) is formed between the heterojunction structure (13) and the isolation structure (12), the air gap (14) being located between adjacent stacked structures (11).

2. The semiconductor structure according to claim 1, characterized in that, The stacked structure (11) further includes a buffer layer (112) located between the nucleation layer (111) and the first epitaxial layer (113).

3. The semiconductor structure according to claim 1 or 2, characterized in that, The heterojunction structure (13) includes, from bottom to top, a channel layer (131) and a barrier layer (132), wherein the first epitaxial layer (113) is made of the same material as the channel layer (131); Alternatively, the heterojunction structure (13) may include, from bottom to top, a back barrier layer (133) and a channel layer (131), wherein the first epitaxial layer (113) is made of the same material as the back barrier layer (133).

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor substrate (10) is made of sapphire, silicon carbide, silicon or diamond, and the isolation structure (12) is made of at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, magnesium oxide, titanium oxide and gallium oxide.

5. The semiconductor structure according to claim 1, characterized in that, The nucleation layer (111) is made of AlN or AlGaN, and the first epitaxial layer (113) and the heterojunction structure (13) are made of at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN.

6. The semiconductor structure according to claim 1, characterized in that, The heterojunction structure (13) includes a source region (13a) and a drain region (13b), and a gate region (13c) located between the source region (13a) and the drain region (13b); the source region (13a) has a source (15a), the drain region (13b) has a drain (15b), and the gate region (13c) has a P-type semiconductor layer (16) and a gate (15c) in sequence.

7. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate (10) is provided, on which a plurality of stacked structures (11) and a plurality of isolation structures (12) are formed respectively. The stacked structures (11) are spaced apart, and the isolation structures (12) are located between adjacent stacked structures (11). The stacked structure (11) includes, from bottom to top, a nucleation layer (111) and a first epitaxial layer (113). The thickness of the isolation structure (12) is less than the thickness of the stacked structure (11). Heterojunction structures (13) are epitaxially grown on the plurality of stacked structures (11), and the heterojunction structures (13) on adjacent stacked structures (11) are healed into a full-surface distribution. An air gap (14) is formed between the heterojunction structure (13) and the isolation structure (12), and the air gap (14) is located between adjacent stacked structures (11).

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The formation of a plurality of stacked structures (11) and a plurality of isolation structures (12) on the semiconductor substrate (10) includes: An isolation structure (12) is formed on the semiconductor substrate (10) at intervals. Using the isolation structure (12) as a mask, a core layer (111) and a first epitaxial layer (113) are sequentially grown on the semiconductor substrate (10) to form the plurality of stacked structures (11).

9. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The formation of a plurality of stacked structures (11) and a plurality of isolation structures (12) on the semiconductor substrate (10) includes: A core layer (111) and a first epitaxial layer (113) are sequentially grown on the semiconductor substrate (10). The nucleation layer (111) and the first epitaxial layer (113) in a certain area are removed to expose the semiconductor substrate (10), and the remaining nucleation layer (111) and the first epitaxial layer (113) are spaced apart to form the plurality of stacked structures (11). An isolation structure (12) is formed on the exposed semiconductor substrate (10).

10. The method for fabricating a semiconductor structure according to claim 8 or 9, characterized in that, Before growing the first epitaxial layer (113), a buffer layer (112) is also grown on the nucleation layer (111).

11. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The semiconductor substrate (10) is made of sapphire, silicon carbide, silicon, or diamond, and the isolation structure (12) is made of at least one of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, magnesium oxide, titanium oxide, and gallium oxide. The method for forming the isolation structure (12) includes: The insulating material layer is formed using physical vapor deposition or chemical vapor deposition. The insulating material layer is graphically formed to create an isolation structure (12); Or include: Multiple grooves are formed in the semiconductor substrate (10), and an insulating material layer is filled in the grooves to form the isolation structure (12).

12. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The semiconductor substrate (10) is made of silicon, the isolation structure (12) is made of silicon dioxide, and the isolation structure (12) is formed by local thermal oxidation.

13. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The heterojunction structure (13) includes, from bottom to top, a channel layer (131) and a barrier layer (132), wherein the first epitaxial layer (113) is made of the same material as the channel layer (131); Alternatively, the heterojunction structure (13) may include, from bottom to top, a back barrier layer (133) and a channel layer (131), wherein the first epitaxial layer (113) is made of the same material as the back barrier layer (133).

14. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The heterojunction structure (13) includes: a source region (13a) and a drain region (13b), and a gate region (13c) located between the source region (13a) and the drain region (13b); the fabrication method further includes: A source (15a) is formed on the source region (13a), a drain (15b) is formed on the drain region (13b), and a P-type semiconductor layer (16) and a gate (15c) are sequentially formed on the gate region (13c).

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