A thin-film transistor panel detection circuit and testing method

Abstract

This invention relates to a thin-film transistor panel testing circuit and testing method, including first and second fast detection circuits and first and second detection circuits, and also provides a corresponding testing method. Before attaching the electronic paper film, this invention applies a specific timing voltage to the detection signal input terminal, and then uses a voltage detection device to determine whether the panel has an open circuit or short circuit abnormality. The testing is not only accurate but also efficient in medium and large-sized display areas.

Description

Technical Field

[0001] This invention relates to the field of electronic paper circuit testing, and more specifically, to a thin-film transistor panel testing circuit and testing method. Background Technology

[0002] Electronic paper is used in almost every aspect of life, especially in cultural and educational activities, where its role is becoming increasingly prominent, playing an unparalleled role in both student learning and teacher instruction. The core of electronic paper lies in its display area, which is generally composed of a matrix of pixel units. Each horizontal row of pixel units is controlled by a scan line, and each vertical column of pixel units is controlled by a data line. Normally, each data line and scan line is independent and not electrically connected to each other during the entire electrical connection process. However, during manufacturing, sometimes data lines and scan lines break, creating open circuits, or short circuits occur at overlapping points. This results in only partial display of the electronic paper display area. Therefore, how to accurately test for open and short circuits in the scan and data lines to improve the yield rate is a problem that urgently needs to be solved.

[0003] A prior art solution provides a detection circuit for electronic paper, which includes an open-circuit detection circuit for detecting whether there is an open circuit in the data lines or scan lines within the electronic paper display area, a short-circuit detection circuit for detecting whether there is a short circuit between the data lines or scan lines, and a thin-film transistor combination test circuit electrically connected to the data lines or scan lines. This technical solution also provides a detection method for the electronic paper detection circuit.

[0004] However, the applicability of this detection circuit and method is limited, especially for medium to large-sized panels, where the testing efficiency is far from ideal, and it cannot combine the testing of open and short circuits in the scan lines and data lines. Furthermore, for medium to large-sized display panels, existing technologies typically only detect and determine abnormalities after an electronic paper film has been applied. If an abnormality is detected, the internal circuitry is rendered unusable, resulting in a waste of the electronic paper film and integrated circuit materials. Therefore, a detection circuit and method specifically designed for medium to large-sized panels are needed. Summary of the Invention

[0005] The purpose of this invention is to overcome the defects of the prior art and to provide a thin-film transistor panel detection circuit and testing method with simple circuit structure and convenient and simple testing.

[0006] The present invention provides a thin-film transistor panel detection circuit, the technical solution of which is as follows:

[0007] A thin-film transistor (TFT) panel detection circuit includes a first input terminal, a second input terminal, a third input terminal, a first TFT fast detection circuit, and a second TFT fast detection circuit. The first TFT fast detection circuit includes a plurality of first TFTs connected in parallel. The gate of each first TFT is electrically connected to the third input terminal, the source of each first TFT is electrically connected to the first input terminal, and the drain of each first TFT is electrically connected to a first end of a scan line. The second TFT fast detection circuit includes a plurality of second TFTs. The gate of each second TFT is electrically connected to the third input terminal, the source of each second TFT is electrically connected to the second input terminal, and the drain of each second TFT is electrically connected to a first end of a data line. The circuit also includes a first short-circuit or open-circuit detection circuit for detecting short circuits or open circuits in the scan line or data line.

[0008] The first short-circuit or open-circuit detection circuit includes several transistor combination circuits. Two adjacent transistor combination circuits are electrically connected through a thin-film transistor T5. The gate of each thin-film transistor T5 is electrically connected to the second end of a data line. Each transistor combination circuit is electrically connected to a fifth input terminal. Each transistor combination circuit is electrically connected to a first output terminal. Each transistor combination circuit is simultaneously electrically connected to the second end of a scan line and the second end of a data line.

[0009] The transistor combination circuit includes a first-end transistor combination circuit, a last-end transistor combination circuit, and several intermediate transistor combination circuits. The first-end transistor combination circuit is electrically connected to the fourth input terminal, and the last-end transistor combination circuit is also electrically connected to the second output terminal.

[0010] Compared with the prior art, the technical solution provided by this invention application offers at least the following advantages: By designing a new detection circuit and detection terminal, this invention can not only determine whether the panel has an open or short circuit by applying a specific timing voltage to the detection input terminal before attaching the electronic paper film, thereby reducing waste and cost and improving yield, but also achieves high testing efficiency in the testing of medium to large-sized panels with the help of numerous transistor combination circuits. Simultaneously, when an input signal is received, the first and second thin-film transistor fast detection circuits transmit the signal to the data lines and scan lines, enabling the detection signal of this circuit to conduct, thus effectively utilizing the electronic characteristics of the fast detection circuit and improving testing efficiency.

[0011] Preferably, the first-end transistor combination circuit includes a first-end thin-film transistor, a second-end thin-film transistor, a third-end thin-film transistor, and a fourth-end thin-film transistor. The source of the first-end thin-film transistor is electrically connected to the first output terminal, the drain of the first-end thin-film transistor is electrically connected to the fourth input terminal, the gate of the first-end thin-film transistor is electrically connected to the source of the third-end thin-film transistor, the source of the third-end thin-film transistor is also electrically connected to the drain of the thin-film transistor T5 adjacent to the first-end transistor combination circuit, and the gate of the third-end thin-film transistor is electrically connected to the second terminal of the scan line. The drain of the third thin-film transistor is electrically connected to the source of the second thin-film transistor at the first end. The drain and gate of the second thin-film transistor at the first end are both electrically connected to the fifth input terminal. The drain of the third thin-film transistor at the first end is also electrically connected to the source of the fourth thin-film transistor at the first end. The gate of the fourth thin-film transistor at the first end is electrically connected to the second end of the data line. The drain of the fourth thin-film transistor at the first end is electrically connected to the fourth input terminal. This part of the circuit is located at the beginning of the entire circuit. It receives the input signal, connects the data line and the scan line, and can also directly output the signal to the output terminal and the next group of transistor combination circuits. It has good detection efficiency and facilitates signal transmission.

[0012] Preferably, the terminal transistor combination circuit includes a first terminal thin-film transistor, a second terminal thin-film transistor, a third terminal thin-film transistor, and a fourth terminal thin-film transistor. The source of the first terminal thin-film transistor is electrically connected to the first output terminal, the drain of the first terminal thin-film transistor is electrically connected to the source of the thin-film transistor T5 adjacent to the terminal transistor combination circuit, the gate of the first terminal thin-film transistor is electrically connected to the source of the third terminal thin-film transistor, the source of the third terminal thin-film transistor is also electrically connected to the second output terminal, and the gate of the third terminal thin-film transistor is electrically connected to the second terminal of the scan line. The drain of the body transistor is electrically connected to the source of the second thin-film transistor at the end. The drain and gate of the second thin-film transistor at the end are both electrically connected to the fifth input terminal. The drain of the third thin-film transistor at the end is also electrically connected to the source of the fourth thin-film transistor at the end. The gate of the fourth thin-film transistor at the end is electrically connected to the second end of the data line. The drain of the fourth thin-film transistor at the end is electrically connected to the source of the thin-film transistor T5. This part of the circuit is located at the end and can export the signals from the transistor combination circuits of other parts. Moreover, since it is also connected to the data line and the scan line, it can accurately transmit signals regarding the on / off status of the data line and the scan line connected to it.

[0013] Preferably, the intermediate transistor combination circuit includes an intermediate first thin-film transistor, an intermediate second thin-film transistor, an intermediate third thin-film transistor, and an intermediate fourth thin-film transistor. The source of the intermediate first thin-film transistor is electrically connected to the first output terminal, the drain of the intermediate first thin-film transistor is electrically connected to the source of the thin-film transistor T5 adjacent to the intermediate transistor combination circuit in the first stage, the gate of the intermediate first thin-film transistor is electrically connected to the source of the intermediate third thin-film transistor, the source of the intermediate third thin-film transistor is also electrically connected to the drain of the thin-film transistor T5 adjacent to the intermediate transistor combination circuit in the second stage, and the gate of the intermediate third thin-film transistor is connected to the scan line. The second terminal is electrically connected. The drain of the intermediate third thin-film transistor is electrically connected to the source of the intermediate second thin-film transistor. The drain and gate of the intermediate second thin-film transistor are both electrically connected to the fifth input terminal. The drain of the intermediate third thin-film transistor is also electrically connected to the source of the intermediate fourth thin-film transistor. The gate of the intermediate fourth thin-film transistor is electrically connected to the second terminal of the data line. The drain of the intermediate fourth thin-film transistor is electrically connected to the source of the thin-film transistor T5, which is adjacent to the first intermediate transistor combination circuit. This part of the circuit is located in the middle, connected to the first terminal signal at the top and the end terminal circuit at the bottom. In addition, it is also connected to the data line and the scan line, which can realize the fast and accurate presentation of the signal.

[0014] Preferably, the first short-circuit or open-circuit detection circuit is located at the top of the display area, so as not to occupy the display area and to ensure efficiency and safety.

[0015] Preferably, the thin-film transistor panel detection circuit further includes a second short-circuit or open-circuit detection circuit for detecting the open circuit of the via scan line through the line-changing hole. The second short-circuit or open-circuit detection circuit includes a plurality of third thin-film transistors connected in series. The drain of the first third thin-film transistor is electrically connected to the fourth input terminal, and the source of the last third thin-film transistor is electrically connected to the third output terminal. The gate of each third thin-film transistor is electrically connected to the second end of a scan line. The presence of this circuit ensures the determination of short-circuit or open-circuit conditions of the data line through the line-changing hole.

[0016] Preferably, the second short-circuit or open-circuit detection circuit is located on one side of the via scan line in the display area, so as not to occupy the display area space and to improve space utilization.

[0017] Meanwhile, the present invention also provides a method for short-circuit and open-circuit testing of scan lines and data lines of a thin-film transistor panel, applicable to the first short-circuit or open-circuit detection circuit, including a scan line or data line open-circuit detection method, a scan line short-circuit detection method, and a data line short-circuit detection method.

[0018] The method for detecting open circuits in scan lines or data lines includes the following steps:

[0019] A1. Input a high level H2 to the first input terminal, input a high level H2 to the second input terminal, and input a high level H1 to the third input terminal, where H1>H2;

[0020] A2. Input a low level L1 to the fourth input terminal and a low level L2 to the fifth input terminal, where L1>L2;

[0021] A3. Measure the voltage signal at the second output terminal using a voltage detection device. If the L1 signal is detected, it indicates that the scan line and data line are normal. If a ground signal is detected, it indicates that there is an open circuit in the scan line or data line.

[0022] The data cable short-circuit detection method includes the following steps:

[0023] B1. Input a high level H2 to the first input terminal, a low level L to the second input terminal, and a high level H1 to the third input terminal;

[0024] B2. Ground the fourth input terminal and input a high level H2 to the fifth input terminal;

[0025] B3. Measure the voltage signal at the first output terminal using a voltage detection device. If a ground signal is detected, the data line is normal. If a high-level signal is detected, the data line is short-circuited.

[0026] The scan line short-circuit detection method includes the following steps:

[0027] C1. Input a low level L to the first input terminal, a high level H2 to the second input terminal, and a high level H1 to the third input terminal;

[0028] C2. Ground the fourth input terminal and input a high level H2 to the fifth input terminal;

[0029] C3. Measure the voltage signal at the first output terminal using a voltage detection device. If a ground signal is detected, the scan line is normal. If a high-level signal is detected, the scan line is short-circuited.

[0030] This method is simple to operate and highly practical. After the signal is input, only a voltage testing device such as a multimeter is needed as a testing tool to quickly detect the continuity. Moreover, before attaching the electronic paper film, a specific timing voltage is applied to the detection input terminal to determine whether there is an open circuit or short circuit in the panel, thereby reducing waste and cost, improving yield, and being economical and applicable.

[0031] Preferably, the method for testing short circuits and open circuits of thin-film transistor panel scan lines and data lines also includes a method for detecting open circuits of via scan lines passing through replacement holes, comprising the following steps:

[0032] Step 1: Input a high level H to the first input terminal, a low level L to the second input terminal, and a high level H to the third input terminal;

[0033] Step 2: Input a low level L to the fourth input terminal and a low level L to the fifth input terminal;

[0034] Step 3: Measure the voltage signal at the third output terminal using a voltage detection device. If a low-level signal is detected, it indicates that the via scan line through the line-changing hole is normal. If a ground signal is detected, it indicates that there is an open circuit in the via scan line through the line-changing hole.

[0035] This method provides guidance for detecting short circuits in via data lines. The method is simple to operate; you only need to use a multimeter to test the third output terminal after the input signal to detect the result. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the overall structure of the electronic paper display area of ​​a thin-film transistor panel detection circuit according to the present invention;

[0037] Figure 2 This is a structural diagram of the first and second thin-film transistor fast detection circuits for existing medium and large-sized display panels;

[0038] Figure 3 This is a structural diagram of the first short-circuit or open-circuit detection circuit of the present invention;

[0039] Figure 4 This is a structural diagram of the second short-circuit or open-circuit detection circuit of the present invention;

[0040] Figure 5 This is the circuit breaker detection timing sequence in an embodiment of the present invention;

[0041] Figure 6 This is the timing sequence for the data line short-circuit test in this embodiment of the invention;

[0042] Figure 7 This is the timing sequence for the scan line short-circuit test in an embodiment of the present invention;

[0043] Figure 8 This is the timing sequence for testing the open circuit of the via scan line in an embodiment of the present invention.

[0044] In the diagram, the numbers represent: 1. First thin-film transistor fast detection circuit; 2. Second thin-film transistor fast detection circuit; 3. Display area; 31. Scan line; 311. Via scan line; 32. Data line; 33. Replacement hole; 4. First short-circuit or open-circuit detection circuit; 41. First-end transistor combination circuit; 411. First-end first thin-film transistor; 412. First-end second thin-film transistor; 413. First-end third thin-film transistor; 414. First-end fourth thin-film transistor; 42. End transistor combination circuit; 421. End first thin-film transistor; 422. 423. End-end second thin-film transistor; 424. End-end third thin-film transistor; 43. Intermediate transistor combination circuit; 431. Intermediate first thin-film transistor; 432. Intermediate second thin-film transistor; 433. Intermediate third thin-film transistor; 434. Intermediate fourth thin-film transistor; 5. Second short-circuit or open-circuit detection circuit; 51. First input terminal; 52. Second input terminal; 53. Third input terminal; 54. Fourth input terminal; 55. Fifth input terminal; 61. First output terminal; 62. Second output terminal; 63. Third output terminal. Detailed Implementation

[0045] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0046] Combination Figure 1 —5. This embodiment provides a detailed description of a technical solution for a thin-film transistor panel detection circuit.

[0047] This invention provides a thin-film transistor (TFT) panel detection circuit, comprising a first input terminal 51, a second input terminal 52, a third input terminal 53, a first TFT fast detection circuit 1, and a second TFT fast detection circuit 2. The first TFT fast detection circuit 1 comprises a plurality of first TFTs connected in parallel. The gate of each first TFT is electrically connected to the third input terminal 53, the source of each first TFT is electrically connected to the first input terminal 51, and the drain of each first TFT is electrically connected to the first end of a scan line 31. The second TFT fast detection circuit 2 comprises a plurality of second TFTs. The gate of each second TFT is electrically connected to the third input terminal 53, the source of each second TFT is electrically connected to the second input terminal 52, and the drain of each second TFT is electrically connected to the first end of a data line 32.

[0048] The two circuits described above are existing fast-detection circuits used to check for short circuits in the scan lines and data lines of medium and large display panels. However, if these circuits are used for testing, the presence of abnormalities in the data lines and scan lines can only be determined after an electronic paper film is applied. These two circuits are typically located at the lower end of the display area and are responsible for transmitting input signals to the scan lines or data lines, thus also functioning as switches in a certain sense. In this embodiment, the scan lines and data lines are arranged sequentially, represented as G1, G2, etc., and the data lines are also arranged sequentially, represented as D1, D2, etc.

[0049] The first input terminal 51 is connected to the scan line through the first fast detection circuit, so it can also be called the scan line signal input terminal (gatepad). The second input terminal 52 is connected to the data line through the second fast detection circuit, so it can also be called the data line signal input terminal (datapad). The third input terminal 53 is a control terminal used to control the conduction or shutdown of each thin-film transistor, so it can also be called the switch signal input terminal (switchpad).

[0050] The key feature of this invention is that it also includes a first short-circuit or open-circuit detection circuit 4 for detecting short circuits or open circuits in the scan line 31 or the data line 32. The first short-circuit or open-circuit detection circuit 4 includes several transistor combination circuits. Adjacent transistor combination circuits are electrically connected via thin-film transistors T5. The gate of each thin-film transistor T5 is electrically connected to the second terminal of a data line 32. Each transistor combination circuit is electrically connected to a fifth input terminal 55 and a first output terminal 61. Each transistor combination circuit is simultaneously electrically connected to the second terminal of both a scan line 31 and a data line 32.

[0051] The transistor combination circuit includes a first-end transistor combination circuit 41, a last-end transistor combination circuit 42, and several intermediate transistor combination circuits 43. The first-end transistor combination circuit 41 is electrically connected to the fourth input terminal 54, and the last-end transistor combination circuit 42 is also electrically connected to the second output terminal 62.

[0052] In this embodiment, the first-end transistor combination circuit 41 includes a first-end first thin-film transistor 411, a first-end second thin-film transistor 412, a first-end third thin-film transistor 413, and a first-end fourth thin-film transistor 414. The source of the first-end thin-film transistor 411 is electrically connected to the first output terminal 61, the drain of the first-end first thin-film transistor 411 is electrically connected to the fourth input terminal 54, and the gate of the first-end first thin-film transistor 411 is electrically connected to the source of the first-end third thin-film transistor 413. The source of the first-end third thin-film transistor 413 is also adjacent to the first-end transistor combination circuit 41. The drain of thin-film transistor T5 is electrically connected. The gate of the first-end third thin-film transistor 413 is electrically connected to the second end of the scan line 31. The drain of the first-end third thin-film transistor 413 is electrically connected to the source of the first-end second thin-film transistor 412. The drain and gate of the first-end second thin-film transistor 412 are both electrically connected to the fifth input terminal 55. The drain of the first-end third thin-film transistor 413 is also electrically connected to the source of the first-end fourth thin-film transistor 414. The gate of the first-end fourth thin-film transistor 414 is electrically connected to the second end of the data line 32. The drain of the first-end fourth thin-film transistor 414 is electrically connected to the fourth input terminal 54.

[0053] In this embodiment, the terminal transistor combination circuit 42 includes a first terminal thin-film transistor 421, a second terminal thin-film transistor 422, a third terminal thin-film transistor 423, and a fourth terminal thin-film transistor 424. The source of the first terminal thin-film transistor 421 is electrically connected to the first output terminal 61, the drain of the first terminal thin-film transistor 421 is electrically connected to the source of the thin-film transistor T5 adjacent to the terminal transistor combination circuit 42, and the gate of the first terminal thin-film transistor 421 is electrically connected to the source of the third terminal thin-film transistor 423. The source of the third terminal thin-film transistor 423 is also electrically connected to... The second output terminal 62 is electrically connected. The gate of the third thin-film transistor 423 at the end is electrically connected to the second end of the scan line 31. The drain of the third thin-film transistor 423 at the end is electrically connected to the source of the second thin-film transistor 422 at the end. The drain and gate of the second thin-film transistor 422 at the end are both electrically connected to the fifth input terminal 55. The drain of the third thin-film transistor 423 at the end is also electrically connected to the source of the fourth thin-film transistor 424 at the end. The gate of the fourth thin-film transistor 424 at the end is electrically connected to the second end of the data line 32. The drain of the fourth thin-film transistor 424 at the end is electrically connected to the source of the thin-film transistor T5.

[0054] In this embodiment, the intermediate transistor combination circuit 43 includes an intermediate first thin-film transistor 431, an intermediate second thin-film transistor 432, an intermediate third thin-film transistor 433, and an intermediate fourth thin-film transistor 434. The source of the intermediate first thin-film transistor 431 is electrically connected to the first output terminal 61, the drain of the intermediate first thin-film transistor 431 is electrically connected to the source of the thin-film transistor T5 adjacent to the right side of the intermediate transistor combination circuit 43, the gate of the intermediate first thin-film transistor 431 is electrically connected to the source of the intermediate third thin-film transistor 433, and the source of the intermediate third thin-film transistor 433 is also adjacent to the left side of the intermediate transistor combination circuit 43. The drain of the thin-film transistor T5 is electrically connected. The gate of the intermediate third thin-film transistor 433 is electrically connected to the second end of the scan line 31. The drain of the intermediate third thin-film transistor 433 is electrically connected to the source of the intermediate second thin-film transistor 432. The drain and gate of the intermediate second thin-film transistor 432 are both electrically connected to the fifth input terminal 55. The drain of the intermediate third thin-film transistor 433 is also electrically connected to the source of the intermediate fourth thin-film transistor 434. The gate of the intermediate fourth thin-film transistor 434 is electrically connected to the second end of the data line 32. The drain of the intermediate fourth thin-film transistor 434 is electrically connected to the source of the thin-film transistor T5 adjacent to the right side of the intermediate transistor combination circuit 43 in which it is located.

[0055] The thin-film transistor panel detection circuit of this embodiment also includes a second short-circuit or open-circuit detection circuit 5 for detecting open or short circuits in the via scan line 311 passing through the line-changing hole 33. The second short-circuit or open-circuit detection circuit 5 includes a plurality of third thin-film transistors connected in series. The drain of the first third thin-film transistor is electrically connected to the fourth input terminal 54, and the source of the last third thin-film transistor is electrically connected to the third output terminal 63. The gate of each third thin-film transistor is electrically connected to the second end of a via scan line 311. The via data line is the scan line in the data line 32 that passes through the line-changing hole 33. Since there can only be one line-changing hole 33 per row in the display area, the presence of the line-changing hole may affect the determination of the open circuit status of the via scan line 311. Therefore, for safety reasons, the second short-circuit or open-circuit detection circuit 5 is designed.

[0056] In this embodiment, the first short circuit or open circuit detection circuit 4 is disposed at the top of the display area 3; the second short circuit or open circuit detection circuit 5 is disposed on one side of the via scan line 311 of the display area 3.

[0057] This embodiment also provides a method for testing short circuits and open circuits of scan lines and data lines in a thin-film transistor panel, the specific technical solution of which is as follows;

[0058] A method for short-circuit and open-circuit testing of scan lines and data lines in a thin-film transistor panel is applicable to the first short-circuit or open-circuit detection circuit 4 in the thin-film transistor panel detection circuit of this embodiment, including a method for detecting open circuit of scan line 31 or data line 32, a method for detecting short circuit of scan line 31, and a method for detecting short circuit of data line 32.

[0059] The open circuit detection method for scan line 31 or data line 32 includes the following steps:

[0060] Step 1: Input a high level H2 to the first input terminal 51, input a high level H2 to the second input terminal 52, and input a high level H1 to the third input terminal 53, where H1 > H2;

[0061] Step 2: Input a low level L1 to the fourth input terminal 54 and a low level L2 to the fifth input terminal 55, where L1 > L2;

[0062] Step 3: Use a multimeter to test the voltage signal at the second output terminal 62. If the L1 signal can be detected, it means that the scan line 31 and the data line 32 are normal. If the ground signal is detected, it means that there is an open circuit in the scan line 31 or the data line 32.

[0063] The specific driving timing of this method is as follows: Figure 5 As shown.

[0064] Next, the short-circuit detection method for data cable 32 includes the following steps:

[0065] Step 1: Input a high level H2 to the first input terminal 51, a low level L to the second input terminal 52, and a high level H1 to the third input terminal 53;

[0066] Step 2: Ground the fourth input terminal 54 and input a high level H2 to the fifth input terminal 55;

[0067] Step 3: Measure the voltage signal at the first output terminal 61 using a voltage detection device. If a ground signal is detected, it indicates that the data line 32 is normal. If a high-level signal is detected, it indicates that the data line 32 is short-circuited.

[0068] The specific driving timing of this method is as follows: Figure 6 As shown.

[0069] Next, the short-circuit detection method for scan line 31 includes the following steps:

[0070] Step 1: Input a low level L to the first input terminal 51, a high level H2 to the second input terminal 52, and a high level H1 to the third input terminal 53;

[0071] Step 2: Ground the fourth input terminal 54 and input a high level H2 to the fifth input terminal 55;

[0072] Step 3: Measure the voltage signal at the first output terminal 61 using a voltage detection device. If a ground signal is detected, it indicates that the scan line 31 is normal. If a high-level signal is detected, it indicates that the scan line 31 is short-circuited.

[0073] The specific driving timing of this method is as follows: Figure 7 As shown.

[0074] This embodiment also includes a method for detecting open circuits in via scan lines 311 passing through vias 33 in a thin-film transistor panel, comprising the following steps;

[0075] Step 1: Input a high level H to the first input terminal 51, a low level L to the second input terminal 52, and a high level H to the third input terminal 53;

[0076] Step 2: Input a low level L to the fourth input terminal 54 and a low level L to the fifth input terminal 55;

[0077] Step 3: Measure the voltage signal at the third output terminal 63 using a voltage detection device. If a low-level signal is detected, it indicates that the via scan line 311 through the line change hole 33 is normal. If a ground signal is detected, it indicates that there is an open circuit in the via scan line 311 through the line change hole 33.

[0078] The specific driving timing of this method is as follows: Figure 8 As shown.

[0079] In the specific testing process, the open and short circuit conditions of the data line and scan line are first checked. If a short circuit or open circuit is detected in the scan line, the open circuit detection method of the through-hole scan line 311 through the line replacement hole 33 is used for further judgment, thus achieving accurate judgment. Of course, it can be used flexibly in the specific implementation process.

[0080] In summary, although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to the circuit structures and testing methods in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A thin film transistor panel detection circuit, comprising a first input terminal (51), a second input terminal (52), a third input terminal (53), a first thin film transistor fast detection circuit (1) and a second thin film transistor fast detection circuit (2), the first thin film transistor fast detection circuit (1) comprising a plurality of first thin film transistors connected in parallel, each first thin film transistor gate being electrically connected to the third input terminal (53), each first thin film transistor source being electrically connected to the first input terminal (51), and each first thin film transistor drain being electrically connected to a first end of a scanning line (31), the second thin film transistor fast detection circuit (2) comprising a plurality of second thin film transistors, each second thin film transistor gate being electrically connected to the third input terminal (53), each second thin film transistor source being electrically connected to the second input terminal (52), and each second thin film transistor drain being electrically connected to a first end of a data line (32), characterized in that: The first short-circuit or open-circuit detection circuit (4) comprises a plurality of transistor combination circuits, two adjacent transistor combination circuits are electrically connected through a thin film transistor T5, the gate electrode of each thin film transistor T5 is electrically connected with a second end of a data line (32), each transistor combination circuit is electrically connected with a fifth input end (55), each transistor combination circuit is electrically connected with a first output end (61), and each transistor combination circuit is simultaneously electrically connected with the second end of the scanning line (31) and the second end of the data line (32). The transistor combination circuit comprises a first-end transistor combination circuit (41), a last-end transistor combination circuit (42) and a plurality of intermediate transistor combination circuits (43), the first-end transistor combination circuit (41) is electrically connected with a fourth input end (54), and the last-end transistor combination circuit (42) is further electrically connected with a second output end (62). The first-end transistor combination circuit (41) comprises a first-end first thin film transistor (411), a first-end second thin film transistor (412), a first-end third thin film transistor (413) and a first-end fourth thin film transistor (414), the source electrode of the first-end first thin film transistor (411) is electrically connected with the first output end (61), the drain electrode of the first-end first thin film transistor (411) is electrically connected with the fourth input end (54), the gate electrode of the first-end first thin film transistor (411) is electrically connected with the source electrode of the first-end third thin film transistor (413), the source electrode of the first-end third thin film transistor (413) is further electrically connected with the drain electrode of the thin film transistor T5 adjacent to the first-end transistor combination circuit (41), the gate electrode of the first-end third thin film transistor (413) is electrically connected with the second end of the scanning line (31), the drain electrode of the first-end third thin film transistor (413) is electrically connected with the source electrode of the first-end second thin film transistor (412), and the drain electrode and the gate electrode of the first-end second thin film transistor (412) are electrically connected with the fifth input end (55), the drain electrode of the first-end third thin film transistor (413) is further electrically connected with the source electrode of the first-end fourth thin film transistor (414), the gate electrode of the first-end fourth thin film transistor (414) is electrically connected with the second end of the data line (32), and the drain electrode of the first-end fourth thin film transistor (414) is electrically connected with the fourth input end (54). ​ 2. The thin film transistor panel inspection circuit according to claim 1, characterized by: The end transistor combination circuit (42) comprises an end first thin film transistor (421), an end second thin film transistor (422), an end third thin film transistor (423), and an end fourth thin film transistor (424). The source electrode of the end first thin film transistor (421) is electrically connected with the first output terminal (61). The drain electrode of the end first thin film transistor (421) is electrically connected with the source electrode of the thin film transistor T5 adjacent to the end transistor combination circuit (42). The gate electrode of the end first thin film transistor (421) is electrically connected with the source electrode of the end third thin film transistor (423). The source electrode of the end third thin film transistor (423) is also electrically connected with the second output terminal (62). The gate electrode of the end third thin film transistor (423) is electrically connected with the second end of the scan line (31). The drain electrode of the end third thin film transistor (423) is electrically connected with the source electrode of the end second thin film transistor (422). The drain electrode and the gate electrode of the end second thin film transistor (422) are electrically connected with the fifth input terminal (55). The drain electrode of the end third thin film transistor (423) is also electrically connected with the source electrode of the end fourth thin film transistor (424). The gate electrode of the end fourth thin film transistor (424) is electrically connected with the second end of the data line (32). The drain electrode of the end fourth thin film transistor (424) is electrically connected with the source electrode of the thin film transistor T5.

3. The thin film transistor panel inspection circuit according to claim 2, characterized by: The intermediate transistor combination circuit (43) comprises an intermediate first thin film transistor (431), an intermediate second thin film transistor (432), an intermediate third thin film transistor (433), and an intermediate fourth thin film transistor (434). The source electrode of the intermediate first thin film transistor (431) is electrically connected with the first output terminal (61). The drain electrode of the intermediate first thin film transistor (431) is electrically connected with the source electrode of the thin film transistor T5 adjacent to the first side of the intermediate transistor combination circuit (43). The gate electrode of the intermediate first thin film transistor (431) is electrically connected with the source electrode of the intermediate third thin film transistor (433). The source electrode of the intermediate third thin film transistor (433) is also electrically connected with the drain electrode of the thin film transistor T5 adjacent to the second side of the intermediate transistor combination circuit (43). The gate electrode of the intermediate third thin film transistor (433) is electrically connected with the second end of the scan line (31). The drain electrode of the intermediate third thin film transistor (433) is electrically connected with the source electrode of the intermediate second thin film transistor (432). The drain electrode and the gate electrode of the intermediate second thin film transistor (432) are electrically connected with the fifth input terminal (55). The drain electrode of the intermediate third thin film transistor (433) is also electrically connected with the source electrode of the intermediate fourth thin film transistor (434). The gate electrode of the intermediate fourth thin film transistor (434) is electrically connected with the second end of the data line (32). The drain electrode of the intermediate fourth thin film transistor (434) is electrically connected with the source electrode of the thin film transistor T5 adjacent to the first side of the intermediate transistor combination circuit (43).

4. The thin film transistor panel inspection circuit according to claim 3, characterized by: The first short-circuit or open-circuit detection circuit (4) is arranged on the top of the display area (3).

5. The thin film transistor panel inspection circuit according to claim 4, characterized by: The second short-circuit or open-circuit detection circuit (5) for detecting the open-circuit or short-circuit of the via hole scanning line (311) through the line changing hole (33) comprises a plurality of third thin film transistors connected in series, the drain electrode of the first end of the third thin film transistor is electrically connected with the fourth input end (54), the source electrode of the last end of the third thin film transistor is electrically connected with the third output end (63), and the gate electrode of each third thin film transistor is electrically connected with the second end of the via hole scanning line (311).

6. The thin film transistor panel inspection circuit according to claim 5, characterized by: The second short-circuit or open-circuit detection circuit (5) is arranged on the side of the via hole scanning line (311) of the display area (3).

7. A method for testing short circuits and open circuits of scan lines and data lines in a thin-film transistor panel, characterized in that: The thin film transistor panel detection circuit suitable for the thin film transistor panel detection circuit according to any one of claims 1-6 comprises an open-circuit detection method of the scanning line (31) or the data line (32), a short-circuit detection method of the scanning line (31) and a short-circuit detection method of the data line (32); The open-circuit detection method of the scanning line (31) or the data line (32) comprises the following steps: A1, inputting high level H2 to the first input end (51), inputting high level H2 to the second input end (52) and inputting high level H1 to the third input end, wherein H1>H2; A2, inputting low level L1 to the fourth input end (54) and inputting low level L2 to the fifth input end (55), wherein L1>L2; A3, detecting the voltage signal of the second output end (62) by using a voltage detection device, if L1 signal can be detected, it is indicated that the scanning line (31) and the data line (32) are normal, if ground signal is detected, it is indicated that the scanning line (31) or the data line (32) has open circuit; The short-circuit detection method of the scanning line (31) comprises the following steps: B1, inputting low level L to the first input end (51), inputting high level H2 to the second input end (52) and inputting high level H1 to the third input end (53); B2, grounding the fourth input end (54) and inputting high level H2 to the fifth input end (55); B3, detecting the voltage signal of the first output end (61) by using a voltage detection device, if ground signal can be detected, it is indicated that the scanning line (31) is normal, if high level signal is detected, it is indicated that the scanning line (31) has short circuit; The short-circuit detection method of the data line (32) comprises the following steps: C1, inputting high level H2 to the first input end (51), inputting low level L to the second input end (52) and inputting high level H1 to the third input end (53); C2, grounding the fourth input end (54) and inputting high level H2 to the fifth input end (55); C3, detecting the voltage signal of the first output end (61) by using a voltage detection device, if ground signal can be detected, it is indicated that the data line (32) is normal, if high level signal is detected, it is indicated that the data line (32) has short circuit.

8. The method of claim 7, wherein the method further comprises: applying a voltage to the scan line and the data line; and determining whether the scan line and the data line are short-circuited or open-circuited based on the voltage applied to the scan line and the data line. The open-circuit detection method of the via hole scanning line (311) through the line changing hole (33) comprises the following steps: Step one, input high level H to the first input end (51), input low level L to the second input end (52), and input high level H to the third input end (53); Step two, input low level L to the fourth input end (54) and input low level L to the fifth input end (55); Step three, detect the voltage signal of the third output end (63) by using the voltage detection device, if low level signal can be detected, it indicates that the via hole scanning line (311) through the line changing hole (33) is normal, if ground signal is detected, it indicates that the via hole scanning line (311) through the line changing hole (33) has open circuit.

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