A four-way parallel SAR imaging data transposition system based on DDR SDRAM

Abstract

The present invention discloses a four-way parallel SAR imaging data transposition system based on DDR SDRAM. The present invention divides the data matrix into 4×4 small matrix blocks for data processing, so that the 4-beat data processed in the range direction and the 4-beat data processed in the azimuth direction are just the same 4×4 matrix, which mainly solves the problems of many DDR line changes, low efficiency and large RAM cache required during 4-way parallel processing. The implementation steps are: writing the original data entering sequentially into the DDR SDRAM memory in a block storage manner; storing the data read out of the asynchronous FIFO into the RAM after passing through three shift registers to obtain 4 4×4 small matrix blocks for range data processing; writing the 4×4 small matrix block data into the DDR SDRAM memory again in a block storage manner through a serial-to-parallel conversion module and an asynchronous FIFO; each data read out through the asynchronous FIFO is just a 4×4 small matrix block, which is stored in the RAM and then the azimuth data is processed.

Description

Technical Field

[0001] The invention belongs to the field of radar imaging signal processing, and in particular relates to a system for quickly transposing four-way parallel data in radar imaging signal processing. Background Art

[0002] Synthetic Aperture Radar (SAR) has the characteristics of all-day, all-weather operation and high-resolution imaging accuracy. It has played a huge role in remote sensing mapping in cloudy and foggy areas, military reconnaissance, and national economic construction. In recent years, with the rapid development of hardware manufacturing, the design of SAR real-time imaging system has received more and more research. The SAR imaging signal processing process involves the transmission and storage of large amounts of data. Since the access to data during the imaging processing process needs to switch between the distance dimension and the azimuth dimension, the transposition efficiency is directly related to the speed of SAR imaging signal processing.

[0003] At present, DDR SDRAM (double data rate synchronous dynamic random access memory) is increasingly used in SAR imaging signal processing due to its large storage capacity, fast speed, low power consumption and low cost. In the SAR imaging processing system based on DDR SDRAM, there are two-page or three-page transposition methods in previous studies. This method implements matrix transposition by cyclically accessing two or three SDRAMs. The paper "High-efficiency matrix transposition method based on FPGA and DDR" published by Wu Qinwen of Nanjing Institute of Electronic Technology disassembles the data from the row dimension, so that the original row of data is arranged into a new small matrix to balance the read and write efficiency. The paper "CTM algorithm and implementation based on DDR SDRAM" published by Liu Chen and others of Xi'an Institute of Electronic Engineering proposed the fastest column reading matrix transposition algorithm, which first receives two azimuth data, and then splices the two data alternately and writes them into DDR SDRAM. This method can arrange the column data in order and read them out in sequence. The transposition methods in the above-mentioned literature are all designed for a one-way data processing system, and the data is input into the corresponding submodule by row or column. However, in some imaging algorithm processes, multiple data transpositions are required, and in FPGA-based implementation solutions, a multi-way parallel data processing design is mostly adopted, which will also result in the data being unable to be input into the corresponding submodule by row or column during the data processing process. Summary of the invention

[0004] The present invention mainly aims at the problem that the traditional transposition scheme used in parallel data processing has low reading and writing efficiency and requires a large amount of RAM to cache redundant data. The transposition scheme is optimized, and the echo data is decomposed into 4×4 data matrices for processing, which greatly reduces the RAM cache and row and column switching operations, and greatly improves the operation efficiency of the system.

[0005] The technical solution for realizing the present invention is as follows:

[0006] A four-way parallel SAR imaging data transposition system based on DDR SDRAM, comprising a range data processing module and an azimuth data processing module, wherein the range data processing module comprises a first DDR SDRAM, a first asynchronous FIFO, a shift register group, a first RAM group and a range data processing unit;

[0007] The first DDR SDRAM is used to receive radar echo data. The first DDR SDRAM burst length is 8, the data bit width is 64 bits, the radar echo data bit width is 32 bits, and the radar echo data is defined as a matrix of 8192×8192. The radar echo data is written into the first DDR SDRAM in a block storage manner, and each row of the radar echo data is evenly divided into 512 parts, each of which is 16 32-bit numbers, that is, 512 bits. The 512-bit data written each time occupies 8 address spaces of the first DDR SDRAM, specifically: write the first row of data from address 0, and write 16 32-bit data every 32 addresses; then write the second row of data from address 8, and then write 16 32-bit numbers every 32 addresses; then start the third row of data from address 16, and then write 16 32-bit numbers every 32 addresses; finally, start the fourth row of data from address 24, and then write 16 32-bit numbers every 32 addresses; the first DDR SDRAM is used to store the radar echo data in the first DDR SDRAM. SDRAM addresses 0-16383 are all filled; write 4 rows at a time in the same order until all radar echo data are written;

[0008] The first asynchronous FIFO is used to sequentially read out the data in the first DDR SDRAM, specifically: first read out the first 16 data of the first row, then read out the first 16 data of the second row, then read out the first 16 data of the third row, then read out the first 16 data of the fourth row; then read out the 17th to 32nd data of the first row, and read them out in this order;

[0009] The data read out from the first asynchronous FIFO passes through the shift register group in sequence, and the shift register group includes three 512-bit shift registers. The data passing through the shift register group is stored in the first RAM group. Specifically, the current output of the three 512-bit shift registers and the asynchronous FIFO, that is, the 16 columns of data in four rows, is written into 64 32-bit RAMs every four register processing clocks.

[0010] The first RAM group includes 64 32-bit RAMs, and the data stored in the RAM each time is 4 rows and 16 columns of 32-bit data, which is 4 4×4 matrix blocks. Each clock reads the same column of data of four rows from the first RAM group and inputs it to the data processing unit for processing;

[0011] The azimuth data processing module includes a register serial-to-parallel conversion unit, a second asynchronous FIFO, a second DDRSDRAM, a third asynchronous FIFO, a second RAM group and an azimuth data processing unit;

[0012] The register serial-to-parallel conversion unit combines the distance-processed data into 512-bit data every 4 data processing clocks, and writes it into the second DDR SDRAM through the second asynchronous FIFO, specifically: starting from address 0 of the second DDR SDRAM, writing 16 4×4 matrix blocks every 262144 addresses, after writing 2048 times, starting from address 128, writing 16 4×4 matrix blocks every 262144 addresses, in this order, after writing 2048 times, the initial address is increased by 128 until all 4×4 matrix blocks are written;

[0013] The third asynchronous FIFO is used to read out the data in the second DDR SDRAM in blocks and store them into the second RAM group. The 4×4 matrix blocks read out each time are just data processed in four directions. Specifically, starting from address 0 of the second DDR SDRAM, 16 32-bit data at address 0 are read out first, and then sequentially read every 128 addresses until all the data of the first row of 2048×2048 512-bit matrix blocks, that is, the first four rows of data of the 8192×8192 matrix, are read out; then 16 32-bit data at address 8 are read out, and then sequentially read every 128 addresses until all the data of the second row of 2048×2048 512-bit matrix blocks, that is, the 5th to 8th rows of data of the 8k×8k matrix, are read out; in this order, all the data are read out;

[0014] The second RAM group includes 2 RAM units, each RAM unit includes 16 32-bit RAMs, and the data in the second DDRSDRAM is stored as a whole in the 2 RAM units in a ping-pong manner with 16 32-bit data;

[0015] The azimuth data processing unit reads 16 32-bit data from the second RAM group per clock, and outputs 4 columns and 4 rows of data per data processing clock for azimuth data processing.

[0016] In the solution of the present invention, the 8192×8192 echo data matrix is ​​divided into 2048×2048 small matrices of 4 rows and 4 columns. Every 4 range or azimuth data processing is just one of the 4 rows and 4 columns of the data matrix, avoiding a large amount of data redundancy and line breaks in traditional single row and single column processing. The DDR SDRAM burst length is 8, and the data bit width is 64 bits, that is, one read and write command corresponds to the output of 512 bits of data, that is, the DDR write address can only be an integer multiple of 8. The radar echo data bit width is 32 bits, that is, one read and write to the DDR SDRAM is equivalent to reading out 16 32-bit data. The system is divided into a range data processing module and an azimuth data processing module. The distance data processing module includes a DDR group 1 storage module and an address control module, an input asynchronous FIFO, three 512-bit shift registers and 64 32-bit RAMs; the azimuth data transposition module includes a 128-bit to 512-bit serial-to-parallel conversion module, a distance output asynchronous FIFO, a DDR group 2 storage module and an address control module, an azimuth data input asynchronous FIFO and 16 32-bit RAMs.

[0017] The burst length of DDR SDRAM is 8, and the data width is 64 bits, that is, one read and write command corresponds to the output of 512 bits of data, that is, the DDR write address can only be an integer multiple of 8. The radar echo data width is 32 bits, that is, one read and write to DDR SDRAM is equivalent to reading out 16 32-bit data. The data input width of the asynchronous FIFO is equal to 16 times the original data width, that is, 512 bits, and the data output width is also equal to 16 times the original data width, that is, equal to the data width of DDR.

[0018] Each time the data stored in the RAM is 4 rows and 16 columns of 32-bit data, which is exactly 4 4×4 matrix blocks. Each clock cycle reads out one column of data, that is, 4 32-bit data. A 4×4 matrix block is obtained every 4 clock cycles.

[0019] Through the asynchronous FIFO, each 4×4 matrix block is written into the No. 2 DDRSDRAM memory in a block storage manner.

[0020] Starting from DDR address 0, 16 4×4 matrix blocks are written every 262144 addresses. After writing 2048 times, 16 4×4 matrix blocks are written every 262144 addresses starting from DDR address 128. In this order, after writing 2048 times, the initial address is increased by 128 until all 4×4 matrix blocks are written.

[0021] The data in the DDR is read out in blocks through the asynchronous FIFO, and the 4×4 matrix block read out each time is exactly the data processed in four azimuth directions.

[0022] Starting from address 0 of DDR, a 4×4 data matrix block is read out every 128 addresses; after each reading of 2048 times, the initial address is increased by 8, and a 4×4 data matrix block is read out again every 128 addresses; until 2048 4×4 matrix blocks are read 16 times, data is read out starting from the next address in the same order until all the data is read out.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] First, the present invention improves the DDR read and write efficiency of the parallel transposition system by optimizing the transposition scheme. In the current mainstream parallel transposition system, a 4-way parallel processing requires at least 4 burst operations on the DDR to read 4 different addresses. The present invention uses a block-based approach so that a burst can satisfy the 4-way parallel processing; compared with the mainstream parallel transposition system, the present invention greatly reduces the line-break activation operation of the DDR, greatly improves the read and write efficiency of the DDR, and greatly reduces the power consumption.

[0025] Secondly, the present invention avoids the traditional transposition system from using a large amount of RAM to cache redundant data. The current mainstream transposition scheme still needs to read out 512 bits of data each time after transposition, and only uses 128 bits of data each time. The remaining data needs to be cached until a whole column of 8912 data is read before it can be used again, which consumes a large amount of RAM to cache redundant data. The present invention divides the 8192×8192 data matrix into 2048×2048 4×4 matrix blocks, so that the 4 processing in the range direction and the 4 processing in the azimuth direction are just the same 4×4 matrix block. After transposition, only the current 512 bits of data need to be cached for processing, avoiding a large amount of RAM occupation.

[0026] Third, since the number of points in the range and azimuth directions of radar imaging processing data is a power of 2, the present invention uses a 4×4 small matrix block as a unit, so that the number of points in the range and azimuth directions can meet the power multiple of 4, which can meet the requirements of most imaging scenarios. And the matrix block with 4 rows and 4 columns just meets the 4-way parallel processing, and does not need to be cached, and can be directly pipelined.

[0027] Fourthly, the present invention can ensure that the input data in the range and azimuth directions are processed uninterruptedly, stored in the DDR and read out without loss, thereby ensuring the pipelined high-speed operation of the entire data processing flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1It is a block diagram of the implementation of a four-way parallel SAR imaging data transposition system based on DDR SDRAM of the present invention;

[0029] Figure 2 It is a schematic diagram of 4-way parallel data processing in the present invention.

[0030] Figure 3 It is a flow chart of distance data reading in the present invention;

[0031] Figure 4 This is the arrangement of distance data in DDR in the present invention;

[0032] Figure 5 It is a schematic diagram of distance data reading in the present invention;

[0033] Figure 6 It is a schematic diagram of matrix division in the present invention;

[0034] Figure 7 This is a flow chart of azimuthally transposed data reading in the present invention.

[0035] Figure 8 This is the arrangement of azimuth data in DDR in the present invention; DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with the accompanying drawings and specific implementation methods.

[0037] like Figure 1 As shown, the present invention proposes a four-way parallel SAR imaging data transposition system based on DDR SDRAM, and the system is divided into a range data processing module and an azimuth data processing module. The range data processing module includes a DDR group 1 storage module and an address control module, an input asynchronous FIFO, three 512-bit shift registers and 64 32-bit RAMs; the azimuth data transposition module includes a 128-bit to 512-bit serial-to-parallel conversion module, a range output asynchronous FIFO, a DDR group 2 storage module and an address control module, an azimuth data input asynchronous FIFO and 16 32-bit RAMs.

[0038] Except for DDR SDRAM, the rest of the modules are implemented on FPGA, and the FPGA uses the xc7vx690tffg1761-3 chip from XILINX. The DDR SDRAM chip model is MT8JTF12864HZ-1G6, which is DDR3 SDRAM, and the burst transmission length is set to 8. The development environment is XILINX's Vivado 2019.2, and the DDR SDRAM read and write interface uses the MIG core provided by Vivado.

[0039] In this specific implementation scheme, the size of the matrix to be transposed is 8192×8192, which is divided into distance processing before transposition and azimuth processing after transposition.

[0040] like Figure 2 As shown, this system implements 4-way parallel processing: when processing in the range direction, each clock processes 4 32-bit data in the same column of 4 rows; when processing in the azimuth direction, each clock processes 4 32-bit data in the same row of 4 columns:

[0041] The specific operation is as follows: first, the distance data is processed, such as Figure 3 shown.

[0042] After the 8192×8192 echo data is written into the DDR, it is read out through the asynchronous FIFO and then written into the shift register in sequence. The 16 columns of 4 rows of data obtained are written into the RAM every 4 75M clocks and then read out in 16 300M clocks.

[0043] The order in which echo data is written into DDR is as follows Figure 4 shown.

[0044] Divide each row of echo data into 512 equal parts, each of which is 16 32-bit numbers, i.e. 512 bits. Each 512-bit data written occupies 8 address spaces of DDR. When writing data to DDR, first write 16 32-bit numbers to address 0, then write 16 32-bit numbers every 32 addresses, until the first row is written; then write the second row of data to address 8, then write 16 32-bit numbers every 32 addresses; then write the third row of data to address 16, then write 16 32-bit numbers every 32 addresses; finally write the fourth row of data to address 24, then write 16 32-bit numbers every 32 addresses; fill up DDR addresses 0-16383. Write 4 rows of 4 rows to DDR in the same order until all echo data are written.

[0045] The writing effect is finally achieved that the echo data of the first 16 rows, 2nd row, 3rd row and 4th row are stored in the actual address of DDR in sequence, and then the next 16 rows, i.e. the 17th to 32nd row, of the echo data of the first row, 2nd row, 3rd row and 4th row are stored in the actual address of DDR in this order, and all the data of rows one to four are stored in the actual address of DDR in this order; then the echo data of rows 5 to 8 are stored in order, and all the echo data are stored in this order.

[0046] FPGA controls 16 32-bit data from DDR as a whole, reads the data through asynchronous FIFO in natural order, and outputs 4 rows of the same column data for distance data processing through serial-to-parallel conversion for each data processing clock.

[0047] like Figure 4 As shown, the first 16 data of the first row are read out, followed by the first 16 data of the second row, followed by the first 16 data of the third row, and then the first 16 data of the fourth row; then the 17th to 32nd data of the first row are read out, and so on.

[0048] like Figure 5 As shown. Read and write the shift registers in this order, and write the current output of the three 512-bit shift registers and the asynchronous FIFO, that is, four rows of 16 columns of data, into 64 32-bit RAMs every four register processing clocks. FPGA controls each clock to read the same column of data of four rows of data from RAM for data processing, and processes all four rows of 16 columns of data in RAM every 16 data processing clocks, that is, 64 32-bit data. At this time, four register clocks have just passed, and FPGA writes the next 4 rows of 16 columns of data into RAM.

[0049] like Figure 6 As shown. Divide the 8k×8k data into 2k×2k matrices with 4 rows and 4 columns. The 16 32-bit data obtained by the FPGA every 4 data processing clocks are the 2k×2k 4-row and 4-column matrix data. The 16 32-bit data processed by every 4 data processing clocks in the azimuth direction is exactly the 16 32-bit data processed by every 4 data processing clocks in the distance direction. Take each 4×4 data matrix as a whole, that is, divide the 8k×8k data matrix into 2048×2048 512-bit data blocks.

[0050] The FPGA controls the distance processed data to be combined into 512-bit data every 4 data processing clocks, that is, a 4-row 4-column matrix as mentioned above, and then writes it into the DDR.

[0051] Azimuth data processing Figure 7 As shown, after the 8192×8192 distance processed data is written into DDR, it is read out through the asynchronous FIFO and then ping-pong written into RAM group 1 and RAM group 2.

[0052] Press Figure 8The distance processed data is written into DDR in the order shown, where A(x,y) is a 4-row 4-column matrix. According to the segmented 512-bit data blocks, the first 16 512-bit data blocks of the first row are written into DDR, then the address is increased by 262144, and the 17th to 32nd 512bit data blocks of the first row are written, and the address is increased by 262144 again until all the data of the first row is written; then the first 16 512-bit data blocks of the second row are written at address 128, and then the address is increased by 262144. This sequence is repeated until all 2048 rows of 512-bit data are written.

[0053] FPGA control reads 16 32-bit data from DDR as a whole through asynchronous FIFO, and stores them into RAM group 1 and RAM group 2 in a ping-pong manner. RAM group 1 and RAM group 2 both contain 16 32-bit RAMs. When RAM group 1 writes data, RAM group 2 reads data, and when RAM group 2 writes data, RAM group 1 reads data, thereby ensuring uninterrupted data.

[0054] First read out 16 32-bit data at address 0 from DDR, then read sequentially every 128 addresses until all the data in the first row of the 2048×2048 512-bit matrix block is read, that is, the first four rows of the 8192×8192 matrix; then read out 16 32-bit data at address 8 from DDR, then read sequentially every 128 addresses until all the data in the second row of the 2048×2048 512-bit matrix block is read, that is, the 5th to 8th rows of the 8k×8k matrix. Continue in this order until all the data is read.

[0055] Each register clock reads 16 32-bit data, and each data processing clock outputs 4 columns and 4 rows of data for azimuth data processing.

Claims

1. A four-way parallel SAR imaging data transposition system based on DDR SDRAM, characterized in that: It includes a distance data processing module and an azimuth data processing module, wherein the distance data processing module includes a first DDR SDRAM, a first asynchronous FIFO, a shift register group, a first RAM group and a distance data processing unit; The first DDR SDRAM is used to receive radar echo data. The first DDR SDRAM burst length is 8, the data bit width is 64 bits, the radar echo data bit width is 32 bits, and the radar echo data is defined as a matrix of 8192×8192. The radar echo data is written into the first DDR SDRAM in a block storage manner, and each row of the radar echo data is evenly divided into 512 parts, each of which is 16 32-bit numbers, that is, 512 bits. The 512-bit data written each time occupies 8 address spaces of the first DDR SDRAM, specifically: write the first row of data from address 0, and write 16 32-bit data every 32 addresses; then write the second row of data from address 8, and then write 16 32-bit numbers every 32 addresses; then start the third row of data from address 16, and then write 16 32-bit numbers every 32 addresses; finally, start the fourth row of data from address 24, and then write 16 32-bit numbers every 32 addresses; the first DDR SDRAM is used to store the radar echo data in the first DDR SDRAM. SDRAM addresses 0-16383 are all filled; write 4 rows at a time in the same order until all radar echo data are written; The first asynchronous FIFO is used to sequentially read out the data in the first DDR SDRAM, specifically: first read out the first 16 data of the first row, then read out the first 16 data of the second row, then read out the first 16 data of the third row, then read out the first 16 data of the fourth row; then read out the 17th to 32nd data of the first row, and read them out in this order; The data read out from the first asynchronous FIFO passes through the shift register group in sequence, and the shift register group includes three 512-bit shift registers. The data passing through the shift register group is stored in the first RAM group. Specifically, the current output of the three 512-bit shift registers and the asynchronous FIFO, that is, the 16 columns of data in four rows, is written into 64 32-bit RAMs every four register processing clocks. The first RAM group includes 64 32-bit RAMs, and the data stored in the RAM each time is 4 rows and 16 columns of 32-bit data, which is 4 4×4 matrix blocks. Each clock reads the same column of data of four rows from the first RAM group and inputs it to the data processing unit for processing; The azimuth data processing module includes a register serial-to-parallel conversion unit, a second asynchronous FIFO, a second DDR SDRAM, a third asynchronous FIFO, a second RAM group and an azimuth data processing unit; The register serial-to-parallel conversion unit combines the distance-processed data into 512-bit data every 4 data processing clocks, and writes it into the second DDR SDRAM through the second asynchronous FIFO, specifically: starting from address 0 of the second DDR SDRAM, writing 16 4×4 matrix blocks every 262144 addresses, after writing 2048 times, starting from address 128, writing 16 4×4 matrix blocks every 262144 addresses, in this order, after writing 2048 times, the initial address is increased by 128 until all 4×4 matrix blocks are written; The third asynchronous FIFO is used to read out the data in the second DDR SDRAM in blocks and store them into the second RAM group. The 4×4 matrix blocks read out each time are just data processed in four directions. Specifically, starting from address 0 of the second DDR SDRAM, 16 32-bit data at address 0 are read out first, and then sequentially read every 128 addresses until all the data of the first row of 2048×2048 512-bit matrix blocks, that is, the first four rows of data of the 8192×8192 matrix, are read out; then 16 32-bit data at address 8 are read out, and then sequentially read every 128 addresses until all the data of the second row of 2048×2048 512-bit matrix blocks, that is, the 5th to 8th rows of data of the 8k×8k matrix, are read out; in this order, all the data are read out; The second RAM group includes two RAM units, each RAM unit includes 16 32-bit RAMs, and the data in the second DDR SDRAM is stored as a whole in the two RAM units in a ping-pong manner with 16 32-bit data; The azimuth data processing unit reads 16 32-bit data from the second RAM group per clock, and outputs 4 columns and 4 rows of data per data processing clock for azimuth data processing.

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