A high speed driver for a phased array antenna

Abstract

The application discloses a high-speed driving device of a phased array antenna, which is applied to a super surface reconfigurable phased array antenna and comprises a wave control board and a driving board integrated on the super surface reconfigurable phased array antenna; wherein the wave control board is connected with the driving board and an external host computer respectively, analyzes data transmitted by the host computer, converts the data into 256-way control data capable of being output in parallel, and then effectively outputs the data; and the driving board receives the 256-way control data to realize high-speed driving of the super surface reconfigurable phased array antenna. The chip single-pole double-throw switch (SPDT) is used as the antenna driving mode, so that state quick switching can be realized at low cost.

Description

Technical Field

[0001] This invention relates to the field of metasurface reconfigurable phased array antenna technology, and more specifically to a high-speed driving device for a phased array antenna. Background Technology

[0002] Phased array technology emerged as early as the late 1930s. The United States began research in 1937. However, it wasn't until the mid-1950s that two practical shipborne phased array radars were developed. Phased array radar fundamentally solved the inherent problems of traditional mechanically scanned radars. Under the same aperture and operating wavelength, phased array radars far surpass traditional radars in terms of reaction speed, target update rate, multi-target tracking capability, resolution, multi-functionality, and electronic countermeasures capabilities.

[0003] However, phased array antennas in the radar field have extremely high requirements for scanning speed; the scanning speed directly depends on the radar performance. Beam scanning is the core of metasurface reconfigurable phased array antennas, but traditional voltage conversion is driven by MOSFETs. However, due to junction capacitance equivalent circuitry and their own characteristics, MOSFETs, as switches, require a relatively long time to transition between states, making them unsuitable for applications like radar metasurfaces. (See appendix) Figure 1 The diagram illustrates the principle of a traditional MOSFET switching circuit. Using a MOSFET driving method, it theoretically requires an NPN transistor and a PNP transistor to achieve positive and negative voltage switching. However, MOSFETs have PN junctions and parasitic capacitances, which impede signal conversion, thus requiring a certain amount of time to reach a steady state. (See appendix.) Figure 2 Based on the corresponding response time shown, it takes at least 4µs to switch from negative voltage to positive voltage stability. In other words, high-end phased array radars need to ensure a beam switching time of 1µs, and this driving method cannot meet the switching requirements.

[0004] Therefore, how to develop a high-speed driving device for phased array antennas is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention provides a high-speed driving device for a phased array antenna to solve the technical problems existing in the prior art.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A high-speed driving device for a phased array antenna, used in a metasurface reconfigurable phased array antenna, includes: a wave control board and a driving board integrated on the metasurface reconfigurable phased array antenna;

[0008] The wave control board is connected to the drive board and an external host computer. It parses the data transmitted by the host computer and converts it into 256 channels of control data that can be output in parallel before outputting them effectively. The drive board receives the 256 channels of control data to realize high-speed driving of the metasurface reconfigurable phased array antenna.

[0009] Preferably, it also includes a power supply board, which provides 24V power to the wave control board.

[0010] Preferably, the wave control board includes: an FPGA chip, a 256-channel single-pole double-throw switch module, a 4G communication module, a network-to-serial converter module, and a GPS positioning module;

[0011] The FPGA chip parses the data transmitted from the host computer, the 4G communication module, the network-to-serial module, and the GPS positioning module to obtain parsed data. The parsed data is then converted into an output voltage signal and output to the driver board in parallel through a 256-channel single-pole double-throw switch module, providing 256 channels of control data.

[0012] Preferably, the FPGA chip has a serial interface pin, which is connected to a 485 bus and a 232 bus. The FPGA chip receives data transmitted from the host computer through the 485 bus and the 232 bus.

[0013] Preferably, the parsed data includes GPS information, inertial navigation information, RSSI calibration information, and algorithm compensation information.

[0014] Preferably, the circuit structure of the 256-channel single-pole double-throw switch module includes:

[0015] A single-pole double-throw switch includes a bipolar device positive power supply port, a bipolar device negative power supply port, a power output port, a control terminal, a positive voltage power supply port, a negative voltage power supply port, a first capacitor, and a second capacitor.

[0016] The power output port is connected to the moving end of the single-pole double-throw switch to receive power signals. The positive power port and the negative power port of the bipolar device are connected to the two stationary ends of the single-pole double-throw switch and output control signals through the control terminal to control the positive and negative voltage signals.

[0017] The positive voltage power supply port is grounded through the first capacitor;

[0018] The negative voltage power supply port is connected in series with the second capacitor and grounded.

[0019] Preferably, the driver board includes four 64-channel control relay combination modules.

[0020] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a high-speed driving device for phased array antennas, applied in metasurface reconfigurable phased array antennas, and using a chip single-pole double-throw switch (SPDT) as the antenna driving method, thereby enabling low-cost and rapid state switching. Specific beneficial effects are as follows:

[0021] (1) The present invention uses a single-pole double-throw switch (SPDT) to control positive and negative voltage signals and integrates the single-pole double-throw switch (SPDT) into the chip. With the same control of the number of drive channels, the present invention has a much smaller unit area than the existing MOS transistor drive method, saving circuit board cost.

[0022] (2) This invention eliminates many LC coupling devices, which reduces the obstruction to the signal and shortens the stable switching time from negative voltage to positive voltage. In other words, the response speed is 100 times that of the traditional MOS driving method.

[0023] (3) The driving method of the present invention can fully meet the requirement of 1µs beam switching response time for high-end phased array radar, and is also suitable for applications with higher radar requirements. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a driving circuit for a traditional MOSFET combination.

[0026] Figure 2 This is a schematic diagram illustrating the response time of a traditional MOSFET combination driving method.

[0027] Figure 3 This is a schematic diagram of the device structure of the present invention;

[0028] Figure 4 The circuit structure diagram is for a 256-channel single-pole double-throw switch module.

[0029] Figure 5 This is a schematic diagram of the response time of a 256-channel single-pole double-throw switch module. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] See appendix Figure 3 As shown, this embodiment of the invention discloses a high-speed driving device for a phased array antenna, which is applied in a metasurface reconfigurable phased array antenna, including: a wave control board and a driving board integrated on the metasurface reconfigurable phased array antenna;

[0032] The wave control board is connected to the driver board and the external host computer. It parses the data transmitted by the host computer and converts it into 256 channels of control data that can be output in parallel before outputting them effectively. The driver board receives the 256 channels of control data to realize the high-speed driving of the metasurface reconfigurable phased array antenna.

[0033] Compared to the traditional method of using MOSFETs as switches, with one P-channel and one N-channel, where the N-channel is on and the P-channel is off when the voltage is high, and the N-channel is off and the P-channel is on when the voltage is low, thus achieving the switching of positive and negative voltages, the MOSFETs themselves have a relatively large delay. This application achieves a higher response speed by using a single-pole double-throw switch.

[0034] In one specific embodiment, a power supply board is also included, which provides 24V power to the wave control board.

[0035] In one specific embodiment, the wave control board includes: an FPGA chip, a 256-channel single-pole double-throw switch module, a 4G communication module, a network-to-serial converter module, a GPS positioning module, and a serial interface;

[0036] The FPGA chip parses the data transmitted by the host computer through the 4G communication module, the network-to-serial module, and the GPS positioning module to obtain parsed data. The parsed data is then converted into output voltage signals and output to the driver board in parallel through the 256-channel single-pole double-throw switch module, providing 256 channels of control data.

[0037] In one specific embodiment, the parsed data includes GPS information, inertial navigation information, RSSI calibration information, and algorithm compensation information.

[0038] See appendix Figure 4 As shown, in one specific embodiment, the circuit structure of the 256-channel single-pole double-throw switch module includes:

[0039] A single-pole double-throw switch includes a bipolar device power supply positive port VCC+, a bipolar device power supply negative port VCC-, a power output port, a control terminal, a positive voltage power supply port VDD, a negative voltage power supply port VSS, and a first capacitor and a second capacitor.

[0040] The power output port is connected to the moving end D1 of the single-pole double-throw switch to receive the power signal. The positive and negative power ports of the bipolar device are connected to the two stationary ends S1B and S1A of the single-pole double-throw switch, and the control signal is output through the control terminal to realize the control of the positive and negative voltage signals.

[0041] The positive voltage power supply port is grounded through the first capacitor;

[0042] A second capacitor is connected in series between the negative voltage power supply port and the ground terminal and then grounded.

[0043] Specifically, the purpose of adding a capacitor to the positive voltage supply terminal VDD is for filtering, and the purpose of adding a capacitor between the negative voltage terminals VSS and GND is to prevent negative voltage interference signals and thus filter them.

[0044] In one specific embodiment, the FPGA chip has a serial interface pin, which is connected to a 485 bus and a 232 bus. The FPGA chip receives data transmitted from the host computer through the 485 bus and the 232 bus.

[0045] Through the above technical solution, this invention uses a single-pole double-throw (SPDT) switch to control positive and negative voltage signals, and integrates it into the chip. For the same number of drive channels, the SPDT method results in a much smaller area per unit area compared to the MOSFET drive method, saving circuit board costs. Furthermore, the SPDT eliminates many LC coupling devices, so signal obstruction is minimal, only affected by the manufacturing process. (See appendix.) Figure 5 As shown, the switching time from negative voltage to positive voltage stability is only 40ns at most, which means that the response speed is 100 times that of the MOS driving method. High-end phased array radars need to ensure a beam switching time of 1us, so this driving method can fully meet the response time requirement and even has more than enough, making it suitable for applications with higher radar requirements.

[0046] In one specific embodiment, the driver board includes four 64-channel control relay modules.

[0047] On the other hand, the present invention also discloses a high-speed driving method for a phased array antenna, specifically including the following steps:

[0048] (1) Improve refresh rate by controlling the beam of phased array antenna through FPGA.

[0049] (2) Use a single-pole double-throw switch to build a driving circuit to upgrade the antenna response speed.

[0050] Specifically, in step (1), the FPGA parses the data transmitted by the host computer. The parsed data includes GPS information, inertial navigation information, RSSI calibration information, algorithm compensation, etc. After parsing, 256 control data are output in parallel. The 256 control data are connected to 256 single-pole double-throw switches to realize the switching conversion of voltage switching.

[0051] More specifically, FPGAs are widely used as field-programmable gate array circuit chips. Due to their fast response speed, large number of GPIOs, and simultaneous synchronous output, they are a very suitable choice for phased array antennas with a large number of array elements.

[0052] Specifically, in step (2), the metasurface reconfigurable phased array antenna is a very advanced electronically scanned phased array antenna with a scanning speed much greater than that of traditional antennas. Since the phase transformation requires positive and negative voltage driving, the switching time of the positive and negative voltage of the power supply directly affects the performance of the antenna. However, the single-pole double-throw driving chip used in this patent fundamentally solves this problem.

[0053] In summary, this invention is applied to metasurface reconfigurable phased array antennas and uses a chip single-pole double-throw switch (SPDT) as the antenna driving method, thereby achieving low-cost and fast state switching.

[0054] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0055] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-speed driving device for a phased array antenna, characterized in that, Applications in metasurface reconfigurable phased array antennas include: a wave control board and a driver board integrated on the metasurface reconfigurable phased array antenna; The wave control board is connected to the drive board and an external host computer. It parses the data transmitted from the host computer and converts it into 256 channels of control data that can be output in parallel before outputting them effectively. The drive board receives the 256 channels of control data to realize high-speed driving of the metasurface reconfigurable phased array antenna. The wave control board includes: an FPGA chip, a 256-channel single-pole double-throw switch module, a 4G communication module, a network-to-serial converter module, and a GPS positioning module; The FPGA chip parses the data transmitted by the host computer, the 4G communication module, the network-to-serial module and the GPS positioning module to obtain parsed data. The parsed data is converted into an output voltage signal and outputs 256 control data channels to the driver board in parallel through the 256-channel single-pole double-throw switch module. The circuit structure of the 256-channel single-pole double-throw switch module includes: a single-pole double-throw switch, a bipolar device power positive port, a bipolar device power negative port, a power output port, a control terminal, a positive voltage power supply port, and a negative voltage power supply port; The power output port is connected to the moving end of the single-pole double-throw switch to receive power signals. The positive power port and the negative power port of the bipolar device are connected to the two stationary ends of the single-pole double-throw switch and output control signals through the control terminal to realize the control of positive and negative voltage signals. The driver board includes four 64-channel control relay combination modules.

2. The high-speed driving device for a phased array antenna according to claim 1, characterized in that, It also includes a power board that provides 24V power to the wave control board.

3. The high-speed driving device for a phased array antenna according to claim 1, characterized in that, The FPGA chip has a serial interface pin, which is connected to a 485 bus and a 232 bus. The FPGA chip receives data transmitted from the host computer through the 485 bus and the 232 bus.

4. The high-speed driving device for a phased array antenna according to claim 1, characterized in that, The analyzed data includes GPS information, inertial navigation information, RSSI calibration information, and algorithm compensation information.

5. The high-speed driving device for a phased array antenna according to claim 1, characterized in that, The circuit structure of the 256-channel single-pole double-throw switch module also includes: First capacitor and second capacitor; The positive voltage power supply port is grounded through the first capacitor; The negative voltage power supply port is connected in series with the second capacitor and grounded.

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