Video processing chip bandwidth monitoring and adjusting method, device, equipment and medium

Abstract

The application provides a video processing chip bandwidth monitoring and adjusting method, device, equipment and medium, comprising: acquiring a bandwidth monitoring signal of a submodule in real time; forming a corresponding adjusting feedback loop according to the bandwidth monitoring signal of the submodule to adjust the clock frequency and the input image frame rate. The application separately monitors the bandwidth monitoring signal of each submodule, forms a corresponding adjusting feedback loop according to the acquired bandwidth monitoring signal of the submodule to feedback and adjust the clock frequency and the input image frame rate, thereby reducing the bandwidth demand of the submodule and reducing the overall power consumption of the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of bandwidth monitoring, and in particular to a video processing chip bandwidth monitoring and adjusting method, device, equipment and medium. BACKGROUND

[0002] The data to be processed inside the chip is usually stored in the shared memory such as DRAM, SDRAM, etc. inside the chip, and only one data bus path can access the shared memory. When multiple devices need to access the shared memory, the problem of how to allocate limited bandwidth to meet the needs of application scenarios is involved.

[0003] Due to different access sequences of various modules, the arbitration mechanism currently used can only mechanically distribute bandwidth, and it is easy to cause the situation that the data access needs of all devices cannot be met. At this time, the computing power of the module not allocated with bandwidth will be wasted, and the system will generate additional power consumption.

[0004] Therefore, it is necessary to provide a video processing chip bandwidth monitoring and adjusting method, device, equipment and medium to solve the above problems. SUMMARY

[0005] The purpose of the present application is to provide a video processing chip bandwidth monitoring and adjusting method, device, equipment and medium to improve the problem that the existing arbitration mechanism cannot meet the data access needs of all devices.

[0006] In a first aspect, the present application provides a video processing chip bandwidth monitoring and adjusting method applied to a bandwidth monitoring module corresponding to a sub-module one by one, the sub-module being used for processing a video data stream. The method comprises: acquiring a bandwidth monitoring signal of the sub-module in real time; and forming a corresponding adjusting feedback loop according to the bandwidth monitoring signal of the sub-module to adjust a clock frequency and an input image frame rate.

[0007] The method provided by the present application has the beneficial effect that the bandwidth monitoring signals of each sub-module are monitored separately, a corresponding adjusting feedback loop is formed according to the acquired bandwidth monitoring signals of the sub-modules to feedback adjust the clock frequency and the input image frame rate, thereby reducing the bandwidth demand of the sub-modules and reducing the overall power consumption of the system.

[0008] In a possible embodiment, forming a corresponding adjusting feedback loop according to the bandwidth monitoring signal of the sub-module to adjust the clock frequency and the input image frame rate comprises:

[0009] overflow judgment is performed according to the bandwidth monitoring signal, and an overflow condition is acquired;

[0010] An adjusting signal is generated according to the overflow condition, and the adjusting signal is used to adjust the clock frequency and the input image frame rate.

[0011] In a possible embodiment, when the sub-module is a video stream module, overflow is judged according to the bandwidth monitoring signal, and overflow condition is obtained, and an adjustment signal is generated according to the overflow condition, the adjustment signal being used to adjust clock frequency and input image frame rate, comprising:

[0012] According to bus activity in the bandwidth monitoring signal, bus activity is counted, and when each horizontal synchronization signal in the field active area arrives, overflow and underflow signals are generated in real time according to overflow and underflow thresholds, the overflow and underflow signals being counted by a counter, a software interrupt or a hardware adjustment signal being generated in the field blanking area, and clock frequency and input image frame rate being adjusted in real time.

[0013] In a possible embodiment, overflow and underflow signals are generated in real time according to overflow and underflow thresholds, and the overflow and underflow signals are counted by a counter, comprising:

[0014] When the horizontal synchronization signal is greater than a horizontal signal overflow threshold, a horizontal overflow signal is generated, and the horizontal overflow signal is counted by a counter to obtain an overflow count;

[0015] When the horizontal synchronization signal is less than a horizontal signal underflow threshold, a horizontal underflow signal is generated, and the horizontal underflow signal is counted by a counter to obtain an underflow count.

[0016] In a possible embodiment, when the sub-module is a non-video stream module, overflow is judged according to the bandwidth monitoring signal, and overflow condition is obtained, and an adjustment signal is generated according to the overflow condition, comprising:

[0017] According to bus activity in the bandwidth monitoring signal, bus activity is counted in units of image frames, so as to count bus activity counts in a complete frame processing time, the bus activity counter synchronization signal being a signal pulse indicating that the sub-module starts to work and completes work, the bus activity counter being cleared when the sub-module starts to work, and overflow and underflow signals being generated when the sub-module completes work.

[0018] In a possible embodiment, when an overflow signal is generated, the adjustment signal is used to reduce sub-module clock frequency, lengthen horizontal blanking area length, lengthen field blanking area length, reduce video stream clock frequency, increase clock frequency of an arbiter and a shared memory module, and generate an overflow software interrupt.

[0019] When an underflow signal is generated, the adjustment signal is used to increase sub-module clock frequency, reduce horizontal blanking area length, reduce field blanking area length, increase video stream clock frequency, reduce clock frequency of an arbiter and a shared memory module, and generate an underflow software interrupt.

[0020] In a second aspect, the present application further provides a device for monitoring and adjusting bandwidth of a video processing chip. The device comprises a module / unit for implementing any of the methods according to the first aspect.

[0021] In a third aspect, the present application provides an electronic device. The electronic device comprises a processor and a memory. The memory is configured to store one or more computer programs. When the one or more computer programs stored in the memory are executed by the processor, the electronic device is enabled to implement any of the methods according to the first aspect.

[0022] In a fourth aspect, the present application provides a computer-readable storage medium. The computer-readable storage medium comprises a computer program. When the computer program is run on an electronic device, the electronic device is enabled to perform any of the methods according to any of the second aspect to the fifth aspect.

[0023] In a fifth aspect, the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device is enabled to perform any of the methods according to any of the second aspect to the fifth aspect.

[0024] The advantages of the second aspect to the fifth aspect can be referred to the description of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 FIG. 1 is a schematic diagram of a chip bus structure according to the present application.

[0026] Figure 2 FIG. 2 is a flowchart of a method for monitoring and adjusting bandwidth of a video processing chip according to the present application.

[0027] Figure 3 FIG. 3 is a schematic diagram of a bandwidth monitoring waveform of a method for monitoring and adjusting bandwidth of a video processing chip according to the present application.

[0028] Figure 4 FIG. 4 is a schematic diagram of a device for monitoring and adjusting bandwidth of a video processing chip according to the present application.

[0029] Figure 5 FIG. 5 is a schematic diagram of an electronic device according to the present application. DETAILED DESCRIPTION

[0030] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall into the scope of the present application. Unless otherwise defined, the technical terms or scientific terms used herein should be understood as the common meanings of the terms by those of ordinary skill in the art to which the present application belongs. The terms such as "comprise" and the like used herein mean that the elements or objects before the terms encompass the elements or objects listed after the terms and equivalents thereof, and do not exclude other elements or objects.

[0031] In view of the problems in the prior art, the embodiments of the present application provide a video processing chip bandwidth monitoring and adjusting method, Figure 1 FIG. 1 is a schematic diagram of a chip bus structure according to the present application, Figure 1 The method is applied to a bandwidth monitoring module 102 corresponding to each of sub-modules 101, and the sub-modules 101 are used to process video data streams. Figure 2 FIG. 2 is a flowchart of a video processing chip bandwidth monitoring and adjusting method according to the present application, Figure 2 The method comprises the following steps.

[0032] S201: Real-time acquisition of a bandwidth monitoring signal of a sub-module 101.

[0033] S202: Formation of a corresponding adjusting feedback loop according to the bandwidth monitoring signal of the sub-module 101, to adjust a clock frequency and an input image frame rate.

[0034] In S202, the formation of the corresponding adjusting feedback loop according to the bandwidth monitoring signal of the sub-module 101, to adjust the clock frequency and the input image frame rate, comprises: overflow judgment according to the bandwidth monitoring signal, and acquisition of an overflow condition; generation of an adjusting signal according to the overflow condition, the adjusting signal being used to adjust the clock frequency and the input image frame rate.

[0035] The present application judges the overflow of the bandwidth monitoring signal of the sub-module 101, to acquire the overflow condition of the bandwidth monitoring signal of the sub-module 101, and then generates a corresponding adjusting signal according to the overflow condition of the bandwidth monitoring signal, to adjust the clock frequency and the input image frame rate, thereby reducing the bandwidth demand of the sub-module 101 and reducing the overall power consumption of the system.

[0036] In the present embodiment, the sub-module 101 is divided into two cases of a video stream module and a non-video stream module, and the two cases will be described below.

[0037] In S201, in a preferred embodiment, Figure 3 The bandwidth monitoring waveform schematic diagram of the video processing chip bandwidth monitoring and adjusting method of the present application is shown in Figure 3 For the case that the sub-module 101 is a video stream module, overflow is judged according to the bandwidth monitoring signal, and overflow condition is obtained, and an adjusting signal is generated according to the overflow condition, which is used to adjust clock frequency and input image frame rate, including: counting bus activity according to bus activity in the bandwidth monitoring signal, and generating overflow and underflow signals in real time according to overflow and underflow thresholds when each horizontal synchronization signal in the field active area arrives, counting the overflow and underflow signals by a counter, generating a software interrupt or a hardware adjusting signal during the field blanking area, and adjusting the clock frequency and the input image frame rate in real time.

[0038] In the embodiment, the bus activity includes reading cache data, writing new data, and reading and writing at the same time. Bus activity and line activity are not necessarily one-to-one correspondence, and can be N:1 or 1:N according to the characteristics of the sub-module 101.

[0039] Preferably, the horizontal synchronization signal is a pulse signal or a level signal. The line active signal is a high level signal or a low level signal.

[0040] In S202, in a specific embodiment, overflow and underflow signals are generated in real time according to overflow and underflow thresholds, and the overflow and underflow signals are counted by a counter, including: when the horizontal synchronization signal is greater than the horizontal signal overflow threshold, a horizontal overflow signal is generated, the horizontal overflow signal is counted by a counter to obtain an overflow count; when the horizontal synchronization signal is less than the horizontal signal underflow threshold, a horizontal underflow signal is generated, and the horizontal underflow signal is counted by a counter to obtain an underflow count. Specifically, it is judged whether the horizontal synchronization signal is greater than the horizontal signal overflow threshold, and when the judgment result is yes, the current overflow count is increased by 1 by the counter to obtain a new overflow count, and the current overflow count is replaced by the new overflow count; it is judged whether the horizontal synchronization signal is less than the horizontal signal underflow threshold, and when the judgment result is yes, the current underflow count is increased by 1 by the counter to obtain a new underflow count, and the current underflow count is replaced by the new underflow count.

[0041] In S203, in a specific embodiment, the sub-module 101 is adjusted according to the overflow condition, including: during the field blanking area, adjustment is judged according to the overflow count or the underflow count to determine the adjustment mode and the adjustment step value, and the corresponding adjustment mode and the corresponding adjustment step value are used for adjustment.

[0042] In S201, in another preferred embodiment, for the case that the sub-module 101 is a non-video stream module, such as a rotation module, an OSD (on-screen display) module, etc. Overflow judgment is performed according to the bandwidth monitoring signal, and an overflow condition is obtained, and an adjustment signal is generated according to the overflow condition, including: according to the bus activity in the bandwidth monitoring signal, bus activity is counted in units of image frames, to count the bus activity count in a complete frame time, the bus activity counter synchronization signal is the signal pulse when the sub-module 101 starts working and completes work, and is cleared when the sub-module 101 starts working, and overflow up and overflow down signals are generated when the sub-module 101 completes work.

[0043] In S202, in a specific embodiment, the bus activity count synchronization signal is cleared when the sub-module 101 starts working, and overflow up and overflow down signals are generated when the sub-module 101 completes work, including: when the bus activity count synchronization signal in a frame time is greater than the bus activity signal overflow threshold, a bus activity overflow signal is generated, and an overflow time consumption ratio is calculated; when the bus activity count synchronization signal in a frame time is less than the bus activity signal underflow threshold, a bus activity underflow signal is generated, and an underflow time consumption ratio is calculated; wherein the bus statistical count value includes a bus activity count value and a bus idle count value, and the time consumption ratio is equal to the ratio of the bus activity count value and the bus statistical count value.

[0044] In a specific embodiment, the threshold judgment method of overflow up and overflow down can adopt absolute value judgment, or ratio value judgment, or a combination of the two.

[0045] In S203, in a specific embodiment, the sub-module 101 is adjusted according to the overflow condition, including: adjustment judgment is performed according to the overflow up time consumption ratio or the overflow down time consumption ratio, to determine the adjustment method and the adjustment step value, and the corresponding adjustment method and the corresponding adjustment step value are used for adjustment.

[0046] In S203, in a preferred embodiment, referring to Figure 1 When the overflow up signal is generated, the adjustment signal is used to reduce the clock frequency of the sub-module 101, lengthen the length of the row blanking area, lengthen the length of the field blanking area, reduce the video stream clock frequency, increase the clock frequency of the arbiter 103 and the shared memory 104 module, and generate an overflow up software interrupt. When the overflow down signal is generated, the adjustment signal is used to increase the clock frequency of the sub-module 101, reduce the length of the row blanking area, reduce the length of the field blanking area, increase the video stream clock frequency, reduce the clock frequency of the arbiter 103 and the shared memory 104 module, and generate an overflow down software interrupt.

[0047] In a possible embodiment, the adjustment signal is generated according to the overflow condition, including: setting a condition for triggering adjustment, and generating an adjustment signal of a corresponding adjustment mode when the condition for triggering adjustment is met. Specifically, the adjustment modes can be arranged in combination of thresholds, and the priority of each adjustment mode can also be arranged in combination. The hardware preferentially executes the adjustment mode with higher priority. For example, the number of times of triggering adjustment can be single or multiple, and can also be controlled by a register threshold. When the number of times of the overflow count or the number of times of the underflow count meets the number of times of triggering a certain adjustment mode, the adjustment signal of the adjustment mode is generated.

[0048] In a specific embodiment, different adjustment step values can be set for each adjustment mode. According to the threshold of the adjustment item (for example, the threshold of the clock frequency, the threshold of the row / field blanking area length), the adjustment can be performed according to the threshold of the adjustment item in proportion to the threshold of the adjustment item, or the adjustment can be performed according to the threshold of the adjustment item in a fixed step.

[0049] Further, upper and lower limit hard thresholds can be set for each adjustment mode. When the corresponding adjustment operation exceeds the hard threshold range of the adjustment item, the adjustment operation is not performed by using the adjustment mode, and an interruption of the corresponding operation is triggered. The software can configure a register to shield such interruption, and the limitation is used to avoid system abnormalities. The hardware processing mode when the out-of-range adjustment occurs is to automatically perform an adjustment of a priority lower than the current priority once, or not to perform the adjustment. That is, the hardware can automatically degrade the processing, or not to process.

[0050] The bandwidth monitoring and adjustment method of the video processing chip provided in the application proposes a bandwidth monitoring mechanism, which can monitor the bandwidth used by each sub-module 101 in real time at the hardware bottom layer, to judge and obtain the overflow and underflow of each sub-module 101, and feed back the adjustment of the corresponding clock frequency, row / field blanking area length, input image frame rate, and the like according to the overflow and underflow, so as to form a corresponding adjustment feedback loop, and achieve the effects of reducing bandwidth demand and lowering system power consumption. The application realizes real-time automatic adjustment of the frequency of the sub-module 101 by the hardware, automatically finds the lowest frequency that can meet the image processing requirements according to the load of different sub-modules 101, avoids performance waste, and lowers the overall power consumption of the system.

[0051] In addition, the application also proposes a bandwidth monitoring and adjustment device of a video processing chip, Figure 4 FIG. 1 is a schematic diagram of a bandwidth monitoring and adjustment device of a video processing chip according to the application, Figure 4The device comprises: an acquisition unit 401, configured to acquire a bandwidth monitoring signal of the sub-module 101 in real time; and an adjustment unit 402, configured to form a corresponding adjustment feedback loop according to the bandwidth monitoring signal of the sub-module 101, so as to adjust the clock frequency and the input image frame rate. All related contents of the steps involved in the method embodiments can be cited to the function description of the corresponding function modules, and will not be repeated here.

[0052] In some other embodiments of the present application, the embodiments of the present application disclose an electronic device, Figure 5 For the structural schematic diagram of the electronic device of the present application, see Figure 5 The electronic device can include one or more processors 501, a memory 502, a display 503, one or more application programs (not shown), and one or more computer programs 504. The above devices can be connected through one or more communication buses 505. The one or more computer programs 504 are stored in the memory 502 and configured to be executed by the one or more processors 501. The one or more computer programs 504 include instructions that can be used to perform the steps in the embodiments of the present application. Figure 2 and Figure 4 and the steps in the corresponding embodiments.

[0053] Through the description of the above embodiments, those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above division of functional modules is taken as an example. In actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0054] The functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0055] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application essentially or in other words the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a flash memory, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0056] Although the embodiments of the present application have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to the embodiments. However, it should be understood that such modifications and changes are within the scope and spirit of the present application as described in the claims. Moreover, the present application described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A method for monitoring and adjusting bandwidth of a video processing chip, applied to a bandwidth monitoring module corresponding to a sub-module, wherein the sub-module is used for processing a video data stream, and the method comprises the steps of: monitoring a bandwidth of the sub-module; determining a bandwidth of the sub-module; and adjusting the bandwidth of the sub-module according to the determined bandwidth. The method comprises: Real-time acquisition of a bandwidth monitoring signal of a sub-module; According to the bandwidth monitoring signal of the sub-module, a corresponding adjustment feedback loop is formed to adjust the clock frequency and the input image frame rate; According to the bandwidth monitoring signal of the sub-module, a corresponding adjustment feedback loop is formed to adjust the clock frequency and the input image frame rate, comprising: judging overflow according to the bandwidth monitoring signal and obtaining overflow condition; generating an adjustment signal according to the overflow condition, the adjustment signal being used to adjust the clock frequency and the input image frame rate; When the sub-module is a video stream module, judging overflow according to the bandwidth monitoring signal and obtaining overflow condition, generating an adjustment signal according to the overflow condition, the adjustment signal being used to adjust the clock frequency and the input image frame rate, comprising: counting bus activity according to bus activity in the bandwidth monitoring signal, and generating an overflow signal and an underflow signal in real time according to the overflow threshold and the underflow threshold when each horizontal synchronization signal in the field active area arrives, the overflow signal and the underflow signal being counted by a counter, a software interrupt or a hardware adjustment signal being generated in the field blanking area, and the clock frequency and the input image frame rate being adjusted in real time; When an overflow signal is generated, the adjustment signal is used to reduce the sub-module clock frequency, lengthen the row blanking area length, lengthen the field blanking area length, reduce the video stream clock frequency, increase the clock frequency of the arbiter and the shared memory module, and generate an overflow software interrupt; When an underflow signal is generated, the adjustment signal is used to increase the sub-module clock frequency, reduce the row blanking area length, reduce the field blanking area length, increase the video stream clock frequency, reduce the clock frequency of the arbiter and the shared memory module, and generate an underflow software interrupt.

2. The method of claim 1, wherein, Generating an overflow signal and an underflow signal in real time according to the overflow threshold and the underflow threshold, the overflow signal and the underflow signal being counted by a counter, comprising: When the horizontal synchronization signal is greater than the row signal overflow threshold, a row overflow signal is generated, and the row overflow signal is counted by a counter to obtain an overflow count; When the horizontal synchronization signal is less than the row signal underflow threshold, a row underflow signal is generated, and the row underflow signal is counted by a counter to obtain an underflow count.

3. The method of claim 1, wherein, When the sub-module is a non-video stream module, judging overflow according to the bandwidth monitoring signal and obtaining overflow condition, generating an adjustment signal according to the overflow condition, comprising: According to bus activity in the bandwidth monitoring signal, bus activity is counted in units of image frames to count bus activity in a complete frame processing time, a bus activity counter synchronization signal being a signal pulse indicating that the sub-module starts working and completes work, being cleared when the sub-module starts working, and generating an overflow signal and an underflow signal when the sub-module completes work.

4. A video processing chip bandwidth monitoring and regulating apparatus, characterized in that, The device comprises: An acquisition unit configured to acquire a bandwidth monitoring signal of a sub-module in real time; An adjustment unit configured to form a corresponding adjustment feedback loop according to the bandwidth monitoring signal of the sub-module to adjust the clock frequency and the input image frame rate; The adjusting unit forms a corresponding adjusting feedback loop according to the bandwidth monitoring signal of the sub-module to adjust the clock frequency and the input image frame rate, specifically for: judging overflow according to the bandwidth monitoring signal and obtaining overflow condition; generating an adjusting signal according to the overflow condition, the adjusting signal being used to adjust the clock frequency and the input image frame rate; When the sub-module is a video stream module, the overflow is judged according to the bandwidth monitoring signal, and the overflow condition is obtained, and the adjusting signal is generated according to the overflow condition, the adjusting signal being used to adjust the clock frequency and the input image frame rate, specifically for: counting the bus activity according to the bus activity in the bandwidth monitoring signal, and generating an overflow signal and an underflow signal in real time according to the overflow threshold and the underflow threshold when each horizontal synchronization signal in the field active area arrives, the overflow signal and the underflow signal being counted by a counter, a software interrupt or a hardware adjusting signal being generated in the field blanking area, and the clock frequency and the input image frame rate being adjusted in real time; When the overflow signal is generated, the adjusting signal is used to reduce the sub-module clock frequency, lengthen the row blanking area length, lengthen the field blanking area length, reduce the video stream clock frequency, increase the clock frequency of the arbiter and the shared memory module, and generate an overflow software interrupt; When the underflow signal is generated, the adjusting signal is used to increase the sub-module clock frequency, reduce the row blanking area length, reduce the field blanking area length, increase the video stream clock frequency, reduce the clock frequency of the arbiter and the shared memory module, and generate an underflow software interrupt.

5. The apparatus of claim 4, wherein, The adjusting unit generates an overflow signal and an underflow signal in real time according to the overflow threshold and the underflow threshold, and the overflow signal and the underflow signal are counted by a counter, specifically for: When the horizontal synchronization signal is greater than the row signal overflow threshold, a row overflow signal is generated, and the row overflow signal is counted by a counter to obtain an overflow count; When the horizontal synchronization signal is less than the row signal underflow threshold, a row underflow signal is generated, and the row underflow signal is counted by a counter to obtain an underflow count.

6. The apparatus of claim 4, wherein, When the sub-module is a non-video stream module, the adjusting unit judges overflow according to the bandwidth monitoring signal and obtains overflow condition, and generates an adjusting signal according to the overflow condition, specifically for: According to the bus activity in the bandwidth monitoring signal, the bus activity is counted in units of image frames to count the bus activity count in the processing of a complete frame, the bus activity counter synchronization signal being a signal pulse indicating that the sub-module starts working and completes work, being cleared when the sub-module starts working, and generating an overflow signal and an underflow signal when the sub-module completes work.

7. An electronic device, comprising: It comprises: a processor and a memory, the memory being used to store a computer program; the processor being used to execute the computer program stored in the memory to enable the electronic device to execute the method in any one of claims 1 to 3.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to implement the method in any one of claims 1 to 3.

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