Video processing apparatus

Abstract

The utility model discloses a video processing device, which comprises a processor and a plurality of video processing chips, and the processor is connected with the plurality of video processing chips through a PCIE switch chip. According to the utility model, the plurality of video processing chips carry out parallel processing on the video code stream, so that the processing performance of the multi-channel video can be improved, and the video processing performance of the video processing equipment can be improved when the operand of the video code stream is large.

Description

TECHNICAL FIELD

[0001] The utility model relates to video processing technical field especially, is related to a kind of video processing equipment. BACKGROUND

[0002] With the development of video processing technology, video processing technology is widely applied in various industries, such as Internet, security monitoring, broadcast television, etc.

[0003] In the prior art, video processing technology includes encoding and decoding, image detection and identification. The processor includes fixed encoding module, decoding module and AI (Artificial Intelligence) module. The encoding module and the decoding module are used for transcoding processing of received code stream, and the AI module is used for detecting and identifying the transcoded video stream to extract important target information.

[0004] However, due to the single nature of the fixed encoding module, decoding module and AI module in the processor, the performance of the processor for video processing is limited. When the operation amount of the video code stream is large, the performance of the processor for video processing is poor. UTILITY MODEL CONTENT

[0005] One of the technical problems to be solved by the embodiments of the utility model is to improve the product traceability effectiveness of the video processing equipment.

[0006] In a first aspect, the application provides a video processing device, which comprises a processor and a plurality of video processing chips, wherein:

[0007] The processor is connected to the plurality of video processing chips through a PCIE switch chip.

[0008] In one embodiment, the processor is disposed on a main circuit board, and the processor includes a PCIE interface. The main circuit board further includes a PCIE card slot.

[0009] In one embodiment, the PCIE switch chip includes a first PCIE switch chip and a second PCIE switch chip.

[0010] The first PCIE switch chip is disposed on the main circuit board, and the second PCIE switch chip is disposed on the video processing circuit board.

[0011] In one embodiment, the upstream port of the first PCIE switch chip is connected to the PCIE interface of the processor, and the downstream port of the first PCIE switch chip is connected to the PCIE card slot.

[0012] In one of the embodiments, the upstream port of the second PCIE switch chip is connected with the PCIE card slot through a golden finger, and the downstream port of the second PCIE switch chip is connected with the plurality of video processing chips.

[0013] In one of the embodiments, the PCIE switch chip comprises a first PCIE switch chip.

[0014] The first PCIE switch chip is arranged on a main circuit board, the upstream port of the first PCIE switch chip is connected with the PCIE interface of the processor, and the downstream port of the first PCIE switch chip is connected with the plurality of video processing chips.

[0015] In one of the embodiments, the PCIE switch chip comprises a second PCIE switch chip, and the main circuit board further comprises a PCIE card slot.

[0016] The second PCIE switch chip is arranged on a video processing circuit board, and the PCIE interface of the processor is connected with the PCIE card slot.

[0017] The upstream port of the PCIE switch chip is connected with the PCIE card slot through a golden finger, and the downstream port of the PCIE switch chip is connected with the plurality of video processing chips.

[0018] In one of the embodiments, the processor comprises at least two PCIE interfaces, and each PCIE interface is connected with a PCIE switch chip.

[0019] In one of the embodiments, the video processing circuit board comprises a PCIE switch and at least two video processing chips.

[0020] In one of the embodiments, the processor comprises a network interface, a universal serial bus interface, an inter-integrated circuit bus interface, a general-purpose input / output interface, a universal asynchronous receiver / transmitter interface, a multimedia interface and a PCIE interface.

[0021] The video processing device comprises a processor and a plurality of video processing chips, wherein the processor is connected with the plurality of video processing chips through a PCIE switch chip.

[0022] The technical scheme of the present application will be further described in detail below with reference to the drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings, which form a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0024] The present application can be understood more clearly with reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0025] Figure 1 is a structural schematic view of a video processing device in one embodiment;

[0026] Figure 2 is a structural schematic view of a two-level PCIE switch chip structure of a video processing device in one embodiment. DETAILED DESCRIPTION

[0027] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. Note that the relative arrangement, numerical expressions, and numerical values of components and steps set forth in these embodiments are not limiting to the scope of the present application unless otherwise specifically stated.

[0028] It should also be understood that the size of the various portions shown in the drawings is not intended to be limiting, and that the size of the various portions can be exaggerated or reduced to facilitate description.

[0029] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are merely intended to facilitate the description of the present application and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more. In the description of the present application, it should be noted that, unless otherwise specifically stated and limited, the terms "mounting", "connection", and "connection" should be interpreted broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0030] The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the present application or its application or uses.

[0031] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art can not be discussed in any detail since they can be readily understood from the following description and are considered part of the present description.

[0032] It is to be noted that like reference numerals and letters refer to like items in the following figures, and as a result, once an item is defined in one figure, it need not be discussed further in subsequent figures.

[0033] In one embodiment, as shown in FIG. 1, a video processing device (100) is provided, which comprises a processor (101) and a plurality of video processing chips (102), wherein: Figure 1

[0034] The processor (101) is connected with the plurality of video processing chips (102) through a PCIE switch chip (103).

[0035] In the present embodiment, video processing technology is widely used in Internet live broadcast, security monitoring, broadcast television and other fields. Video processing technology mainly includes video coding and decoding, image detection and recognition, etc. After the original video is collected by a camera, it will be encoded into a specific code stream format, and then transmitted to the server through the network. After receiving the video code stream, the video processing device (100) of the server can use the video processing device (100) to transcode (decode and then encode) the video code stream according to the business needs, so as to convert it into the code stream format required by the business, or perform detection, recognition and other processing on the decoded image to extract important target information. For example, in the Internet live broadcast scenario, users upload video streams in real time, and after the video processing device (100) receives the video code stream from the network, it transcodes the video code stream through the video processing chip (102) to adapt to different network environments and devices, and at the same time, the video processing device (100) performs content recognition and audit on the video code stream according to the video processing chip (102).

[0036] When there are many video code streams accessed and the operation amount is large, in order to improve the performance and scalability of video processing, the video processing device (100) connects the PCIE switch chip (103) through the PCIE (Peripheral Component Interconnect Express, Peripheral Component Interconnect Express) interface, which expands the processor (101) with a plurality of video processing chips (102) for processing multiple video code streams.

[0037] ​Specifically, the processor (101) is connected to the PCIE switch chip (103) through a PCIE interface, and the PCIE switch chip (103) is responsible for distributing the video stream received by the processor (101) to each video processing chip (102). Each video processing chip (102) can be responsible for processing a part of the video stream of the same user, that is, decoding, encoding, image detection and identification, etc. on a part of the video stream of the same user, or each video processing chip (102) can process the video stream of different users respectively, that is, decoding, encoding, image detection and identification, etc. on the video stream of different users respectively. After video processing, the video processing chip (102) returns the video processing result to the processor (101) through the same PCIE path. The processor (101) can store the video processing result in the hard disk according to the business demand, display it on the display or send it to the next stage device through the network for further processing.

[0038] The video processing device (100) can improve the overall processing performance of the video processing device (100) by applying the PCIE switch chip (103) to enable the processor (101) to distribute tasks to multiple video processing chips (102), and each video processing chip (102) is responsible for processing part of the video stream. Secondly, the PCIE switch chip (103) can establish a low-delay communication channel between the processor (101) and the multiple video processing chips (102), ensuring that the video stream can be quickly distributed and processed, avoiding data accumulation and delay, and the PCIE switch chip (103) can distribute video stream data to different video processing chips (102) according to the instructions of the processor (101), and then the processor (101) can evenly distribute tasks to multiple video processing chips (102), avoiding the situation that some video processing chips (102) are overloaded while other video processing chips (102) are idle, achieving load balancing of the video processing device (100), thereby improving the overall processing efficiency of the video processing device (100).

[0039] The above-mentioned video processing device includes a processor (101) and multiple video processing chips (102), wherein the processor (101) is connected to the multiple video processing chips (102) through a PCIE switch chip (103). By using the utility model, the video stream is processed in parallel by multiple video processing chips (102), which can improve the processing performance of multiple video streams, and then when the operation amount of the video stream is large, the performance of the video processing device (100) for video processing can be improved.

[0040] In one embodiment, the processor (101) is disposed on the main circuit board (104), the processor (101) includes a PCIE interface (1011), and the main circuit board (104) further includes a PCIE card slot (105).

[0041] In the embodiment, the processor (101) can be disposed on the main circuit board (104), the processor (101) is generally integrated with a PCIE controller, supports a PCIE protocol, that is, the processor (101) has a PCIE interface (1011). The PCIE interface (1011) is a high-speed serial bus standard, used for connecting the processor (101) and the video processing chip (102). The main circuit board (104) is further designed with the PCIE card slot (105) for inserting a PCIE device (for example, the PCIE switch chip (103)), wherein the processor (101) can be connected with the PCIE switch chip (103) through the PCIE interface (1011), and connected with the PCIE card slot (105) through the PCIE switch chip (103), or directly connected with the plurality of video processing chips (102) through the PCIE switch chip (103). Alternatively, the PCIE interface (1011) in the processor (101) can also be directly connected with the PCIE card slot (105), and connected with the PCIE switch chip (103) through the PCIE card slot (105), and connected with the plurality of video processing chips (102) through the PCIE switch chip (103), thereby realizing the communication between the processor (101) and the plurality of video processing chips (102) through the PCIE switch chip (103).

[0042] The PCIE card slot (105) can be directly connected with the PCIE interface (1011) of the processor (101) through the wiring on the main circuit board (104), or the PCIE interface (1011) is connected with the PCIE card slot (105) through the PCIE switch chip (103). The PCIE card slot (105) supports the hot plug and the plug and play function, facilitating the expansion and maintenance of the video processing device (100).

[0043] The PCIE switch chip (103) is used for expanding the number of PCIE interfaces (1011) in the processor (101), allowing the processor (101) to be connected with the plurality of video processing chips (102) through one PCIE interface (1011), and the PCIE switch chip (103) is responsible for the distribution and routing of the video code stream, ensuring that the video code stream can be efficiently transmitted between the processor (101) and the plurality of video processing chips (102).

[0044] In one embodiment, as Figure 2As shown, the PCIE switch chip (103) includes a first PCIE switch chip (1031) and a second PCIE switch chip (1032).

[0045] The first PCIE switch chip (1031) is disposed on the main circuit board (104), and the second PCIE switch chip (1032) is disposed on the video processing circuit board (106).

[0046] In the embodiment, the PCIE switch chip (103) in the video processing device (100) can be used to realize the communication between the processor (101) and the video processing chip (102) in a two-level structure. Specifically, the first PCIE switch chip (1031) is disposed in the main circuit board (104) and is used to expand the PCIE interface (1011) in the processor (101) to improve the number of PCIE devices (for example, the second PCIE switch chip (1032)) connected to the processor (101); the second PCIE switch chip (1032) is disposed on the video processing circuit board (106) and is used to further expand each downstream interface of the first PCIE switch chip (1031) to further improve the number of video processing chips (102) that can be finally connected to the processor (101).

[0047] In an exemplary embodiment, if the PCIE interface (1011) of the processor (101) has only one PCIE x 16 interface, the first PCIE switch chip (1031) can expand the PCIE x 16 interface into multiple PCIE x 8 interfaces, and each PCIE x 8 interface of the first PCIE switch chip (1031) is connected to the second PCIE switch chip (1032) in a different video processing circuit board (106). For each downstream interface of the first PCIE switch chip (1031), if the downstream interface of the first PCIE switch chip (1031) is a PCIE x 8 interface, the second PCIE switch chip (1032) can expand the PCIE x 8 interface of the downstream interface of the first PCIE switch chip (1031) into multiple PCIE x 4 interfaces, and each PCIE x 4 interface of the second PCIE switch chip (1032) is connected to the video processing chip (102) in the video processing circuit board (106).

[0048] In the fact example, through the two-stage architecture of the first PCIE switch chip (1031) and the second PCIE switch chip (1032), the number of PCIE interfaces (1011) of the processor (101) in the video processing device (100) is expanded to a large number, and the performance of the video processing device (100) for processing multiple video code streams is improved. At the same time, different video processing chips (102) can be special video processing chips for processing different video code streams, and thus the code stream format that the processor (101) can support can be expanded. Secondly, the two-stage architecture of the first PCIE switch chip (1031) and the second PCIE switch chip (1032) can realize that the video processing device (100) can flexibly allocate bandwidth according to business needs, and more bandwidth can be allocated to the video processing chip (102) that needs high bandwidth, and lower bandwidth can be allocated to other video processing chips (102).

[0049] In one embodiment, as shown in FIG. 1, the upstream port of the first PCIE switch chip (1031) is connected with the PCIE interface (1011) of the processor (101), and the downstream port of the first PCIE switch chip (1031) is connected with the PCIE card slot. Figure 2

[0050] In the embodiment of the present application, the upstream port of the first PCIE switch chip (1031) is connected with the PCIE interface (1011) of the processor (101) through the wiring of the main circuit board (104), and the downstream port of the first PCIE switch chip (1031) is connected with the PCIE card slot (105) through the wiring of the main circuit board (104).

[0051] In one embodiment, the upstream port of the second PCIE switch chip (1032) is connected with the PCIE card slot (105) through the gold finger, and the downstream port of the second PCIE switch chip (1032) is connected with the multiple video processing chips (102).

[0052] ​In the embodiment of the present application, the second PCIE switch chip (1032) is arranged on the video processing circuit board (106), and the upstream port of the second PCIE switch chip (1032) is connected with the golden finger (not shown in the figure) of the video processing circuit board (106). The golden finger is located at the edge of the video processing circuit board (106) and is a row of exposed contacts, which is used to contact the PCIE card slot (105) in the main circuit board (104) to establish electrical connection between the first PCIE switch chip (1031) in the main circuit board (104) and the second PCIE switch chip (1032) in the video processing circuit board (106).

[0053] In the video processing circuit board (106), the downstream port of the second PCIE switch chip (1032) is connected with the PCIE pin of each video processing chip (102), so as to realize the connection between the video processing chip (102) and the processor (101) through the first PCIE switch chip (1031) and the second PCIE switch chip (1032).

[0054] In one embodiment, the PCIE switch chip (103) includes the first PCIE switch chip (1031);

[0055] The first PCIE switch chip (1031) is arranged on the main circuit board (104), the upstream port of the first PCIE switch chip (1031) is connected with the PCIE interface (1011) of the processor (101), and the downstream port of the first PCIE switch chip (1031) is connected with the plurality of video processing chips (102).

[0056] In the embodiment of the present application, the video processing device (100) can also be arranged with only the first PCIE switch chip (1031) on the main circuit board (104). In the main circuit board (104), the upstream port of the first PCIE switch chip (1031) is connected with the PCIE interface (1011) of the processor (101) through the wiring of the main circuit board (104), and the downstream port of the first PCIE switch chip (1031) is connected with the plurality of video processing chips (102) in the main circuit board (104) through the wiring of the main circuit board (104).

[0057] In an optional embodiment, the downstream port of the first PCIE switch chip (1031) (103) can also be connected with the PCIE card slot (105) through the wiring of the main circuit board (104), and connected with the single video processing chip (102) in the video processing circuit board (106) through the PCIE card slot (105), so as to realize the connection between the processor (101) and the video processing chip (102) in the multiple video processing circuit boards (106).

[0058] In an embodiment, the PCIE switch chip (103) comprises a second PCIE switch chip (103), and the main circuit board further comprises a PCIE card slot;

[0059] The second PCIE switch chip (1032) is arranged in the video processing circuit board, and the PCIE interface (1011) of the processor (101) is connected with the PCIE card slot (105);

[0060] The upstream port of the second PCIE switch chip (1032) is connected with the PCIE card slot through the gold finger, and the downstream port of the second PCIE switch chip (1032) is connected with the multiple video processing chips (102).

[0061] In the embodiment, the video processing device (100) can also only arrange the second PCIE switch chip (1032) in the video processing circuit board (106). In the main circuit board (104), the PCIE interface (1011) of the processor (101) is directly connected with the PCIE card slot (105) through the wiring of the main circuit board (104), and then the upstream port of the second PCIE switch chip (1032) in the video processing circuit board (106) is connected with the gold finger of the video processing circuit board (106) through the wiring of the video processing circuit board (106), and the gold finger of the video processing circuit board (106) is contacted with the PCIE card slot (105) in the main circuit board (104), so as to connect the processor (101) with the second PCIE switch chip (1032). The downstream port of the second PCIE switch chip (1032) is connected with the multiple video processing chips (102) through the wiring of the video processing circuit board (106), so as to realize the communication between the processor (101) and the multiple video processing chips (102).

[0062] In an embodiment, the processor (101) comprises at least two PCIE interfaces (1011), and each PCIE interface (1011) is connected with a PCIE switch chip (103) respectively.

[0063] In the embodiments of the present application, the processor (101) in the main circuit board (104) has at least two PCIE interfaces (1011), each of which can be directly connected with a PCIE switch chip (103). The PCIE switch chip (103) can include a first PCIE switch chip (1031) and a second PCIE switch chip (1032) and form a two-level structure, or the PCIE switch chip (103) can only include an independent first PCIE switch chip (1031) or an independent second PCIE switch chip (1032).

[0064] In one embodiment, the video processing circuit board (106) includes the PCIE switch (103) and at least two video processing chips (102).

[0065] In one embodiment, as shown in Figure 2 the processor (101) includes a PCIE interface (1011), a network interface (1012), a universal serial bus interface (1013), an inter-integrated circuit bus interface (1014), a general-purpose input / output interface (1015), a universal asynchronous receiver / transmitter interface (1016), and a multimedia interface (1017).

[0066] In this embodiment, the processor (101) in the main circuit board (104) has a plurality of peripheral ports, including a network interface, a universal serial bus interface, an inter-integrated circuit bus interface, a general input / output interface, a universal asynchronous receiver / transmitter interface, a multimedia interface and a PCIE interface. Among them, the network interface can be a GMAC (Gigabit Ethernet MAC (Media Access Control) Interface), which is connected with a PHY (Physical Layer Interface) through the wiring of the main circuit board (104), and the PHY is connected with an RJ45 (Registered Jack 45, Ethernet network interface); the universal serial bus interface can be a USB3.0 (Universal Serial Bus), which is connected with a USB-to-SATA (Serial Advanced Technology Attachment hard disk) element, and the USB-to-SATA element is connected with a SATA interface; the inter-integrated circuit bus interface can be an I2C (Inter-Integrated Circuit), which is connected with a clock / calendar chip, and the clock / calendar chip is connected with a button cell; the general input / output interface can be a GPIO (General Purpose Input / Output), which is connected with a key and an indicator element; the universal asynchronous receiver / transmitter interface can be a UART (Universal Asynchronous Receiver / Transmitter), which is connected with a debugging serial port; the multimedia interface can be an HDMI (High-Definition Multimedia Interface), which is connected with a port (display port).

[0067] For the video processing result processed by the video processing chip (102), the video processing chip (102) returns the video processing result to the processor (101) along the original PCIE path, and the processor can store the video processing result to the SATA hard disk connected with the SATA interface through the USB3.0 and the USB-to-SATA element, or transmit the video processing result to a display through the HDMI, or send the video processing result to a next device for further processing through the GMAC.

[0068] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties.

[0069] It can be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing related hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiments of each method. Any reference to memory, database or other medium used in the embodiments provided by the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided by the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided by the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0070] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between each embodiment can be referred to each other.

[0071] The description is given for the purpose of exemplification and description only and is not intended to be exhaustive or to limit the application to the precise form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. Embodiments were chosen and described in order to best explain the principles of the application and its practical application and to thereby enable others skilled in the art to best utilize the application, as well as various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A video processing device, comprising: The video processing device comprises a processor and a plurality of video processing chips, wherein: The processor is connected with the plurality of video processing chips through a PCIE switch chip.

2. The video processing device of claim 1, wherein, The processor is arranged on a main circuit board, and the processor comprises a PCIE interface, and the main circuit board further comprises a PCIE card slot.

3. The video processing device of claim 2, wherein, The PCIE switch chip comprises a first PCIE switch chip and a second PCIE switch chip. The first PCIE switch chip is arranged on the main circuit board, and the second PCIE switch chip is arranged on a video processing circuit board.

4. The video processing device of claim 3, wherein, The upstream port of the first PCIE switch chip is connected with the PCIE interface of the processor, and the downstream port of the first PCIE switch chip is connected with the PCIE card slot.

5. The video processing device of claim 3, wherein, The upstream port of the second PCIE switch chip is connected with the PCIE card slot through a golden finger, and the downstream port of the second PCIE switch chip is connected with the plurality of video processing chips.

6. The video processing device of claim 1, wherein, The PCIE switch chip comprises a first PCIE switch chip; The first PCIE switch chip is arranged on a main circuit board, and the upstream port of the first PCIE switch chip is connected with the PCIE interface of the processor, and the downstream port of the first PCIE switch chip is connected with the plurality of video processing chips.

7. The video processing device of claim 1, wherein, The PCIE switch chip comprises a second PCIE switch chip, and the main circuit board further comprises a PCIE card slot; The second PCIE switch chip is arranged on a video processing circuit board, and the PCIE interface of the processor is connected with the PCIE card slot; The upstream port of the second PCIE switch chip is connected with the PCIE card slot through a golden finger, and the downstream port of the second PCIE switch chip is connected with the plurality of video processing chips.

8. The video processing device of claim 2, wherein, The processor comprises at least two PCIE interfaces, and each PCIE interface is connected with a PCIE switch chip.

9. The video processing device of claim 3, wherein, The video processing circuit board comprises a PCIE switch and at least two video processing chips.

10. The video processing device of claim 1, wherein, The processor comprises a network interface, a universal serial bus interface, an inter-integrated circuit bus interface, a general-purpose input / output interface, a universal asynchronous receiver / transmitter interface, a multimedia interface and a PCIE interface.

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