Method of manufacturing a capacitive array

Abstract

A method of fabricating a capacitor array. The method includes depositing a sacrificial layer on a bottom electrode; depositing an insulating layer on the sacrificial layer; forming a polysilicon hard mask on the insulating layer; etching the insulating layer and the sacrificial layer exposed through a plurality of openings in the polysilicon hard mask to form a plurality of channels; depositing a metal film on the polysilicon hard mask and in the channels; depositing a passivation film on the metal film; performing a first removal process to remove portions of the passivation film and the metal film over the polysilicon hard mask; performing a second removal process to remove portions of the polysilicon hard mask exposed through the passivation film and the metal film; performing a third removal process to remove the polysilicon hard mask and portions of the passivation film and the metal film surrounding the polysilicon hard mask; removing the passivation film and the metal film from the insulating layer and the sacrificial layer; depositing a conductive material in the channels and in contact with the insulating layer and the sacrificial layer; removing the sacrificial layer; and forming a top electrode on the insulating layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Applications Nos. 17 / 584,567 and 17 / 584,636 (i.e., priority date "January 26, 2022"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a method for processing a substrate. In particular, it relates to a method for patterning a substrate, the substrate comprising oxide and nitride layers. Background Technology

[0003] The semiconductor industry has developed an ultra-fine technique for providing patterns on the nanometer scale. This ultra-fine technique benefits from efficient lithography. Typical lithography involves applying a material layer onto a semiconductor substrate, coating a photoresist layer onto the material layer, exposing and developing the photoresist layer to provide a photoresist pattern, and using the photoresist pattern as a mask to etch the material layer.

[0004] When minimizing the pattern to be formed, it may be difficult to provide a fine pattern with the desired contour using only the typical lithography techniques described above. Therefore, a layer referred to herein as a hard mask can be formed to provide a fine pattern between the material layer to be etched and the photoresist layer. The hard mask acts as an intermediate layer that transfers the fine pattern of the photoresist to the material layer through a selective etching process. Therefore, the hard mask layer needs to be chemically resistant, heat-resistant, and etch-resistant to withstand various types of etching processes.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One aspect of this disclosure provides a method for processing a substrate. The method includes the following steps: providing a substrate including a sacrificial layer and an insulating layer stacked on the sacrificial layer; forming a polysilicon hard mask on the insulating layer; etching the insulating layer and the sacrificial layer through a plurality of openings in the polysilicon hard mask to expose the insulating layer and the sacrificial layer to form a plurality of channels; depositing a metal film on the polysilicon hard mask and in the channels; depositing a passivation film on the metal film; performing a first removal process to remove a portion of the passivation film and the metal film located above the polysilicon hard mask; performing a second removal process to remove a portion of the polysilicon hard mask exposed through the passivation film and the metal film; and performing a third removal process to remove the polysilicon hard mask and the portions of the passivation film and the metal film surrounding the polysilicon hard mask.

[0007] In some embodiments, the passivation film comprises an oxide and protects the insulating layer and the sacrificial layer from removal during the first, second, and third removal processes.

[0008] In some embodiments, the first removal process uses a process gas comprising a mixture of boron trichloride (BCl3), chlorine (Cl2), and carbon tetrafluoride (CF4).

[0009] In some embodiments, the ratio of boron trichloride (BCl3) to chlorine (Cl2) to carbon tetrafluoride (CF4) is 2:1:1.

[0010] In some embodiments, the first removal process is performed at a pressure of 50 millitor.

[0011] In some embodiments, the second removal process uses boron trichloride (BCl3) and chlorine (Cl2) as reaction gases.

[0012] In some embodiments, the ratio of boron trichloride (BCl3) to chlorine (Cl2) is 1:1.

[0013] In some embodiments, the second removal process is performed at a pressure of 10 millitor.

[0014] In some embodiments, the second removal process uses hydrogen bromide (HBr) as the reaction gas.

[0015] In some embodiments, the second removal process is performed at a pressure of 50 to 80 millitor.

[0016] In some embodiments, the second removal process is performed at a power of 1500 watts, a bias voltage of 200 volts, and a duty cycle of 50%.

[0017] In some embodiments, the third removal process uses chlorine (Cl2), oxygen (O2), and carbon tetrafluoride (CF4) as reaction gases.

[0018] In some embodiments, the ratio of chlorine (Cl2) to oxygen (O2) to carbon tetrafluoride (CF4) is 20:1:1.

[0019] In some embodiments, the third removal process is performed at a pressure of less than 20 millitor.

[0020] In some embodiments, the metal film comprises a refractory metal and a nitride.

[0021] One aspect of this disclosure is a method for fabricating a capacitor array. The method includes: depositing a sacrificial layer on a bottom electrode; depositing an insulating layer on the sacrificial layer; forming a polysilicon hard mask on the insulating layer; etching the insulating layer and the sacrificial layer through a plurality of openings in the polysilicon hard mask to expose the insulating layer and the sacrificial layer to form a plurality of channels; depositing a metal film on the polysilicon hard mask and in the channels; depositing a passivation film on the metal film; performing a first removal process to remove a portion of the passivation film and the metal film on the polysilicon hard mask; performing a second removal process to remove a portion of the polysilicon hard mask exposed through the passivation film and the metal film; performing a third removal process to remove the polysilicon hard mask and a portion of the passivation film and the metal film surrounding the polysilicon hard mask; removing the passivation film and the metal film from the insulating layer and the sacrificial layer; depositing a conductive material in the channels and in contact with the insulating layer and the sacrificial layer; removing the sacrificial layer; and forming a top electrode on the insulating layer.

[0022] In some embodiments, during the first removal process, horizontal portions of the passivation film and the metal film located on a topmost surface of the bottom electrode and the polysilicon hard mask are removed.

[0023] In some embodiments, the passivation film comprises an oxide and protects the insulating layer and the sacrificial layer from removal during the first, second, and third removal processes.

[0024] In some embodiments, the first removal process uses a process gas comprising a mixture of boron trichloride (BCl3), chlorine (Cl2), and carbon tetrafluoride (CF4).

[0025] In some embodiments, the ratio of boron trichloride (BCl3) to chlorine (Cl2) to carbon tetrafluoride (CF4) is 2:1:1.

[0026] In some embodiments, the first removal process is performed at a pressure of 50 millitor.

[0027] In some embodiments, the second removal process uses boron trichloride (BCl3) and chlorine (Cl2) as reaction gases.

[0028] In some embodiments, the ratio of boron trichloride (BCl3) to chlorine (Cl2) is 1:1.

[0029] In some embodiments, the second removal process is performed at a pressure of 10 millitor.

[0030] In some embodiments, the second removal process uses hydrogen bromide (HBr) as the reaction gas.

[0031] In some embodiments, the second removal process is performed at a pressure of 50 to 80 millitor.

[0032] In some embodiments, the second removal process is performed at a power of 1500 watts, a bias voltage of 200 volts, and a duty cycle of 50%.

[0033] In some embodiments, the third removal process uses chlorine (Cl2), oxygen (O2), and carbon tetrafluoride (CF4) as reaction gases.

[0034] In some embodiments, the ratio of chlorine (Cl2) to oxygen (O2) to carbon tetrafluoride (CF4) is 20:1:1.

[0035] In some embodiments, the third removal process is performed at a pressure of less than 20 millitor.

[0036] In some embodiments, the metal film comprises a refractory metal and a nitride.

[0037] In some embodiments, the passivation film is removed earlier than the metal film.

[0038] By using the above configuration of patterning a multi-layered substrate with a hard mask, the hard mask on the patterned substrate can be removed by an in-situ removal process, thereby reducing the possibility of contamination and saving processing time.

[0039] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure. Attached Figure Description

[0040] This disclosure can be read in conjunction with the following figures and detailed description for better understanding. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of each feature may be arbitrarily enlarged or reduced.

[0041] Figure 1 to Figure 1C A flowchart of a method for fabricating a capacitor array is shown according to some embodiments of this disclosure.

[0042] Figures 2 to 22 A cross-sectional view of an intermediate stage in forming a capacitor array is shown according to some embodiments of this disclosure.

[0043] The reference numerals in the attached figures are explained as follows:

[0044] 10: Capacitor Array

[0045] 102: Array area

[0046] 104: Outer Area

[0047] 110: Bottom electrode

[0048] 120: First insulating layer

[0049] 122: First insulating block

[0050] 130: First conductive component

[0051] 140: Air gap

[0052] 150: Second insulation layer

[0053] 152: Second insulating block

[0054] 160: Second conductive component

[0055] 170: Air gap

[0056] 180: Top electrode

[0057] 190: Second Channel

[0058] 200: First Channel

[0059] 210: First Sacrifice Layer

[0060] 212: First Sacrificial Block

[0061] 220: First polycrystalline silicon layer

[0062] 222: First polysilicon hard mask

[0063] 224: First Opening

[0064] 226: Top surface

[0065] 230: Component Pattern

[0066] 232: Window

[0067] 233: First metal film

[0068] 234: First metal liner

[0069] 240: First passivation film

[0070] 242: First passivation liner

[0071] 250: Second Sacrificial Layer

[0072] 252: Second Sacrificial Block

[0073] 260: Second polysilicon layer

[0074] 262: Second polysilicon hard mask

[0075] 264: Second opening

[0076] 270: Second metal film

[0077] 272: Second metal liner

[0078] 280: Second passivation film

[0079] 282: Second passivation liner

[0080] 400: Method

[0081] S402: Steps

[0082] S404: Steps

[0083] S406: Steps

[0084] S408: Steps

[0085] S410: Steps

[0086] S412: Steps

[0087] S414: Steps

[0088] S416: Steps

[0089] S418: Steps

[0090] S420: Steps

[0091] S422: Steps

[0092] S424: Steps

[0093] S426: Steps

[0094] S428: Steps

[0095] S430: Steps

[0096] S432: Steps

[0097] S434: Steps

[0098] S436: Steps

[0099] S438: Steps

[0100] S440: Steps

[0101] S442: Steps

[0102] S444: Steps

[0103] T1: First thickness

[0104] T2: Second thickness

[0105] W1: First width

[0106] W2: Second width Detailed Implementation

[0107] The embodiments or examples of this disclosure shown in the drawings are described below using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the embodiments, and any further application of the principles set forth herein, are to be regarded as normal occurrences by those skilled in the art related to this disclosure. Reference numerals may be repeated in all embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they use the same reference numerals.

[0108] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited to these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part.

[0109] The terms used herein are for the purpose of describing particular example embodiments only and are not intended to limit the concepts of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” also include the plural forms. It should be understood that the terms “comprises” and “comprising” as used in this specification indicate the presence of said components, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more components, integers, steps, operations, elements, components, or combinations thereof.

[0110] Figures 1A to 1C A flowchart of a method 400 for fabricating a capacitor array 10 is shown according to some embodiments of this disclosure. Figures 2 to 22 According to some embodiments of this disclosure, cross-sectional schematic diagrams are shown of various fabrication stages constructed according to the fabrication method 400 of the capacitor array 10. Figures 2 to 22 The stages shown are also schematically illustrated in... Figures 1A to 1C In the flowchart. In the subsequent discussion, Figures 2 to 22 The preparation stages shown will refer to Figures 1A to 1C The process steps shown will be discussed.

[0111] Reference Figure 2 ,according to Figure 1A In step S402, a bottom electrode 110 is provided, and a first sacrificial layer 210, a first insulating layer 120, and a first polysilicon layer 220 are stacked on the bottom electrode 110. Figure 2 As shown, a first sacrificial layer 210 covers the bottom electrode 110, and a first insulating layer 120 is sandwiched between the first sacrificial layer 210 and the first polysilicon layer 220. The bottom electrode 110 comprises a highly conductive material to ensure fast device speeds. The first sacrificial layer 210, comprising oxide, has a first thickness T1, and the second thickness T2 of the first insulating layer 120 is less than the first thickness T1.

[0112] The first sacrificial layer 210 is blanket-deposited on the bottom electrode 110 using chemical vapor deposition (CVD), physical vapor deposition (PVD), or spin-on processes. For example, a first insulating layer 120 comprising a nitride (e.g., silicon nitride) is deposited using a CVD or PVD process to conformally cover the first sacrificial layer 210. The fabrication technique for the first polysilicon layer 220 may include a low-pressure chemical vapor deposition (LPCVD) process. In some embodiments, a planarization process may be performed on the first insulating layer 120 prior to the deposition of the first polysilicon layer 220 to produce an acceptable flat topology.

[0113] Subsequently, a feature pattern 230 is applied to the first polysilicon layer 220. The feature pattern 230 may comprise various materials depending on the material of the etched layer (i.e., the polysilicon layer) to be etched and the purpose of the pattern. The feature pattern 230 may be formed in a preceding etching process that forms a plurality of windows 232 having a first width W1 within the feature pattern 230 by removing material from areas exposed to one or more etchants. The windows 232 are located within an array region 102 surrounded by a peripheral region 104 and expose portions of the first polysilicon layer 220 to be subsequently etched.

[0114] Reference Figure 3 ,according to Figure 1AIn step S404, the portion of the first polysilicon layer 220 not covered by the component pattern 230 is removed to form a plurality of first openings 224. As a result, a first polysilicon hard mask 222 is generated. Using a known etching process, such as anisotropic plasma etching, the component pattern 230 is transferred to the first polysilicon layer 220. The first polysilicon hard mask 222 is formed using the component pattern 230 as a mask.

[0115] like Figure 3 As shown, the first opening 224 has a second width W2, which is the same as the first width W1 of the window 232 in the component pattern 230. Typically, the purpose of the first polysilicon hard mask 222 is to faithfully reproduce the component pattern 230 on the first insulating layer 120 and the first sacrificial layer 210. That is, the opening 224 exposes portions of the first insulating layer 120 and the first sacrificial layer 210 that will subsequently be etched. After the first polysilicon hard mask 222 is formed, the component pattern 230 is completely removed using, for example, an etching process, a chemical mechanical polishing (CMP) process, or a similar process.

[0116] Reference Figure 4 ,according to Figure 1A In step S406, portions of the first insulating layer 120 and the first sacrificial layer 210 not covered by the first polysilicon hard mask 222 are removed to form a plurality of first channels 200. The first channels 200 can be formed in various ways. In some embodiments, the first channels 200 can be generated in an etching process using a variety of etchants selected based on the materials of the first insulating layer 120 and the first sacrificial layer 210, to sequentially etch the first insulating layer 120 and the first sacrificial layer 210 until a portion of the bottom electrode 110 is exposed. The etching process may consume a portion of the first polysilicon hard mask 222. Because the etching rate is related to the component size, and a larger component size corresponds to a larger etching rate, the remaining first polysilicon hard mask 222 in the array region 102 and the peripheral region 104 have inconsistent thicknesses.

[0117] Reference Figure 5 ,according to Figure 1AIn steps S408 and S410, a first metal film 233 and a first passivation film 240 are sequentially deposited on the first polysilicon hard mask 222 and in the first opening 224 and the first channel 200. The first metal film 233 (such as titanium nitride (TiN)) is conformally deposited on the first polysilicon hard mask 222 above the bottom electrode 110. The first opening 224 exposes a portion of the polysilicon hard mask 222, and the first channel 200 exposes a portion of the remaining first insulating layer (hereinafter referred to as "first insulating block 122") and the remaining first sacrificial layer (hereinafter referred to as "first sacrificial block 212"). Thus, the first metal film 233 has a topology such as the first polysilicon hard mask 222, the first insulating block 122, the first sacrificial block 212, and the bottom electrode 110. The first passivation film 240 is deposited on the first metal film 233 in a blanket manner. The first metal film 233 and the first passivation layer 240 have substantially the same thickness. The fabrication technology of the first metal film 233 may include PVD process or atomic layer deposition (ALD) process, and the fabrication technology of the first passivation film 240 (including oxide) may include ALD process.

[0118] Reference Figure 6 ,according to Figure 1A In step S412, a first removal process is performed to remove a portion of the first metal film 233 and the first passivation film 240 located above the first polysilicon hard mask 222. As a result, the top surface 226 of the first polysilicon hard mask 222 is exposed. In some embodiments, an isotropic etching process is performed to remove the horizontal portions of the first passivation film 240 and the first metal film 233 located on the bottom electrode 110 and the top surface 226 of the first polysilicon hard mask 222, while the vertical portions of the first metal film 233 and the first passivation film 240 remain on the portion of the first sacrificial block 212 and the first insulating block 122 exposed to the first channel 200 and on the first polysilicon hard mask 222 exposed to the first opening 224, thereby forming a plurality of first metal substrates 234 and a plurality of first passivation substrates 242 on the sidewalls of the first sacrificial block 212, the first insulating block 122, and the first polysilicon hard mask 222.

[0119] The first removal process can be performed using a process gas at a pressure of 50 mTorr, the process gas comprising a mixture of boron trichloride (BCl3), chlorine (Cl2), and carbon tetrafluoride (CF4) applied to the horizontal portions of the first passivation film 240 and the first metal film 233. In some embodiments, the ratio of boron trichloride to chlorine to carbon tetrafluoride is, for example, 2:1:1.

[0120] Reference Figure 7 Subsequently, according to Figure 1AIn step S414, a second removal process is performed to remove a portion of the first polysilicon hard mask 222 exposed to the first metal substrate 234 and the first passivation substrate 242. In some embodiments, boron trichloride and chlorine can be used as reactant gases to perform the second removal process at a pressure of 50 mTorr. Alternatively, the ratio of boron trichloride to chlorine may be, for example, 1:1. Alternatively, hydrogen bromide (HBr) can be used as the reactant gas to perform the second removal process at a pressure of 50 to 80 mTorr, a power of 1500 watts, a bias voltage of 200 volts, and 50% load cycling. During the second removal process, the first polysilicon hard mask 222 is recessed, so that the top surface 226 of the first polysilicon hard mask 222 is no longer a flat surface. Since the exposed area of ​​the first polysilicon hard mask 222 in the peripheral region 104 is larger than the exposed area in the array region 102, the recess depth of the first polysilicon hard mask 222 in the peripheral region 104 is greater than the recess depth in the array region. Therefore, the uneven thickness of the first polysilicon hard mask 222 can be reduced.

[0121] Reference Figure 8 ,according to Figure 1A In step S416, a third removal process is performed to remove the portion of the first polysilicon hard mask 222 and the portions of the first metal substrate 234 and the first passivation substrate 242 surrounding the first polysilicon hard mask 222. The third removal process is performed using oxygen (O2), chlorine, and carbon tetrafluoride as reaction gases at a pressure of less than 20 mTorr (e.g., 10 mTorr). In some embodiments, the ratio of oxygen to chlorine to carbon tetrafluoride is, for example, 1:20:1. During the third removal process, the first polysilicon hard mask 222 is completely removed from the first insulating block 122. It is noteworthy that the first, second, and third removal processes can be performed in situ to save process time and reduce the possibility of contamination. As used herein, "in situ" means a process in which the treated layer or film is not exposed to the external surrounding environment (e.g., outside the processing system).

[0122] Reference Figure 9 After the third removal process, according to Figure 1B Step S418 then removes the first passivation liner 242 and the first metal liner 234 used to protect the first insulating block 122 and the first sacrificial block 212 from etching. The first passivation liner 242 and the first metal liner 234 are removed using, for example, a wet etching process. Since the first sacrificial block 212 and the first passivation liner 242 have the same material (e.g., oxide), the first passivation liner 242 can be removed before the first metal liner 234 is removed.

[0123] Reference Figure 10 ,according to Figure 1BIn step S420, a first conductive material is deposited in the first channel 200. The first conductive material (including tungsten) is uniformly deposited to fill the first channel 200 and cover the first insulating block 122 until the first channel 200 is completely filled. Next, a planarization process, including a CMP process, is performed on the first conductive material until the first insulating block 122 is exposed. This forms a plurality of first conductive components 130 parallel to each other. In cross-sectional view, each first conductive component 130 may have a linear structure.

[0124] After the planarization process, the top surface of the first conductive component 130 and the top surface of the first insulating block 122 are flush with each other. The aspect ratio of the first conductive component 130 can be in the range of 42:1 to 45:1. (Refer to...) Figure 2 and Figure 11 The aspect ratio of the first conductive component 130 can be adjusted by controlling the first width W1 of the component pattern 230, the first thickness T1 of the first sacrificial layer 210, and the second thickness T2 of the first insulating layer 120.

[0125] Reference Figure 11 ,according to Figure 1B In step S422, the first sacrificial block 212 is removed. As a result, the space previously occupied by the first sacrificial block 212 remains as an air gap 140. From the cross-sectional view, each air gap 140 containing ambient gas (such as air) may have a linear structure extending parallel to the first conductive component 130. The first sacrificial block 212 can be removed using a stripping process and / or a wet etching process.

[0126] Reference Figure 12 ,according to Figure 1B In step S424, a second sacrificial layer 250, a second insulating layer 150, and a second polysilicon layer 260 are sequentially formed on the first insulating block 122 and the first conductive component 130. The second sacrificial layer 250 is conformally deposited to cover the first insulating block 122 and the first conductive component 130. The second sacrificial layer 250, comprising oxide, can be blanket-formed onto the first insulating block 122 and the first conductive component 130 using a process (such as a CVD process), although any acceptable process can be used to form a second sacrificial layer 250 of a predetermined thickness. The second sacrificial layer 250 may comprise oxide, and the second sacrificial layer 250 may comprise the same material as the first sacrificial layer 210.

[0127] A second insulating layer 150 is deposited on the second sacrificial layer 250 to conformally cover the second sacrificial layer 250. A second insulating layer 150 comprising a dielectric material is formed on the second sacrificial layer 250 using a CVD process. The second insulating layer 150 may include a nitride. Furthermore, the first insulating layer 120 and the second insulating layer 150 may have the same material.

[0128] A second polysilicon layer 260 is deposited to cover the second insulating layer 150. In some embodiments, the fabrication technique of the second polysilicon layer 260 may include the same technique used with the first polysilicon layer 220 (e.g., ...). Figure 2 (As shown) the same process.

[0129] Then, the component pattern 230 is used as a mask to pattern the second polysilicon layer 260, thereby forming a plurality of second openings 264. The component pattern 230 is used as a mask for patterning the second polysilicon layer 260; therefore, a second polysilicon hard mask 262 is formed, as shown. Figure 13 As shown. The thicknesses of the second polysilicon layer 260, the second insulating layer 150, and the second sacrificial layer 250 can be adjusted so that each of these layers has sufficient thickness during the respective etching process (discussed below) to protect the first conductive component 130.

[0130] Then, the method proceeds to step S426, removing portions of the second insulating layer 150 and the second sacrificial layer 250 exposed to the second polysilicon hard mask 262; thereby forming a plurality of second channels 190 to expose portions of the first conductive component 130, such as... Figure 14 As shown.

[0131] Reference Figure 15 ,according to Figure 1B In step S428, a second metal film 270 is formed on the second polysilicon hard mask 262 and the first conductive component 130, as well as in the second opening 264 and the second channel 190. The thickness of the second metal film 270 on the second polysilicon hard mask 262 and the first conductive component 130 is the same as its thickness in the second opening 264 and the second channel 190. That is, the second metal film 270 does not completely fill the second opening 264 and the second channel 190. The second metal film 270 has a topology such as that of the second polysilicon hard mask 262, the second insulating block 152, the second sacrificial block 252, and the first conductive component 130. In some embodiments, the second metal film 270 is a refractory metal nitride film. The second metal film 270 can be formed using a PVD process or an ALD process.

[0132] Then, the method proceeds to step S430, forming a second passivation film 280 to cover the second metal film 270. The second passivation film 280 has a substantially uniform thickness and comprises an oxide-based material, and the fabrication technology of the second passivation film 280 includes an ALD process.

[0133] Reference Figure 16 ,according to Figure 1BIn step S432, a first removal process is performed to remove portions of the second passivation film 280 and the second metal film 270, thereby forming a plurality of second metal substrates 272 and a plurality of second passivation substrates 282. In some embodiments, an isotropic etching process is used to remove portions of the second passivation film 280 and the second metal film 270 above the horizontal portions of the first conductive component 130 and the second polysilicon hard mask 262.

[0134] Because the thicknesses of the second passivation film 280 are different over the horizontal portions of the first conductive component 130 and the second polysilicon hard mask 262, the second passivation liner 282 remains along the sidewalls of the second metal film 270. Similarly, anisotropic etching is performed on the second metal film 270 to remove the horizontal portions attached to the first conductive component 130 and the second polysilicon hard mask 262, and the second metal liner 272 still remains along the sidewalls of the second polysilicon hard mask 262, the second insulating block 152, and the second sacrificial block 252. The first removal process uses a reactive gas comprising boron trichloride, chlorine, and carbon tetrafluoride to etch the second passivation film 280 and the second metal film 270 at a pressure of 50 mTorr.

[0135] Then, the method proceeds to step S434, as follows: Figure 17 As shown, a second removal process is performed to recess the exposed second polysilicon hard mask 262, thereby improving the thickness uniformity of the second polysilicon hard mask 262 in array region 102 and peripheral region 104. In some embodiments, the second removal process uses a reactive gas composed of boron trichloride and chlorine to etch the exposed portion of the second polysilicon hard mask 262 at a pressure of 50 mTorr. Furthermore, the ratio of boron trichloride to chlorine is, for example, 1:1. In an alternative embodiment, the second removal process uses hydrogen bromide as the reactive gas to recess the exposed second polysilicon hard mask 262 at a pressure of 50 to 80 mTorr, a power of 1500 watts, a bias voltage of 200 volts, and 50% load cycling.

[0136] Reference Figure 18 ,according to Figure 1C Step S436 of the process performs a third removal process to remove the second polysilicon hard mask 262. During the removal of the second polysilicon hard mask 262, portions of the second passivation liner 282 and the second metal liner 272 surrounding the second polysilicon hard mask 262 are simultaneously removed. The third removal process can completely remove the second polysilicon hard mask 262 using a mixture of oxygen, chlorine, and carbon tetrafluoride at a pressure of 10 mTorr. In some embodiments, the ratio of oxygen to chlorine to carbon tetrafluoride is, for example, 1:20:1.

[0137] Reference Figure 19 After removing the second polysilicon hard mask 262, in Figure 1CIn step S438, the second passivation liner 282 and the second metal liner 272 are removed from the second insulating block 152 and the second sacrificial block 252. This exposes the entire top surface of the first conductive component 130. The second metal liner 272 and the second passivation liner 282 are removed using a wet etching process. In some embodiments, the second metal liner 272 may be removed after the second passivation liner 282 has been completely removed.

[0138] Reference Figure 20 ,according to Figure 1C In step S440, a second conductive material is deposited in the second channel 190. The first and second conductive materials can be metallic materials, such as tungsten. The second conductive material can be uniformly deposited to fill the second channel 190 and cover the second insulating block 152 until the second channel 190 is completely filled. Next, a planarization process, including a CMP process, is performed on the second conductive material until the second insulating block 152 is exposed. This forms a plurality of second conductive components 160 parallel to each other. The second conductive components 160 are respectively connected to the first conductive component 130. After the planarization process, the top surfaces of the second conductive components 160 and the top surfaces of the second insulating block 152 are flush with each other.

[0139] Reference Figure 21 ,according to Figure 1C In step S442, the second sacrificial block 252 is removed. As a result, the space previously occupied by the second sacrificial block 252 remains as an air gap 170. Each air gap 170 containing an ambient gas (such as air) extends between the first insulating block 122 and the second insulating block 152, and the second conductive components 160 are spaced apart from each other by a predetermined distance. The second sacrificial block 252 can be removed using a stripping process and / or a wet etching process.

[0140] Reference Figure 22 ,according to Figure 1C In step S444, a top electrode 180 is formed on the second insulating block 152 and the second conductive component 160. Therefore, the capacitor array 10 is formed. The top electrode 180 may comprise a low-resistivity metallic material.

[0141] like Figure 22 As shown, the capacitor array 10 includes a bottom electrode 110, a top electrode 180, a first insulating block 122, a second insulating block 152, a plurality of first conductive components 130, a plurality of second conductive components 160, and a plurality of air gaps 140 and 170. The top electrode 180 is spaced apart from the bottom electrode 110, and the first insulating block 122 is located between the bottom electrode 110 and the top electrode 180. The first conductive components 130 extend from the bottom electrode 110 into the first insulating block 122. The second insulating block 152 is attached to the top electrode 180, and the second conductive components 160 extend from the first conductive components 130 into the second insulating block 152.

[0142] Air gap 140 extends between bottom electrode 110 and first insulating block 122, and between first conductive members 130 spaced a predetermined distance apart. Air gap 170 extends between first insulating block 122 and second insulating block 152, and between second conductive member 160. Air gaps 140 and 170 contain ambient gas (such as air).

[0143] The bottom electrode 110 may comprise at least one of a doped semiconductor material (e.g., doped silicon), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, and / or tantalum), and a conductive metal oxide (e.g., iridium oxide). The top electrode 180 covering the second insulating block 152 and the second conductive component 160 may comprise the same material as the bottom electrode 110. Alternatively, the top electrode 180 may comprise a different conductive material than the bottom electrode 110. The first insulating block 122 connecting the first conductive component 130 and the second insulating block 152 connecting the second conductive component 160 comprise nitrides.

[0144] In summary, by including a method of patterning a substrate using polysilicon hard masks 222 / 262 on a substrate, the substrate including nitride insulating blocks 122 and 152 and oxide sacrificial blocks 212 and 252, the polysilicon hard masks 222 / 262 on the insulating blocks 122 and the patterned insulating blocks 152 can be removed by performing the first to third removal processes in situ, thus reducing the possibility of contamination and saving processing time.

[0145] One aspect of this disclosure provides a method for processing a substrate. The method includes the following steps: providing a substrate including a first insulating layer and a second insulating layer stacked on the first insulating layer; forming a polysilicon hard mask on the second insulating layer; etching the first insulating layer and the second insulating layer through at least one opening in the polysilicon hard mask; conformally depositing a metal film and a passivation film on the second insulating layer and the polysilicon hard mask and in the opening; performing a removal process to remove horizontal portions of the passivation film and the metal film to expose the polysilicon hard mask; and performing a dry etching process using an etchant comprising boron trichloride and chlorine to remove the polysilicon hard mask.

[0146] One aspect of this disclosure provides a method for fabricating a capacitor array. The method includes the following steps: forming a bottom electrode; depositing a first insulating layer on the bottom electrode; depositing a second insulating layer on the first insulating layer; forming a polysilicon hard mask on the second insulating layer; etching the first insulating layer and the second insulating layer through at least one opening in the polysilicon hard mask; conformally depositing a metal film and a passivation film on the second insulating layer and the polysilicon hard mask and in the opening; performing a removal process to remove horizontal portions of the passivation film and the metal film to expose the polysilicon hard mask; and performing a dry etching process using an etchant comprising boron trichloride and chlorine to remove the polysilicon hard mask.

[0147] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0148] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a capacitor array, comprising: A sacrificial layer is deposited on a bottom electrode; An insulating layer is deposited on the sacrificial layer; A polycrystalline silicon hard mask is formed on the insulating layer; Etching exposes the insulating layer and the sacrificial layer through multiple openings in the polysilicon hard mask to form multiple channels; A metal film is deposited on the polycrystalline silicon hard mask and in the plurality of channels; A passivation film is deposited on the metal film; A first removal process is performed to remove a portion of the passivation film and the metal film above the polysilicon hard mask; A second removal process is performed to remove the portion of the polysilicon hard mask exposed through the passivation film and the metal film; A third removal process is performed to remove the polysilicon hard mask and a portion of the passivation film and the metal film surrounding the polysilicon hard mask; Remove the passivation film and the metal film from the insulating layer and the sacrificial layer; A conductive material is deposited in the plurality of channels and in contact with the insulating layer and the sacrificial layer; Remove the sacrifice layer; as well as A top electrode is formed on the insulating layer.

2. The method for fabricating a capacitor array as claimed in claim 1, wherein during the first removal process, horizontal portions of the passivation film and the metal film located on a topmost surface of the bottom electrode and the polysilicon hard mask are removed.

3. The method for fabricating a capacitor array as claimed in claim 1, wherein the passivation film comprises an oxide and protects the insulating layer and the sacrificial layer from being removed during the first removal process, the second removal process, and the third removal process.

4. The method for fabricating a capacitor array as claimed in claim 1, wherein the first removal process uses a process gas comprising a mixture of boron trichloride (BCl3), chlorine (Cl2), and carbon tetrafluoride (CF4).

5. The method for preparing the capacitor array as described in claim 4, wherein the ratio of boron trichloride (BCl3) to chlorine (Cl2) to carbon tetrafluoride (CF4) is 2:1:

1.

6. The method for fabricating a capacitor array as described in claim 4, wherein the first removal process is performed at a pressure of 50 millitor.

7. The method for preparing a capacitor array as described in claim 1, wherein the second removal process uses boron trichloride (BCl3) and chlorine (Cl2) as reaction gases.

8. The method for preparing the capacitor array as described in claim 7, wherein the ratio of boron trichloride (BCl3) to chlorine (Cl2) is 1:

1.

9. The method for fabricating a capacitor array as claimed in claim 7, wherein the second removal process is performed at a pressure of 10 millitor.

10. The method for preparing a capacitor array as claimed in claim 1, wherein the second removal process uses hydrogen bromide (HBr) as a reaction gas.

11. The method for fabricating a capacitor array as claimed in claim 10, wherein the second removal process is performed at a pressure between 50 and 80 millitors.

12. The method of fabricating a capacitor array as claimed in claim 10, wherein the second removal process is performed under a power of 1500 watts, a bias voltage of 200 volts, and a load cycle of 50%.

13. The method for preparing a capacitor array as claimed in claim 1, wherein the third removal process uses chlorine (Cl2), oxygen (O2), and carbon tetrafluoride (CF4) as reaction gases.

14. The method for preparing the capacitor array as described in claim 13, wherein the ratio of chlorine (Cl2) to oxygen (O2) to carbon tetrafluoride (CF4) is 20:1:

1.

15. The method for fabricating a capacitor array as claimed in claim 13, wherein the third removal process is performed at a pressure of less than 20 millitor.

16. The method for fabricating a capacitor array as claimed in claim 1, wherein the metal film comprises a nitride of a refractory metal.

17. The method for fabricating a capacitor array as claimed in claim 1, wherein the removal of the passivation film precedes the removal of the metal film.

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