Cutting semiconductor wafer camera system and method

Abstract

A semiconductor wafer imaging system for imaging a semiconductor wafer includes a shroud panel defining a black box, a camera positioned in the black box for imaging the semiconductor wafer, and an illumination panel for directing diffuse light to the semiconductor wafer. A portion of the diffuse light is reflected off the semiconductor wafer and the camera images the semiconductor wafer by detecting the reflected diffuse light.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 706,894, filed September 16, 2020, U.S. Provisional Patent Application No. 62 / 706,895, filed September 16, 2020, and U.S. Provisional Patent Application No. 62 / 706,897, filed September 16, 2020, the entire disclosures of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The field of the disclosure relates to imaging semiconductor substrates, and in particular, methods and systems for imaging diced wafers. BACKGROUND

[0004] Semiconductor wafers are commonly used to produce integrated circuit (IC) chips on which circuitry is printed. The circuitry is first printed in a miniaturized form onto the surface of a wafer, and then the wafer is broken down into circuit chips. During the process, the wafers are handled and polished so that the front and back surfaces of each wafer have a reflective, mirror-like surface. To reduce manufacturing costs, the wafers are also imaged during the process to detect defects on the surface of the wafers before further processing the wafers.

[0005] Some imaging systems used in quality control systems image articles by reflecting light off of the article and detecting the reflected light with a camera. The camera typically images the non-mirror surface of the article. However, because the surface of a wafer is mirror-like, the light directed to the wafer must be diffuse, uniform light. Otherwise, the image captured by the imaging system will be a reflected image of the light source, not the features of the wafer.

[0006] Furthermore, while some imaging systems image the reflective surface of a wafer, the imaging systems typically include a large parabolic mirror that increases the size of the imaging system and limits the locations in which the imaging system can be positioned within the process. Specifically, the parabolic mirror substantially increases the height and width of the imaging system. The imaging system can only be positioned in locations that have a large volume of space to accommodate the system. Suitable locations for the system can interrupt the process.

[0007] This section is intended to introduce the reader to various aspects of art that can be related to various aspects of the present disclosure that are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art. SUMMARY

[0008] One aspect of the disclosure relates to a semiconductor wafer imaging system for imaging a semiconductor wafer. The system includes a shroud panel defining a black box, a camera positioned in the black box for imaging the semiconductor wafer, and an illumination panel for directing diffuse light to the semiconductor wafer. A portion of the diffuse light is reflected off the semiconductor wafer and the camera images the semiconductor wafer by detecting the reflected diffuse light.

[0009] Another aspect of the disclosure relates to a black box for imaging a semiconductor wafer. The black box includes a shroud panel defining an upper chamber and a lower chamber. A support plate separates the upper chamber from the lower chamber. A bottom shroud panel at least partially defines the lower chamber and defines a wafer opening. The support plate defines a camera opening. The black box further includes a camera positioned in the upper chamber for imaging the semiconductor wafer and an illumination panel for directing diffuse light to the semiconductor wafer. The diffuse light is transmitted to the semiconductor wafer through the wafer opening and a portion of the diffuse light is reflected off the semiconductor wafer through the wafer opening and the camera opening. The camera images the semiconductor wafer by detecting the reflected diffuse light.

[0010] Yet another aspect of the disclosure relates to a semiconductor wafer processing system for processing a semiconductor wafer. The system includes a semiconductor wafer processing station for processing the semiconductor wafer and a semiconductor wafer imaging system for imaging the semiconductor wafer after the semiconductor wafer processing station processes the semiconductor wafer. The semiconductor wafer imaging system includes a shroud panel defining a black box, a camera positioned in the black box for imaging the semiconductor wafer, and an illumination panel for directing diffuse light to the semiconductor wafer. A portion of the diffuse light is reflected off the semiconductor wafer and the camera images the semiconductor wafer by detecting the reflected diffuse light.

[0011] Yet another aspect of the disclosure relates to a semiconductor wafer processing system for processing semiconductor wafers. The system includes a first manufacturing line for processing a first semiconductor wafer and including a first semiconductor wafer processing station for processing the first semiconductor wafer. The system further includes a second manufacturing line for processing a second semiconductor wafer and including a second semiconductor wafer processing station for processing the second semiconductor wafer. The second manufacturing line intersects the first manufacturing line at a common location. The system further includes a semiconductor wafer imaging system for imaging the first and second semiconductor wafers and positioned within the common location where the first and second manufacturing lines intersect. The semiconductor wafer imaging system images the first and second semiconductor wafers after the first and second semiconductor wafer processing stations process the first and second semiconductor wafers. The semiconductor wafer imaging system includes a shroud panel defining a black box, a camera positioned in the black box for imaging the semiconductor wafer, and an illumination panel for directing diffuse light to the semiconductor wafer. Portions of the diffuse light are reflected off the semiconductor wafer and the camera images the semiconductor wafer by detecting the reflected diffuse light.

[0012] Yet another aspect of the disclosure relates to a semiconductor wafer imaging station of a semiconductor wafer processing system for imaging a semiconductor wafer. The station includes a frame, a positioning plate attached to the frame, and a black box movably attached to the positioning plate. The black box includes a shroud panel defining the black box, a camera positioned in the black box for imaging the semiconductor wafer, and an illumination panel for directing diffuse light to the semiconductor wafer. Portions of the diffuse light are reflected off the semiconductor wafer and the camera images the semiconductor wafer by detecting the reflected diffuse light. The station further includes an end effector for positioning the semiconductor wafer within a field of view of the camera.

[0013] Yet another aspect of the disclosure relates to a method of detecting defects on a semiconductor wafer. The method includes directing diffuse light to the semiconductor wafer and reflecting the diffuse light off the semiconductor wafer. The method further includes detecting the diffuse light with a camera to produce an image of the semiconductor wafer and analyzing the image to detect defects on the semiconductor wafer.

[0014] Yet another aspect of the disclosure relates to a method of processing a semiconductor wafer. The method includes cutting the semiconductor wafer in a cutting station, positioning the semiconductor wafer within a field of view of a camera, and directing diffuse light to the semiconductor wafer. The method further includes reflecting the diffuse light off the semiconductor wafer, detecting the diffuse light with the camera to generate an image of the semiconductor wafer, and analyzing the image to detect defects on the semiconductor wafer.

[0015] Yet another aspect of the disclosure relates to a method of processing a semiconductor wafer using a semiconductor wafer processing system. The semiconductor wafer processing system includes a processing station and a semiconductor wafer imaging station. The method includes processing the semiconductor wafer in the processing station, positioning the semiconductor wafer within a field of view of a camera of the semiconductor wafer imaging station, and directing diffuse light to the semiconductor wafer. The method further includes reflecting the diffuse light off the semiconductor wafer, detecting the diffuse light with the camera to generate an image of the semiconductor wafer, and analyzing the image to detect defects on the semiconductor wafer.

[0016] Yet another aspect of the disclosure relates to a method of processing a semiconductor wafer using a semiconductor wafer processing system. The semiconductor wafer processing system includes a first manufacturing line, a second manufacturing line, and a semiconductor wafer imaging station positioned within a common location at an intersection of the first and second manufacturing lines. The first and second manufacturing lines each include a processing station for processing the semiconductor wafer. The method includes i) processing a first semiconductor wafer in the processing station of the first manufacturing line, ii) positioning the first semiconductor wafer within a field of view of a camera of the semiconductor wafer imaging station, and iii) directing diffuse light to the first semiconductor wafer. The method further includes iv) reflecting the diffuse light off the first semiconductor wafer, v) detecting the diffuse light with the camera to generate an image of the first semiconductor wafer, and vi) analyzing the image to detect defects on the first semiconductor wafer. The method further includes vii) processing a second semiconductor wafer in the processing station of the second manufacturing line, and viii) repeating steps ii-vi to image the second semiconductor wafer.

[0017] Various improvements exist with respect to the features mentioned above. Further features can also be incorporated into the aspects described above. These improvements and additional features can exist individually or in any combination. For instance, various features discussed below with respect to any of the illustrated embodiments can be incorporated into any of the aspects described above, alone or in any combination. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a schematic diagram of a semiconductor wafer processing system.

[0019] Figure 2 is a schematic diagram of an alternative semiconductor wafer processing system.

[0020] Figure 3 is a perspective view of a semiconductor wafer imaging system positioned at a common location within a semiconductor wafer processing system of Figure 1 and 2 .

[0021] Figure 4 is another perspective view of a semiconductor wafer imaging system positioned at a common location within a semiconductor wafer processing system of Figure 1 and 2 .

[0022] Figure 5 is a perspective view of the semiconductor wafer imaging system shown in Figure 3 and 4 , with a transparent shroud.

[0023] Figure 6 is a cross-sectional view of the illumination panel shown in Figure 5 .

[0024] Figure 7 is a perspective view of the semiconductor wafer imaging system shown in Figure 5 , with the shroud removed.

[0025] Figure 8 is another perspective view of the semiconductor wafer imaging system shown in Figure 5 , with the shroud and structural components removed.

[0026] Figure 9 is a cross-sectional view of the semiconductor wafer imaging system shown in Figure 5 .

[0027] Figure 10 is another perspective view of the semiconductor wafer imaging system shown in Figure 5 , showing the filter with the shroud and structural components removed.

[0028] Figure 11 is another perspective view of the semiconductor wafer imaging system shown in Figure 3 and 4 , with an end effector positioner.

[0029] Figure 12 is another perspective view of the semiconductor wafer imaging system shown in Figure 3 and 4 , with an end effector positioner and an isolated end effector.

[0030] Figure 13is a schematic diagram of an image of a semiconductor wafer taken by the semiconductor wafer imaging system shown in Figure 3 and 4

[0031] Figure 14 is a schematic diagram of an image of a semiconductor wafer taken by the semiconductor wafer imaging system shown in Figure 3 and 4

[0032] Figure 15 is a raw fast Fourier transform (FFT) image of a semiconductor wafer generated by the controller.

[0033] Figure 16 is a schematic diagram of an output image of a semiconductor wafer generated by the controller.

[0034] Figure 17 is an output image of a semiconductor wafer generated by the controller.

[0035] Figure 18 is a diagram of a computer program for imaging and analyzing a semiconductor wafer.

[0036] Figures 19 to 21 is a flowchart of a method of imaging and analyzing a semiconductor wafer.

[0037] Figure 22 is a display used when calibrating the position of a wafer through an image analysis process.

[0038] Although specific features of each example can be shown in some figures and not in other figures, this is for convenience only. Any feature of any figure can be referenced and / or claimed in combination with any feature of any other figure.

[0039] Unless otherwise indicated, the figures are intended to illustrate features of examples of the present disclosure. These features are believed to be applicable in a wide array of systems comprising one or more examples of the present disclosure. The figures are not intended to include all conventional features of a system known to those of ordinary skill in the art to practice the disclosed examples of the present disclosure. DETAILED DESCRIPTION

[0040] ​​Semiconductor wafers, which can be referred to as semiconductor or silicon "wafers" or "substrates," are typically fabricated from single ingots (e.g., silicon ingots) formed by a crystal growth process that are sliced into individual wafers. Suitable crystal growth processes include the Czochralski process, the float zone process, the hydrothermal process, the Bridgeman process, the Kyropoulos process, and / or any other crystal growth process. While reference will be made herein to semiconductor wafers composed of silicon, other materials can also be used to fabricate semiconductor wafers, such as germanium, silicon carbide, silicon germanium, gallium arsenide, and other alloys of Group III and Group V elements (such as gallium nitride or indium phosphide), or alloys of Group II and Group VI elements (such as cadmium sulfide or zinc oxide). Each semiconductor wafer includes a central axis, a front surface, and a back surface parallel to the front surface. The front and back surfaces are generally perpendicular to the central axis. A circumferential edge joins the front and back surfaces.

[0041] Semiconductor wafers can be used to fabricate composite layer structures. Composite layer structures, such as semiconductor-on-insulator, and more specifically, silicon-on-insulator (SOI) structures, generally include a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, composite layer structures such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz are created by placing two wafers in close contact, thereby initiating bonding by van der Waal's forces, followed by a heat treatment to strengthen the bond. Annealing can convert terminal silanol groups to siloxane bonds between the two interfaces, thereby strengthening the bond.

[0042] After thermal annealing, the bonded structure is subjected to further processing to remove a substantial portion of the donor wafer to achieve layer transfer. For example, a common method of achieving layer transfer utilizes hydrogen implantation followed by a thermal-induced layer splitting. Particles (atoms or ionized atoms, e.g., hydrogen atoms or a combination of hydrogen atoms and helium atoms) are implanted at a specified depth below the front surface of the donor wafer. The implanted particles form a cleaving plane in the donor wafer at the specified depth at which they were implanted. The surface of the donor wafer is cleaned to remove organic compounds or other contaminants (such as boron compounds) deposited on the wafer during the implantation process.

[0043] The front surface of the donor wafer is then bonded to the handle wafer through a hydrophilic bonding process to form a bonded wafer. Prior to bonding, the donor wafer and / or the handle wafer are activated by exposing the surface of the wafer to a plasma containing, for example, oxygen or nitrogen. Exposure to the plasma modifies the structure of the surface in a process commonly referred to as surface activation, which makes the surface of one or both of the donor wafer and the handle wafer hydrophilic. The surface of the wafer can additionally be chemically activated through a wet treatment, such as an SC1 clean or hydrofluoric acid. The wet treatment and plasma activation can occur in either order, or the wafer can be subjected to only one treatment. The wafers are then pressed together, and a bond is formed between them. This bond is relatively weak due to van der Waals forces, and must be strengthened before further processing can occur.

[0044] In some processes, the hydrophilic bond between the donor wafer and the handle wafer (i.e., the bonded wafer) is strengthened by heating the bonded wafer pair or annealing the bonded wafer pair. In some processes, wafer bonding can occur at low temperatures (e.g., between about 300°C to 500°C). In some processes, wafer bonding can occur at high temperatures (e.g., between about 800°C to 1100°C). The high temperature causes the formation of covalent bonds between the adjoining surfaces of the donor wafer and the handle wafer, thereby solidifying the bond between the donor wafer and the handle wafer. While the bonded wafer is being heated or annealed, the particles previously implanted in the donor wafer weaken the cleave plane.

[0045] Portions of the donor wafer are then separated (i.e., cleaved) from the bonded wafer along the cleave plane to form an SOI wafer. Cleaving can be performed by placing the bonded wafer in a clamp in which a mechanical force is applied perpendicular to opposite sides of the bonded wafer to pull portions of the donor wafer away from the bonded wafer. According to some methods, a suction cup is used to apply the mechanical force. Separation of the portions of the donor wafer is initiated by applying a mechanical wedge at the edge of the bonded wafer at the cleave plane to initiate the propagation of a crack along the cleave plane. The mechanical force applied by the suction cup then pulls the portions of the donor wafer away from the bonded wafer, thereby forming an SOI wafer.

[0046] In one example, a semiconductor wafer imaging system images wafers during processing to detect defects in the wafers. After wafers have been diced to detect defects in the wafers formed during any upstream processing, including the dicing process, the imaging system images the wafers. If the semiconductor wafer imaging system detects a defect in a wafer, the wafer is removed from processing, thereby reducing wafer production costs. The wafers have a reflective, mirror-like surface, and the semiconductor wafer imaging system images the wafers without imaging the light source reflected off the reflective surface. Specifically, the semiconductor wafer imaging system includes a black box around a camera and an illumination panel. The black box minimizes reflections in the semiconductor wafer imaging system, and the illumination panel directs diffuse light toward the wafer. The diffuse light is reflected off the wafer toward the camera. The camera detects the reflected diffuse light, and the illumination panel is not imaged because the light produced by the illumination panel is diffuse. Thus, the camera images the wafer, not the light source, enabling a controller to analyze the wafer for defects and reduce processing costs.

[0047] Reference Figure 1 semiconductor wafer processing system 100 includes a manufacturing line 102 for manufacturing semiconductor wafers 104. The manufacturing line 102 includes semiconductor wafer processing stations 106 for processing the wafers 104. The processing stations 106 include a dicing station 108 and a semiconductor wafer imaging station or system 110 for imaging the wafers 104. In the illustrated embodiment, the imaging system 110 is positioned above the dicing station 108 to image the wafers 104 after they have been diced by the dicing station. The imaging system 110 images each wafer 104, and a controller 112 analyzes the images and detects defects in the wafers. If a wafer 104 includes a defect, the wafer is discarded before further processing, thereby reducing wafer production costs.

[0048] Reference Figure 2 semiconductor wafer processing system 114 includes two or more manufacturing lines 102 for manufacturing wafers 104. Similar to the processing system 100, each manufacturing line 102 includes processing stations 106 that include a dicing station 108. The manufacturing lines 102 also include a common location 116 at which the manufacturing lines intersect. The imaging system 110 is positioned at the common location 116 and images wafers 104 manufactured by all of the manufacturing lines 102 that intersect at the common location. In the illustrated embodiment, the processing system 114 includes two manufacturing lines 102. However, in alternative embodiments, the processing system 114 can include any number of manufacturing lines 102 that enable the processing system 114 to operate as described herein. Furthermore, in Figure 1 and 2In the illustrated embodiment, the imaging system 110 is positioned above or immediately downstream of the cutting station 108. In alternative embodiments, the imaging system 110 can be positioned at any location within the processing system 100 and 114 that enables the processing system to operate as described herein.

[0049] Referring to Figure 3 and 4 The imaging system 110 includes a black box 118, an end effector 120, and a positioning plate 122. As described below, the black box 118 includes a camera for imaging the wafer 104. The positioning plate 122 positions the black box 118 in the common location 116, and the end effector 120 positions the wafer 104 below the black box 118 for imaging. The positioning plate 122 is attached to a frame 124, and the black box 118 is movably attached to the positioning plate. The position of the black box 118 on the positioning plate 122 can be adjusted to adjust the position of the black box 118. Further, the end effector 120 can be moved relative to the black box 118 so that the position of the wafer 104 can be adjusted during imaging.

[0050] Referring to Figure 5 The shroud panels 126 define the black box 118. Specifically, the shroud panels 126 define an upper chamber 128 and a lower chamber 130. A support plate 132 is positioned within the black box 118 and separates the upper chamber 128 from the lower chamber 130. Further, a bottom shroud 134 defines a bottom 136 of the black box 118. The support plate 132 defines a support plate opening 138, and the bottom shroud 134 defines a bottom shroud opening 140. In the illustrated embodiment, both the support plate opening 138 and the bottom shroud opening 140 are circular, corresponding to the size and shape of the wafer 104. However, in alternative embodiments, the support plate opening 138 and the bottom shroud opening 140 are any shape that enables the imaging system 110 to operate as described herein. Further, the support plate opening 138 and the bottom shroud opening 140 are aligned so that the wafer 104 is visible through a direct, unobstructed line of sight 142 from the wafer to the upper chamber 128 when the wafer is positioned in the bottom shroud opening 140. The shroud panels 126 are suitably made of black anodized aluminum panels to minimize reflections in the black box 118. In alternative embodiments, the shroud panels 126 are made of any material that enables the black box 118 to operate as described herein.

[0051] The black box 118 includes an illumination panel 144 for directing diffuse light to the wafer 104. The illumination panel 144 is positioned in the lower chamber 130 and directs diffuse light through the bottom shroud opening 140 to the wafer 104 positioned in the bottom shroud opening. The diffuse light is then reflected off the wafer 104 through the support plate opening 138 and the bottom shroud opening 140 to the upper chamber 128. In the illustrated embodiment, the illumination panel 144 has a rectangular shape and the shape of the lower chamber 130 conforms to the shape of the illumination panel. In alternative embodiments, the illumination panel 144 can have any shape that enables the semiconductor wafer imaging system 110 to operate as described herein, including a circular shape and / or a polygonal shape.

[0052] Referring to Figure 6 The illumination panel 144 includes a frame 186, lights 188, and a transparent plate 190. The frame 186 has a rectangular shape to conform to the shape of the lower chamber 130. In the illustrated embodiment, the lights 188 are light emitting diode (LED) lights. In alternative embodiments, the lights 188 can be any type of light that enables the semiconductor wafer imaging system 110 to operate as described herein. The lights 188 are attached to the frame 186 such that the lights direct visible light through the transparent plate 190 in the horizontal direction 152. The transparent plate 190 includes a first edge 192, a second edge 194, a top face 196, a bottom face 198, and a reflector 200.

[0053] The lights 188 direct light into the first edge 192 of the transparent plate 190 and the light is directed through the bottom face 198 either out the second edge 194 or through the reflector 200. The lights 188 substantially surround the transparent plate 190 such that the visible light emitted by the lights is scattered throughout the transparent plate, traveling and reflecting in all directions parallel to the top and bottom faces 196 and 198. The visible light will remain within the transparent plate 190 until it is directed downward through the reflector 200. The top face 196 is textured with a regular geometric array of reflectors 200 to direct portions of the visible light emitted by the lights 188 downward through the bottom face 198. In the illustrated embodiment, the reflectors 200 include raised and / or recessed features (including holes and / or tabs) formed in the transparent plate 190 that reflect, diffuse, and / or scatter the visible light downward. For example, raised features formed in the transparent plate 190 can include tabs of pyramidal or conical shape extending from the transparent plate, and recessed features formed in the transparent plate 190 can include holes that allow portions of the reflected light to pass through. The raised features are not aligned with the recessed features such that reflections from the features do not interfere with each other. When visible light hits one of the reflectors 200, it is scattered or reflected downward so that it intersects the bottom face 198 at substantially normal incidence such that it is not internally reflected and exits the transparent plate 190. The reflectors 200 scatter the visible light so that it is directed downward as diffuse light toward the wafer 104.

[0054] Diffuse light is reflected upward from the wafer 104 back through the transparent plate 190. A portion of the reflected diffuse light is transmitted through the transparent plate 190 without hitting the reflector 200 and is imaged by the camera as described below. However, the reflected diffuse light that hits the reflector 200 is scattered or refracted such that the camera cannot image the scattered diffuse light, resulting in an array of dark spots on the image of the wafer 104.

[0055] The black box 118 also includes a camera 146 for imaging the wafer 104. The camera 146 includes a monochrome digital camera for taking a black digital photo of the wafer 104. The camera 146 is positioned in the upper chamber 128 and images the wafer 104 through the support plate opening 138 and the bottom shield opening 140. In the illustrated embodiment and as described below, the camera 146 is positioned proximate a mirror 148 that reflects light reflected off the wafer 104 to the camera. In alternative embodiments, the black box 118 does not include the mirror 148 and the camera 146 is positioned in the upper chamber 128 to directly image the wafer 104.

[0056] The black box 118 further includes a slide lock 150 attached to the camera 146 for positioning the camera in the upper chamber 128. The camera 146 is movably attached to the slide lock 150 for positioning and repositioning the camera in the upper chamber 128. Specifically, as Figure 5 and 7 As shown in FIG. 10, the slide lock 150 is oriented in a horizontal direction 152 and slides the camera 146 in the horizontal direction to focus the camera on the wafer 104. In alternative embodiments, the black box 118 does not include the mirror 148 and the slide lock 150 and the camera 146 are oriented in a vertical direction 154. The slide lock 150 slides the camera 146 in the vertical direction 154 to focus the camera on the wafer 104. In alternative embodiments, the camera 146 has an adjustable focus and the black box 118 does not include the slide lock 150.

[0057] The mirror 148 includes a planar mirror 156 attached to a mirror positioning system 158. The planar mirror 156 reflects diffuse light reflected off the wafer 104 to the camera 146 and the mirror positioning system 158 positions the planar mirror 156 in the upper chamber 128. The mirror 148 redirects the diffuse light reflected off the wafer 104 from the vertical direction 154 to the horizontal direction 152, enabling the camera 146 to be oriented in the horizontal direction and reducing the height 160 of the black box 118. Thus, the mirror 148 enables the semiconductor wafer imaging system 110 to be compact and positioned within the semiconductor wafer processing system 100.

[0058] The mirror positioning system 158 includes a base 162, a mirror holder 164, and a plurality of mirror screws 166. The mirror holder 164 is rotatably attached to the base 162, and the screws 166 attach the planar mirror 156 to the mirror holder. The screws 166 are rotated to adjust the angle a of the planar mirror 156 relative to the camera 146. Rotation of the screws 166 makes fine adjustments to the angle a. In alternative embodiments, the mirror positioning system 158 includes a slider similar to the slider lock 150.

[0059] The black box 118 can optionally include a filter 168 positioned in the upper chamber 128. The filter 168 can be a polarizing filter, a color filter, a high-pass filter, and / or any other type of filter that enables the imaging system 110 to operate as described herein. The filter 168 is positioned at a first location 170 on the camera 146, or a second location 172 above the support plate opening 138. The filter 168 creates a contrast between the wafer 104 and the surrounding environment, enabling the camera 146 to image the wafer. Specifically, the filter 168 reduces or eliminates reflections, enabling the camera 146 to image the wafer 104 rather than light or objects reflected through the wafer.

[0060] For example, if the filter 168 is a polarizing filter, the filter creates a contrast between the wafer 104 and the surrounding environment using polarization. As described above, the light emitted from the illumination panel 144 is diffused light that reflects off the mirror-like surface of the wafer 104 and back through the light emitted by the illumination panel. Any light reflected from other surfaces is reflected and scattered. Because the diffused, scattered light is not polarized and the reflected light is polarized, the filter 168 only allows the diffused light reflected off the wafer 104 to be transmitted. Reflections from surrounding surfaces are reduced or not transmitted to the camera 146. Reducing or eliminating reflections enables the camera 146 to image the wafer 104 rather than light or objects reflected through the wafer.

[0061] Similarly, if the filter 168 is a color filter, the filter creates a contrast between the wafer 104 and the surrounding environment based on the wavelengths of light reflected off the mirror-like surface of the wafer 104. The filter 168 selectively transmits different wavelengths of light. For example, the filter 168 can only transmit long wavelengths (long pass), only short wavelengths (short pass), or a band of wavelengths, blocking both longer and shorter wavelengths (band pass). Reflections from surrounding surfaces can have a predetermined wavelength, and the filter 168 reduces or eliminates reflections by absorbing light within the predetermined wavelength. Reducing or eliminating reflections enables the camera 146 to image the wafer 104 rather than light or objects reflected through the wafer.

[0062] Further, if filter 168 is a high-pass filter, the filter creates a contrast between wafer 104 and the surrounding environment based on the wavelengths of light reflecting off the mirrored surface of wafer 104. Specifically, filter 168 transmits light having a wavelength of 600 nanometers (nm) or higher, while absorbing light having a wavelength below 600 nm. Reflections from the surrounding surfaces can have a wavelength below 600 nm, and filter 168 reduces or eliminates the reflections by absorbing light having a wavelength below 600 nm. Reducing or eliminating the reflections enables camera 146 to image wafer 104 rather than light or objects reflected through the wafer.

[0063] Imaging system 110 includes an end effector positioner 174 attached to black box 118 for calibrating a position 176 of end effector 120. After end effector 120 has been calibrated at position 176, end effector positioner 174 is detached from black box 118. End effector positioner 174 includes a black box stand 178, an arm 180, and a positioning disk 182. End effector positioner 174 is attached to black box 118 before imaging system 110 images wafer 104. Positioning disk 182 is attached to arm 180, the arm and positioning disk are attached to black box stand 178, and the arm, positioning disk, and black box stand are attached to black box 118. Black box stand 178 and arm 180 are sized and shaped to position positioning disk 182 below bottom shroud opening 140 within field of view 184 of camera 146. End effector 120 is positioned such that end effector is attached to positioning disk 182, and controller 112 records and calibrates position 176 so that end effector positions wafer 104 at position 176 for each imaging. After position 176 has been calibrated, end effector positioner 174 is detached from black box 118.

[0064] Before manufacturing wafer 104, imaging system 110 is positioned within processing system 100 and calibrated. Specifically, positioning plate 122 is attached to frame 124, and imaging system 110 is attached to the positioning plate. More specifically, black box 118 is attached to positioning plate 122.

[0065] When the imaging system 110 is positioned within the processing system 100 and calibrated, the camera 146 and mirror 148 are positioned and calibrated in the black box 118. Specifically, an operator positions the mirror 148 in the upper chamber 128 of the black box 118 using the mirror positioning system 158. More specifically, the operator attaches the mirror 156 to the mirror holder 164 and attaches the mirror holder and mirror to the base 162. In addition, the operator also attaches the camera 146 to the slide lock 150 and positions the camera and slide lock in the upper chamber 128 of the black box 118. The operator adjusts the slide lock 150, camera 146, and mirror 156 simultaneously to ensure that the field of view 184 of the camera is centered in the bottom shroud opening 140. More specifically, the operator adjusts the screws 166, rotates the mirror holder 164, and slides the camera 146 on the slide lock 150 simultaneously to ensure that the field of view 184 of the camera is centered in the bottom shroud opening 140.

[0066] The operator attaches the end effector positioner 174 to the black box 118 by attaching the positioning disk 182 to the arm 180, attaching the positioning disk and arm to the black box stand 178, and attaching the positioning disk, arm, and black box stand to the black box. The end effector positioner 174 is attached to the black box 118 such that the positioning disk 182 is centered in the bottom shroud opening 140. The operator positions the end effector 120 such that the end effector is directly or indirectly attached to the positioning disk 182. The controller 112 records and calibrates the position 176 of the end effector 120 such that the end effector positions the wafer 104 at the position 176 for each imaging. The operator removes the end effector positioner 174 from the black box 118.

[0067] During operation, the wafer processing system 100 at least partially manufactures the wafer 104. Specifically, in the illustrated embodiment, the dicing station 108 dices the wafer 104 and sends the wafer to the imaging system 110 for imaging. More specifically, after the dicing station 108 dices the wafer 104, the end effector 120 positions the wafer under the bottom shroud opening 140 and the camera 146 generates an image 202 of the wafer (shown in FIG. 2A). A schematic representation 203 of the image 202 is shown in FIG. 2B). The image 202 of the wafer 104 is sent to the controller 112 for analysis, as described below. Figure 14 Figure 13

[0068] Referring to FIGS. 1A and 2A, the imaging system 110 includes a black box 118, a camera 146, a mirror 148, and an end effector positioner 174. The black box 118 includes a bottom shroud opening 140, an upper chamber 128, and a black box stand 178. The camera 146 includes a slide lock 150, a mirror holder 164, a mirror 156, and a field of view 184. The end effector positioner 174 includes a positioning disk 182 and an arm 180. Figure 13 and 14 ​​As shown in image 202 and schematic representation 203 of image 202, wafer 104 includes a base 204 and a transfer layer 206 deposited on the base. Base 204 has a wafer boundary 208 and transfer layer 206 has a transfer layer boundary 210. Wafer boundary 208 and transfer layer boundary 210 define a terrace width 212 therebetween. In addition, wafer 104 includes a notch 222. Controller 112 detects base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210 and terrace width 212 in image 202 and analyzes the detected areas for defects in wafer 104. In addition, as discussed above, the placement of reflector 200 on top surface 196 of transparent plate 190 can create a periodic artifact 214 of regular geometric array in image 202 (shown as a woven pattern on image 202). Specifically, reflector 200 creates a grid pattern of periodic artifact 214 in image 202. The grid pattern of periodic artifact 214 can include a regular spaced periodic array of out-of-focus points, slightly focused points and / or dark points.

[0069] Controller 112 includes a computer program 300 for imaging and analyzing wafers 104. Figure 18 is a diagram of computer program 300 for imaging and analyzing wafers 104. Computer program 300 includes an image capture module 302, a data management module 304 and a data analysis module 306. Image capture module 302 controls semiconductor wafer imaging system 110 to position wafer 104 within bottom shield opening 140, capture an image 202 of the wafer and return the wafer to semiconductor wafer processing system 100 for further processing. Data management module 304 records identification information for each wafer 104, stores image 202 for analysis and informs data analysis module 306 that image 202 is ready for analysis. Data analysis module 306 analyzes image 202, determines whether wafer 104 is acceptable for further processing and removes the wafer from the process as necessary by controlling semiconductor wafer processing system 100.

[0070] Computer program 300 can be a single program including all three modules or multiple programs interfacing with each other. For example, in a first embodiment, computer program 300 is a single program including all three modules. In this embodiment, computer program 300 images and analyzes wafer 104 before another wafer is imaged and analyzed. Modules 302-306 are executed sequentially before another wafer 104 is imaged and analyzed.

[0071] In a second embodiment, the computer program 300 comprises a single process that non-sequentially executes the modules 302-306. For example, in this embodiment, the computer program 300 can sequentially execute the image capture module 302 and the data management module 304, but can not execute the data analysis module 306 until multiple wafers 104 have been imaged, allowing the controller 112 to analyze wafers in batches. If there is an error in the data analysis module 306, the images 202 are saved by the data management module 304 for later analysis.

[0072] In a third embodiment, the computer program 300 comprises multiple programs each comprising one or more modules 302-306. In this embodiment, the modules 302-306 are separated into separate processes so that the modules 302-306 can be executed non-sequentially. For example, a first computer program can comprise the image capture module 302 and the data management module 304, while a second computer program can comprise the data analysis module 306. Further, the first and second computer programs can be executed on different controllers 112 or computing devices, allowing the controllers to execute the image capture module 302 and the data management module 304 without simultaneously analyzing the images 202. If the data analysis module 306 and / or the controller or computing device executing the data analysis module is temporarily unable to perform analysis, the third embodiment allows the process to continue.

[0073] Figures 19 to 21 is a flowchart of a method 400 of imaging and analyzing wafers 104. Each module 302-306 performs specific steps of the method 400, and the modules can be executed non-sequentially. The method 400 comprises imaging 402 a wafer 104 using the semiconductor wafer imaging system 110, as described above. Specifically, imaging 402 a wafer 104 using the semiconductor wafer imaging system 110 comprises positioning 404 the wafer 104 within the bottom shroud opening 140 using the end effector 120, directing 406 diffuse light to the wafer 104 using the illumination panel 144, reflecting 408 the diffuse light off the wafer, and detecting 410 the diffuse light with the camera 146 to produce an image 202 of the wafer.

[0074] The method 400 also comprises storing and transmitting 412 the image. The image 202 is transmitted to the controller 112 and the controller analyzes the image before imaging another wafer 104. Once the image is received from the camera 146, the controller 112 analyzes the image. However, the controller 112 and / or the analysis can create a bottleneck in the process. To reduce manufacturing time, the camera 146 can transmit the image to the controller 112 along with a wafer identification number, and the controller can analyze the image while the wafer 104 continues through the process.

[0075] The method 400 further includes analyzing 414 the wafer 104 using the controller 112 to detect defects on the wafer. The defects can include voids (missing areas within the transfer layer 206 that do not intersect the transfer layer boundary 210), edge voids (missing areas within the transfer layer 206 that intersect the transfer layer boundary 210), asymmetries in the terrace width 212, overlarge and underlarge set recess terrace widths, various metrics of alignment, area, and symmetry of the terrace width, color blobs (darker and / or lighter areas), and / or any other defects within at least one of the pedestals 204, the wafer boundary 208, the transfer layer 206, the transfer layer boundary 210, and the terrace width 212. As discussed above, the placement of the reflector 200 on the top surface 196 of the transparent plate 190 can create a regular geometric array of periodic artifacts 214 in the image 202. To remove or reduce the periodic artifacts 214, analyzing 414 the wafer 104 using the controller 112 to detect defects on the wafer can include applying 416 a software filter to the image 202 to remove or reduce the periodic artifacts 214.

[0076] The software filter includes a fast Fourier transform (FFT) that identifies and removes the periodic artifacts 214 from the image 202. Specifically, because the grid pattern of the periodic artifacts 214 is a regularly spaced periodic array, the FFT breaks down the image 202 into its sine and cosine components and produces an output image 216 (shown in Figure 17 ) in the Fourier or frequency domain when the image 202 is in a spatial domain equivalent. The regular spacing of the grid pattern of the periodic artifacts 214 enables the FFT to identify the periodic artifacts 214 from the image 202. In the output image 216, each point represents a particular frequency contained in the spatial domain image or the image 202. Specifically, the controller 112 produces 418 an original FFT image 218 (shown in Figure 15 ), detects 420 the periodic artifacts 214 in the image 202, removes or reduces 422 the periodic artifacts 214 from the image, and converts 424 the image into the output image 216 (shown in Figure 17 , a schematic representation 217 of the image 216 is shown in Figure 16 ). The software filter improves the image 202 before analyzing the image 202 to detect defects on the wafer 104 because the software filter is not sensitive to translational position variations of the wafer, the diffuser plate, and / or the camera, and is substantially invariant to rotational position variations of the wafer, the diffuser plate, or the camera.

[0077] At high magnification, periodic artifacts 214 resulting from the placement of the reflector 200 on the top surface 196 of the transparent plate 190 are visible. The grid pattern of the periodic artifacts 214 can reduce the accuracy of the results of the analysis 414. When the image 202 is transformed into the frequency domain, the periodic artifacts 214 are represented as high intensity points 228 on the raw FFT image 218. Removing the high intensity points 228 from the raw FFT image 218 and then transforming the raw FFT image 218 back to a spatial domain image, the grid pattern of the periodic artifacts 214 can be removed from the image 202.

[0078] The raw FFT image 218 is generated to enable visualization of the FFT analysis and aspects of the raw FFT image enable visualization of specific aspects of the FFT analysis. For example, the raw FFT image 218 is generated using a conventional FFT method and includes a center point 224 and a pair of perpendicular axes 226. The magnitude of the center point 224 visually represents the period or distance between the periodic artifacts 214 in the image 202. In addition, the raw FFT image 218 also includes high intensity points 228 and the perpendicular axes 226 are aligned with the high intensity points 228. As Figure 14 As shown in the middle, the grid pattern of the periodic artifacts 214 is oriented at an angle. The high intensity points 228 are also oriented at the same angle as the orientation angle of the grid pattern of the periodic artifacts 214, and the pair of perpendicular axes 226 are also oriented at the same angle as the high intensity points 228 and the grid pattern of the periodic artifacts 214. Thus, the raw FFT image 218 enables visualization of the FFT analysis.

[0079] Once the output image 216 has been generated, the controller 112 analyzes the output image to detect defects in the wafer 104. Specifically, the controller 112 detects 426 the pedestals 204, the wafer boundary 208, the transfer layer 206, the transfer layer boundary 210, the step width 212, and the notches 222 in the output image 216. More specifically, the controller 112 detects 428 the wafer boundary 208 by segmenting and isolating the wafer boundary in the output image 216, and detects 430 the transfer layer boundary 210 by segmenting and isolating the transfer layer boundary in the output image 216. The boundaries of the transfer layer 206, the notches 222, and the voids in the transfer layer are segmented using various image processing techniques, including image blurring, gradient calculation, high gradient edge detection, and contour calculation from edge detection. When the boundaries are not clear or blurry, further processing occurs to enhance the edge locations, and in some embodiments where the output image 216 has incomplete or missing edges, an estimate of boundary closure is made if possible. For example, when small edge segments are missing, edge boundary extrapolation can be used, and the detected edges can be smoothed to reduce noise introduced by the edge detection technique. When the controller 112 is unable to estimate closure, the output image 216 is flagged for manual inspection.

[0080] After the pedestal 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 have been detected in the output image 216, the controller 112 analyzes 432 the detected regions for defects. More specifically, the controller 112 analyzes 432 at least one of the pedestal 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 for defects. For example, the controller 112 detects 434 features of at least one of the pedestal 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 and quantifies 436 the detected features into quantified metrics. The controller 112 then compares 438 the quantified metrics to predetermined metrics and detects 440 defects in at least one of the pedestal 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 based on the comparison.

[0081] More specifically, detecting 434 features of at least one of the pedestal 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212 and quantifying 436 the detected features into quantified metrics includes detecting the terrace width 212 and quantifying detected features of the terrace width 212 into various global and local terrace width statistics. For example, in some embodiments, the terrace width 212 is divided into twelve 30° segments around the edge of the wafer 104 and detected features of the terrace width 212 are quantified into local terrace width statistics based on each segment.

[0082] Figure 22 A graphical user interface display 500 used when calibrating the end effector 120 (shown in Figure 12 ) and / or the position of the wafer 104 relative to the camera 146 (shown in Figure 9 ) through the image analysis process is shown. The user interface display 500 shows a captured image 502 of the wafer 104 and centering meters 504-508. To calibrate the end effector 120 and / or the position of the wafer 104 through image analysis, the end effector 120 is positioned below the bottom shroud opening 140 (shown in Figure 5 ) and at least partially within the field of view 184 (shown in Figure 9The camera 146 captures an image 502 of the wafer 104, which is transmitted to the controller 112. The controller 112 then analyzes the captured image 502 of the wafer 104 to determine whether the wafer 104 is within a predefined positioning range and properly centered within the field of view 184. If the controller 112 determines that the wafer is not properly centered within the field of view 184, the position of the wafer 104 and / or the end effector 120 is adjusted based on the determination. After the adjustment, a new image is captured and the controller 112 again determines whether the detected position of the wafer 104 is within the predefined positioning range. The image analysis process can be used with or as an alternative to the centering gauges 504-508 described above with reference to FIG. 5. Figure 12 The described end effector positioner 174 is used together with or as an alternative to the end effector positioner 174 described above with reference to FIG. 4.

[0083] During operation, to determine whether the wafer 104 is properly centered within the field of view 184, the controller 112 captures an image 502 of the wafer 104 and detects the boundaries 208 of the wafer 104, as described above with reference to FIG. 5. Figures 14 to 21 The controller 112 then measures the distances on the captured image 502 between the edges 510-516 of the image 502 and the wafer boundaries 208.

[0084] For example, with respect to positioning along the X-axis, the controller 112 measures a first horizontal distance XI from a first side edge 510 of the captured image 502 to the wafer boundary 208 and a second horizontal distance X2 from a second side edge 512 of the image 502 to the wafer boundary 208. The controller 112 then determines a AX value equal to the difference between the first horizontal distance XI and the second horizontal distance X2. With respect to positioning along the Y-axis, the controller 112 measures a first vertical distance Yl from a bottom edge 514 of the image 502 to the wafer boundary 208 and a second vertical distance Y2 from a top edge 516 of the image 502 to the wafer boundary 208. The controller 112 then determines a AY value equal to the difference between the first vertical distance Yl and the second vertical distance Y2. With respect to positioning along the Z-axis, the controller determines a minimum distance of XI, X2, Yl, and Y2 to determine a minimum clearance of the wafer 104 from the edges 510-516 of the image 502. The controller 112 then compares the determined AX, AY, and minimum clearance values to a predefined tolerance range (e.g., as shown by the centering gauges 504-508) to determine whether further adjustment of the wafer 104 and / or the end effector 120 in the X, Y, or Z direction is needed. Color-coded indicators 520 are provided on or near the image 502 on the user interface 500 to indicate to the technician whether the wafer 104 is centered within the respective ranges along the X, Y, and Z axes. For example, the indicators 520 change color based on whether the corresponding AX, AY, or minimum clearance value is within the corresponding ideal, acceptable, or out-of-bounds range.

[0085] InFigure 22 In embodiments of FIG. 4, the centering gauges 504-508 include an X-axis centering gauge 504, a Y-axis centering gauge 506, and a Z-axis or zoom centering gauge 508. Each of the centering gauges 504-508 indicates an ideal range, an acceptable range, and an out-of-bounds range. The controller 112 maps the determined ΔΧ, ΔΥ, and minimum gap values onto the X-axis centering gauge 504, the Y-axis centering gauge 506, and the Z-axis centering gauge 507, respectively. As shown in FIG. 4, the image 502 has a ΔΥ value of -20 and is within the ideal range of -20 to 20 on the Y-axis centering gauge 506. The minimum gap value is equal to 25 and is within the ideal range of 20 to 40 on the Z-axis centering gauge 508. The ΔΧ value is equal to 130 and is outside of both the ideal range and the acceptable range on the X-axis centering gauge 504. The positioning of the wafer 104 and / or the end effector 120 is then adjusted (e.g., by a technician or by an automated positioning system in communication with the controller 112). In particular, the wafer positioning is adjusted based on the determined values displayed on the centering gauges 504-508. As an example, based on the displayed results from the centering gauges 504-508 as shown in FIG. 4, the technician can move the wafer 104 to the left side of the page (as shown in FIG. 5) to reduce the displayed ΔΧ value. After adjustment, another image is captured and the process is repeated until each of the ΔΧ, ΔΥ, and minimum gap values are all within the acceptable and / or ideal ranges. Figure 22 Figure 22 Figure 22

[0086] The semiconductor wafer imaging system described herein images a wafer during a process to detect defects in the wafer. The imaging system images the wafer after the wafer has been diced to detect defects in the wafer that were formed during the dicing process. If the semiconductor wafer imaging system detects a defect in the wafer, the wafer is removed from the process, reducing the cost of wafer production. The wafer has a reflective, mirror-like surface, and the semiconductor wafer imaging system images the wafer without imaging the light source that reflects off the reflective surface. Specifically, the semiconductor wafer imaging system includes a black box around a camera and an illumination panel. The black box minimizes reflections in the semiconductor wafer imaging system, and the illumination panel directs diffuse light toward the wafer. The diffuse light reflects off the wafer toward the camera. The camera detects the reflected diffuse light, and the illumination panel is not imaged because the light produced by the illumination panel is diffuse. Thus, the camera images the wafer, not the light source, enabling a controller to analyze defects in the wafer and reduce the cost of manufacturing.

[0087] ​​​As used herein, the terms "about," "substantially," "essentially," and "approximately" when used in connection with ranges of dimensions, concentrations, temperatures, or other physical or chemical properties or characteristics, are meant to encompass variations that can exist in the upper and / or lower limits of the ranges, including, for example, experimental error, measurement methods, and other statistical variations.

[0088] When introducing elements of the disclosure or the embodiments thereof, the articles "a," "an," and "the" are intended to mean one or more than one of the elements. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and allow for additional elements. The use of the terms "top," "bottom," "side," and the like, are used for descriptive purposes and do not require any particular orientation of the described item.

[0089] As various changes could be made in the above constructions and methods without departing from the scope of the disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not limiting.

Claims

1. A semiconductor wafer imaging system for imaging semiconductor wafers, the system comprising: The protective panel defines the black box; A camera, positioned inside the black box, is used to image the semiconductor wafer; An illumination panel for directing diffused light onto the semiconductor wafer, wherein a portion of the diffused light is reflected away from the semiconductor wafer and the camera images the semiconductor wafer by detecting the reflected diffused light; and A plane mirror, which is used to reflect the diffused light back to the camera.

2. The system of claim 1, further comprising a controller for analyzing images generated by the camera, wherein the controller detects defects in the semiconductor wafer.

3. The system of claim 1, wherein the shield panel comprises a black anodized aluminum panel to minimize reflections in the black box.

4. The system of claim 1, wherein the shield panel defines an upper chamber and a lower chamber, a support plate separates the upper chamber from the lower chamber, a bottom shield panel at least partially defines the lower chamber and defines a wafer opening, the support plate defines a camera opening, wherein diffused light is transmitted to the semiconductor wafer through the wafer opening, and wherein the reflected diffused light is transmitted from the semiconductor wafer to the camera through the wafer opening and the camera opening.

5. The system of claim 4, wherein the lighting panel is positioned in the lower chamber.

6. The system of claim 4, further comprising an end effector for positioning the semiconductor wafer in the wafer opening.

7. The system of claim 6, further comprising an end effector positioner attached to the black box for calibrating the position of the end effector, wherein the end effector positioner can be detached from the black box after the position of the end effector has been calibrated.

8. The system of claim 4, wherein the camera and the plane mirror are positioned in the upper chamber.

9. The system of claim 8, further comprising a sliding lock attached to the camera for positioning the camera in the upper chamber.

10. The system of claim 8, further comprising a mirror positioning system attached to the plane mirror for positioning the plane mirror in the upper chamber.

11. The system of claim 8, wherein the filter is positioned in the upper chamber and covers the camera opening.

12. The system of claim 8, wherein the filter is attached to the camera and covers the lens of the camera.

13. The system of claim 1, further comprising a positioning plate attached to the black box for positioning the black box.

14. A black box for imaging a semiconductor wafer, the black box comprising: A protective cover panel defines an upper chamber and a lower chamber, a support plate separates the upper chamber and the lower chamber, a bottom protective cover panel at least partially defines the lower chamber and defines a wafer opening, and the support plate defines a camera opening; A camera, positioned in the upper chamber, is used to image the semiconductor wafer; and An illumination panel for guiding diffused light to the semiconductor wafer, wherein the diffused light is transmitted to the semiconductor wafer through an opening in the wafer, and wherein a portion of the diffused light is reflected away from the semiconductor wafer through the opening in the wafer and the opening in the camera, and the camera images the semiconductor wafer by detecting the reflected diffused light.

15. The black box of claim 14, wherein the diffused light is transmitted to the semiconductor wafer through the wafer opening, and wherein the reflected diffused light is transmitted from the semiconductor wafer to the camera through the wafer opening and the camera opening.

16. The black box of claim 14, wherein the lighting panel is positioned in the lower chamber.

17. The black box of claim 14, wherein the camera and the plane mirror are positioned in the upper chamber.

18. The black box of claim 17, further comprising a sliding lock attached to the camera for positioning the camera in the upper chamber.

19. The black box of claim 17, further comprising a mirror positioning system attached to the plane mirror for positioning the plane mirror in the upper chamber.

20. A semiconductor wafer processing system for processing semiconductor wafers, the system comprising: A semiconductor wafer processing station for processing the semiconductor wafers; and A semiconductor wafer imaging system for imaging a semiconductor wafer, wherein the semiconductor wafer imaging system images the semiconductor wafer after the semiconductor wafer has been processed at a semiconductor wafer processing station, the system comprising: A protective panel that defines a black box, wherein one of the protective panels defines a protective opening; A camera, positioned inside the black box, is used to image the semiconductor wafer; An end effector, movable relative to the black box, for positioning the semiconductor wafer aligned with the shield opening and within the field of view of the camera; and An illumination panel, positioned within the black box between the camera and the shroud opening and within the camera's field of view, includes a light source and a reflector for scattering light from the light source to guide diffused light through the shroud opening and onto the semiconductor wafer, wherein a portion of the diffused light is reflected away from the semiconductor wafer and the camera images the semiconductor wafer by detecting the reflected diffused light.

21. The system of claim 20, wherein the semiconductor wafer processing station includes a dicing station and the semiconductor wafer imaging system is positioned above the dicing station.

22. The system of claim 20, wherein the semiconductor wafer processing station includes a dicing station located upstream of the semiconductor wafer imaging system, and wherein the end effector dices the wafer at the dicing station and the camera receives the semiconductor wafer after imaging the diced wafer.

23. The system of claim 20, further comprising a semiconductor wafer imaging station, wherein the semiconductor wafer imaging system is positioned in the semiconductor wafer imaging station, and wherein the illumination panel comprises a transparent plate having a first surface and an opposing second surface, wherein the first surface is textured with an array of reflectors to guide at least a portion of the diffused light through the second surface and to the wafer on the end effector.

24. The system of claim 20, further comprising a frame and a positioning plate attached to the frame, wherein the semiconductor wafer imaging system is attached to the positioning plate.

25. The system of claim 24, wherein the semiconductor wafer imaging system is movably attached to the positioning plate and the position of the semiconductor wafer imaging system is adjusted by adjusting the position of the semiconductor wafer imaging system on the positioning plate.

26. The system of claim 24, wherein the end effector is attached to the frame, and wherein when the wafer is positioned on the end effector, the semiconductor wafer is visible through a direct, unobstructed line of sight from the wafer to the upper chamber, wherein the end effector receives the semiconductor wafer from the semiconductor wafer processing station.

27. A semiconductor wafer processing system for processing semiconductor wafers, the system comprising: A first manufacturing line for processing a first semiconductor wafer and including a first semiconductor wafer processing station for processing the first semiconductor wafer; A second manufacturing line for processing a second semiconductor wafer and including a second semiconductor wafer processing station for processing the second semiconductor wafer, the second manufacturing line intersecting the first manufacturing line at a common location; A semiconductor wafer imaging system for imaging first and second semiconductor wafers and positioning them at a common location where the first and second manufacturing lines intersect, wherein the semiconductor wafer imaging system images the first and second semiconductor wafers after the first and second semiconductor wafer processing stations have processed the first and second semiconductor wafers, the system comprising: A protective panel that defines a black box, wherein one of the protective panels defines a protective opening; A camera, positioned inside the black box, is used to image the semiconductor wafer; An end effector, movable relative to the black box, for positioning the semiconductor wafer aligned with the shield opening and within the field of view of the camera; and An illumination panel, positioned within the black box between the camera and the shroud opening and within the camera's field of view, includes a light source and a reflector for scattering light from the light source to guide diffused light through the shroud opening and onto the semiconductor wafer, wherein a portion of the diffused light is reflected away from the semiconductor wafer and the camera images the semiconductor wafer by detecting the reflected diffused light.

28. The system of claim 27, wherein at least one of the first and second semiconductor wafer processing stations comprises a dicing station, and wherein the dicing station is located upstream of the semiconductor wafer imaging system.

29. The system of claim 27, further comprising a semiconductor wafer imaging station located at the common location where the first and second manufacturing lines intersect, wherein the semiconductor wafer imaging system is located in the semiconductor wafer imaging station.

30. The system of claim 27, further comprising a frame and a positioning plate attached to the frame, wherein the semiconductor wafer imaging system is attached to the positioning plate.

31. The system of claim 30, wherein the semiconductor wafer imaging system is movably attached to the positioning plate and the position of the semiconductor wafer imaging system is adjusted by adjusting the position of the semiconductor wafer imaging system on the positioning plate.

32. The system of claim 30, wherein the end effector is attached to the frame for positioning the first and second semiconductor wafers within the field of view of the camera.

33. The system of claim 32, wherein the end effector receives the semiconductor wafer from at least one of the first and second semiconductor wafer processing stations.

34. The system of claim 27, wherein the semiconductor wafer imaging system is positioned downstream of the first and second semiconductor wafer processing stations and alternates between imaging the first and second semiconductor wafers from the first and second manufacturing lines.

35. A semiconductor wafer imaging station in a semiconductor wafer processing system for imaging semiconductor wafers, the station comprising: frame; A positioning plate, which is attached to the frame; A black box, movably attached to the positioning plate, the black box comprising: A protective panel that defines the black box, wherein one of the protective panels defines a protective opening; A camera, positioned within the black box, is used to image the semiconductor wafer; and An illumination panel, positioned within the black box between the camera and the housing opening and within the camera's field of view, includes a light source and a reflector for scattering light from the light source to guide diffused light through the housing opening and onto the semiconductor wafer, wherein a portion of the diffused light is reflected away from the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light; and An end effector, movable relative to the black box, is used to position the semiconductor wafer aligned with the opening in the shield and within the field of view of the camera.

36. The station according to claim 35, wherein the position of the black box is adjusted by adjusting the position of the black box on the positioning plate.

37. The station of claim 35, wherein the end effector is attached to the frame and positions the semiconductor wafer within the field of view of the camera.

38. The station of claim 35, wherein the lighting panel comprises a transparent plate, and the reflector is positioned on the transparent plate such that the reflector guides diffuse light from the light source through a first surface of the transparent plate, the first surface being oriented toward the shroud opening.

39. The station of claim 38, wherein the transparent plate further includes a second surface and a side edge extending from the first surface to the second surface, the light source being positioned to guide light emitted from the light source through the side edge into the transparent plate and to the reflector, the transparent plate being positioned such that a portion of the diffused light reflected off the semiconductor wafer passes through the first surface and the second surface of the transparent plate and to the camera.

40. A method for detecting defects on a semiconductor wafer, the method comprising: Guide diffused light onto the semiconductor wafer; The diffused light is reflected away from the semiconductor wafer; The diffused light is detected using a camera to generate an image of the semiconductor wafer; and Analyzing the image to detect defects on the semiconductor wafer, wherein analyzing the image to detect defects on the semiconductor wafer includes: The wafer boundary of the semiconductor wafer is detected by segmenting and isolating the wafer boundary in the image; and The transfer layer boundary on the semiconductor wafer is detected by segmenting and isolating the transfer layer boundary in the image.

41. The method of claim 40, wherein analyzing the image to detect defects on the semiconductor wafer further comprises: Analyze the transfer layer of the semiconductor wafer in the image; and Defects in the transfer layer of the semiconductor wafer are detected.

42. The method of claim 40, wherein the wafer boundary and the transfer layer boundary define a step width therebetween, and wherein analyzing the image to detect defects on the semiconductor wafer further includes analyzing the step width to generate step width statistics.

43. The method of claim 40, wherein analyzing the image to detect defects on the semiconductor wafer further comprises quantizing the detected defects into a quantized measure.

44. A method for processing a semiconductor wafer, the method comprising: The semiconductor wafer is cut in a cutting station; Position the semiconductor chip within the camera's field of view; Guide diffused light onto the semiconductor wafer; The diffused light is reflected away from the semiconductor wafer; The camera is used to detect the diffused light to generate an image of the semiconductor wafer; and Analyzing the image to detect defects on the semiconductor wafer, wherein analyzing the image to detect defects on the semiconductor wafer includes: The wafer boundary of the semiconductor wafer is detected by segmenting and isolating the wafer boundary in the image; and The transfer layer boundary on the semiconductor wafer is detected by segmenting and isolating the transfer layer boundary in the image.

45. The method of claim 44, wherein analyzing the image to detect defects on the semiconductor wafer further comprises: Analyze the transfer layer of the semiconductor wafer in the image; and Defects in the transfer layer of the semiconductor wafer are detected.

46. ​​The method of claim 44, wherein the wafer boundary and the transfer layer boundary define a step width therebetween, and wherein analyzing the image to detect defects on the semiconductor wafer further includes analyzing the step width to generate step width statistics.

47. The method of claim 44, wherein analyzing the image to detect defects on the semiconductor wafer further comprises quantizing the detected defects into a quantized measure.

48. A method for processing a semiconductor wafer using a semiconductor wafer processing system, the semiconductor wafer processing system comprising a processing station and a semiconductor wafer imaging station, the method comprising: The semiconductor wafer is processed in the processing station; Position the semiconductor wafer within the field of view of the camera of the semiconductor wafer imaging station; Guide diffused light onto the semiconductor wafer; The diffused light is reflected away from the semiconductor wafer; The camera is used to detect the diffused light to generate an image of the semiconductor wafer; and Analyzing the image to detect defects on the semiconductor wafer, wherein analyzing the image to detect defects on the semiconductor wafer includes: The wafer boundary of the semiconductor wafer is detected by segmenting and isolating the wafer boundary in the image; and The transfer layer boundary on the semiconductor wafer is detected by segmenting and isolating the transfer layer boundary in the image.

49. The method of claim 48, wherein analyzing the image to detect defects on the semiconductor wafer further comprises: Analyze the transfer layer of the semiconductor wafer in the image; and Defects in the transfer layer of the semiconductor wafer are detected.

50. The method of claim 48, wherein the wafer boundary and the transfer layer boundary define a step width therebetween, and wherein analyzing the image to detect defects on the semiconductor wafer further includes analyzing the step width to generate step width statistics.

51. The method of claim 48, wherein analyzing the image to detect defects on the semiconductor wafer further comprises quantizing the detected defects into a quantized measure.

52. A method of processing a semiconductor wafer using a semiconductor wafer processing system, the semiconductor wafer processing system comprising: a first manufacturing line; A second manufacturing line; and a semiconductor wafer imaging station, located at a common location where the first and second manufacturing lines intersect, each of the first and second manufacturing lines including a processing station for processing the semiconductor wafer, the method comprising: i) Processing the first semiconductor wafer in the processing station of the first manufacturing line; ii) Position the first semiconductor wafer within the field of view of the camera of the semiconductor wafer imaging station; iii) Guide the diffused light onto the first semiconductor wafer; iv) Reflect the diffused light away from the first semiconductor wafer; v) Detecting the reflected diffuse light using the camera to generate an image of the first semiconductor wafer; and vi) Analyze the image to detect defects on the first semiconductor wafer; vii) Processing the second semiconductor wafer in the processing station of the second manufacturing line; and viii) Repeat steps ii to vi to image the second semiconductor wafer.

53. The method of claim 52, wherein analyzing the image to detect defects on the first semiconductor wafer comprises: The wafer boundary of the first semiconductor wafer is detected by segmenting and isolating the wafer boundary in the image; and The transfer layer boundary on the first semiconductor wafer is detected by segmenting and isolating the transfer layer boundary in the image.

54. The method of claim 53, wherein analyzing the image to detect defects on the first semiconductor wafer further comprises: Analyze the transfer layer of the first semiconductor wafer in the image; and Defects in the transfer layer of the first semiconductor wafer are detected.

55. The method of claim 53, wherein the wafer boundary and the transfer layer boundary define a step width therebetween, and wherein analyzing the image to detect defects on the first semiconductor wafer further includes analyzing the step width to generate step width statistics.

56. The method of claim 53, wherein analyzing the image to detect defects on the first semiconductor wafer further comprises quantizing the detected defects into a quantized metric.

Images